Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
f96411ab | 2 | /* |
ef3b7d0d | 3 | * rtc-twl.c -- TWL Real Time Clock interface |
f96411ab DB |
4 | * |
5 | * Copyright (C) 2007 MontaVista Software, Inc | |
6 | * Author: Alexandre Rusev <source@mvista.com> | |
7 | * | |
8 | * Based on original TI driver twl4030-rtc.c | |
9 | * Copyright (C) 2006 Texas Instruments, Inc. | |
10 | * | |
11 | * Based on rtc-omap.c | |
12 | * Copyright (C) 2003 MontaVista Software, Inc. | |
13 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
14 | * Copyright (C) 2006 David Brownell | |
f96411ab DB |
15 | */ |
16 | ||
a737e835 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
f96411ab | 19 | #include <linux/kernel.h> |
2fac6674 | 20 | #include <linux/errno.h> |
f96411ab DB |
21 | #include <linux/init.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/rtc.h> | |
25 | #include <linux/bcd.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/interrupt.h> | |
c8a6046e | 28 | #include <linux/of.h> |
f96411ab | 29 | |
a2054256 | 30 | #include <linux/mfd/twl.h> |
f96411ab | 31 | |
e3e7f95b NR |
32 | enum twl_class { |
33 | TWL_4030 = 0, | |
34 | TWL_6030, | |
35 | }; | |
f96411ab DB |
36 | |
37 | /* | |
38 | * RTC block register offsets (use TWL_MODULE_RTC) | |
39 | */ | |
a6b49ffd B |
40 | enum { |
41 | REG_SECONDS_REG = 0, | |
42 | REG_MINUTES_REG, | |
43 | REG_HOURS_REG, | |
44 | REG_DAYS_REG, | |
45 | REG_MONTHS_REG, | |
46 | REG_YEARS_REG, | |
47 | REG_WEEKS_REG, | |
48 | ||
49 | REG_ALARM_SECONDS_REG, | |
50 | REG_ALARM_MINUTES_REG, | |
51 | REG_ALARM_HOURS_REG, | |
52 | REG_ALARM_DAYS_REG, | |
53 | REG_ALARM_MONTHS_REG, | |
54 | REG_ALARM_YEARS_REG, | |
55 | ||
56 | REG_RTC_CTRL_REG, | |
57 | REG_RTC_STATUS_REG, | |
58 | REG_RTC_INTERRUPTS_REG, | |
59 | ||
60 | REG_RTC_COMP_LSB_REG, | |
61 | REG_RTC_COMP_MSB_REG, | |
62 | }; | |
2e84067b | 63 | static const u8 twl4030_rtc_reg_map[] = { |
a6b49ffd B |
64 | [REG_SECONDS_REG] = 0x00, |
65 | [REG_MINUTES_REG] = 0x01, | |
66 | [REG_HOURS_REG] = 0x02, | |
67 | [REG_DAYS_REG] = 0x03, | |
68 | [REG_MONTHS_REG] = 0x04, | |
69 | [REG_YEARS_REG] = 0x05, | |
70 | [REG_WEEKS_REG] = 0x06, | |
71 | ||
72 | [REG_ALARM_SECONDS_REG] = 0x07, | |
73 | [REG_ALARM_MINUTES_REG] = 0x08, | |
74 | [REG_ALARM_HOURS_REG] = 0x09, | |
75 | [REG_ALARM_DAYS_REG] = 0x0A, | |
76 | [REG_ALARM_MONTHS_REG] = 0x0B, | |
77 | [REG_ALARM_YEARS_REG] = 0x0C, | |
78 | ||
79 | [REG_RTC_CTRL_REG] = 0x0D, | |
80 | [REG_RTC_STATUS_REG] = 0x0E, | |
81 | [REG_RTC_INTERRUPTS_REG] = 0x0F, | |
82 | ||
83 | [REG_RTC_COMP_LSB_REG] = 0x10, | |
84 | [REG_RTC_COMP_MSB_REG] = 0x11, | |
85 | }; | |
2e84067b | 86 | static const u8 twl6030_rtc_reg_map[] = { |
a6b49ffd B |
87 | [REG_SECONDS_REG] = 0x00, |
88 | [REG_MINUTES_REG] = 0x01, | |
89 | [REG_HOURS_REG] = 0x02, | |
90 | [REG_DAYS_REG] = 0x03, | |
91 | [REG_MONTHS_REG] = 0x04, | |
92 | [REG_YEARS_REG] = 0x05, | |
93 | [REG_WEEKS_REG] = 0x06, | |
94 | ||
95 | [REG_ALARM_SECONDS_REG] = 0x08, | |
96 | [REG_ALARM_MINUTES_REG] = 0x09, | |
97 | [REG_ALARM_HOURS_REG] = 0x0A, | |
98 | [REG_ALARM_DAYS_REG] = 0x0B, | |
99 | [REG_ALARM_MONTHS_REG] = 0x0C, | |
100 | [REG_ALARM_YEARS_REG] = 0x0D, | |
101 | ||
102 | [REG_RTC_CTRL_REG] = 0x10, | |
103 | [REG_RTC_STATUS_REG] = 0x11, | |
104 | [REG_RTC_INTERRUPTS_REG] = 0x12, | |
105 | ||
106 | [REG_RTC_COMP_LSB_REG] = 0x13, | |
107 | [REG_RTC_COMP_MSB_REG] = 0x14, | |
108 | }; | |
f96411ab DB |
109 | |
110 | /* RTC_CTRL_REG bitfields */ | |
111 | #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01 | |
112 | #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02 | |
113 | #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04 | |
114 | #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08 | |
115 | #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10 | |
116 | #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20 | |
117 | #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40 | |
f3ec434c | 118 | #define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80 |
f96411ab DB |
119 | |
120 | /* RTC_STATUS_REG bitfields */ | |
121 | #define BIT_RTC_STATUS_REG_RUN_M 0x02 | |
122 | #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04 | |
123 | #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08 | |
124 | #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10 | |
125 | #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20 | |
126 | #define BIT_RTC_STATUS_REG_ALARM_M 0x40 | |
127 | #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80 | |
128 | ||
129 | /* RTC_INTERRUPTS_REG bitfields */ | |
130 | #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03 | |
131 | #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04 | |
132 | #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08 | |
133 | ||
134 | ||
135 | /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */ | |
136 | #define ALL_TIME_REGS 6 | |
137 | ||
138 | /*----------------------------------------------------------------------*/ | |
e3e7f95b NR |
139 | struct twl_rtc { |
140 | struct device *dev; | |
141 | struct rtc_device *rtc; | |
142 | u8 *reg_map; | |
143 | /* | |
144 | * Cache the value for timer/alarm interrupts register; this is | |
145 | * only changed by callers holding rtc ops lock (or resume). | |
146 | */ | |
147 | unsigned char rtc_irq_bits; | |
148 | bool wake_enabled; | |
149 | #ifdef CONFIG_PM_SLEEP | |
150 | unsigned char irqstat; | |
151 | #endif | |
152 | enum twl_class class; | |
153 | }; | |
f96411ab DB |
154 | |
155 | /* | |
ef3b7d0d | 156 | * Supports 1 byte read from TWL RTC register. |
f96411ab | 157 | */ |
e3e7f95b | 158 | static int twl_rtc_read_u8(struct twl_rtc *twl_rtc, u8 *data, u8 reg) |
f96411ab DB |
159 | { |
160 | int ret; | |
161 | ||
e3e7f95b | 162 | ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg])); |
f96411ab | 163 | if (ret < 0) |
a737e835 | 164 | pr_err("Could not read TWL register %X - error %d\n", reg, ret); |
f96411ab DB |
165 | return ret; |
166 | } | |
167 | ||
168 | /* | |
ef3b7d0d | 169 | * Supports 1 byte write to TWL RTC registers. |
f96411ab | 170 | */ |
e3e7f95b | 171 | static int twl_rtc_write_u8(struct twl_rtc *twl_rtc, u8 data, u8 reg) |
f96411ab DB |
172 | { |
173 | int ret; | |
174 | ||
e3e7f95b | 175 | ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg])); |
f96411ab | 176 | if (ret < 0) |
a737e835 JP |
177 | pr_err("Could not write TWL register %X - error %d\n", |
178 | reg, ret); | |
f96411ab DB |
179 | return ret; |
180 | } | |
181 | ||
f96411ab | 182 | /* |
a748384b | 183 | * Enable 1/second update and/or alarm interrupts. |
f96411ab | 184 | */ |
e3e7f95b | 185 | static int set_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit) |
f96411ab DB |
186 | { |
187 | unsigned char val; | |
188 | int ret; | |
189 | ||
ce9f6506 | 190 | /* if the bit is set, return from here */ |
e3e7f95b | 191 | if (twl_rtc->rtc_irq_bits & bit) |
ce9f6506 VB |
192 | return 0; |
193 | ||
e3e7f95b | 194 | val = twl_rtc->rtc_irq_bits | bit; |
a748384b | 195 | val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M; |
e3e7f95b | 196 | ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG); |
f96411ab | 197 | if (ret == 0) |
e3e7f95b | 198 | twl_rtc->rtc_irq_bits = val; |
f96411ab DB |
199 | |
200 | return ret; | |
201 | } | |
202 | ||
203 | /* | |
a748384b | 204 | * Disable update and/or alarm interrupts. |
f96411ab | 205 | */ |
e3e7f95b | 206 | static int mask_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit) |
f96411ab DB |
207 | { |
208 | unsigned char val; | |
209 | int ret; | |
210 | ||
ce9f6506 | 211 | /* if the bit is clear, return from here */ |
e3e7f95b | 212 | if (!(twl_rtc->rtc_irq_bits & bit)) |
ce9f6506 VB |
213 | return 0; |
214 | ||
e3e7f95b NR |
215 | val = twl_rtc->rtc_irq_bits & ~bit; |
216 | ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG); | |
f96411ab | 217 | if (ret == 0) |
e3e7f95b | 218 | twl_rtc->rtc_irq_bits = val; |
f96411ab DB |
219 | |
220 | return ret; | |
221 | } | |
222 | ||
ef3b7d0d | 223 | static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled) |
f96411ab | 224 | { |
ae845894 | 225 | struct platform_device *pdev = to_platform_device(dev); |
e3e7f95b | 226 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
ae845894 | 227 | int irq = platform_get_irq(pdev, 0); |
f96411ab DB |
228 | int ret; |
229 | ||
ae845894 | 230 | if (enabled) { |
e3e7f95b NR |
231 | ret = set_rtc_irq_bit(twl_rtc, |
232 | BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); | |
233 | if (device_can_wakeup(dev) && !twl_rtc->wake_enabled) { | |
ae845894 | 234 | enable_irq_wake(irq); |
e3e7f95b | 235 | twl_rtc->wake_enabled = true; |
ae845894 KH |
236 | } |
237 | } else { | |
e3e7f95b NR |
238 | ret = mask_rtc_irq_bit(twl_rtc, |
239 | BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); | |
240 | if (twl_rtc->wake_enabled) { | |
ae845894 | 241 | disable_irq_wake(irq); |
e3e7f95b | 242 | twl_rtc->wake_enabled = false; |
ae845894 KH |
243 | } |
244 | } | |
f96411ab DB |
245 | |
246 | return ret; | |
247 | } | |
248 | ||
f96411ab | 249 | /* |
ef3b7d0d | 250 | * Gets current TWL RTC time and date parameters. |
f96411ab DB |
251 | * |
252 | * The RTC's time/alarm representation is not what gmtime(3) requires | |
253 | * Linux to use: | |
254 | * | |
255 | * - Months are 1..12 vs Linux 0-11 | |
256 | * - Years are 0..99 vs Linux 1900..N (we assume 21st century) | |
257 | */ | |
ef3b7d0d | 258 | static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm) |
f96411ab | 259 | { |
e3e7f95b | 260 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
14591d88 | 261 | unsigned char rtc_data[ALL_TIME_REGS]; |
f96411ab DB |
262 | int ret; |
263 | u8 save_control; | |
f3ec434c | 264 | u8 rtc_control; |
f96411ab | 265 | |
e3e7f95b | 266 | ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG); |
f3ec434c KS |
267 | if (ret < 0) { |
268 | dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret); | |
f96411ab | 269 | return ret; |
f3ec434c KS |
270 | } |
271 | /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */ | |
e3e7f95b | 272 | if (twl_rtc->class == TWL_6030) { |
f3ec434c KS |
273 | if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) { |
274 | save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M; | |
e3e7f95b NR |
275 | ret = twl_rtc_write_u8(twl_rtc, save_control, |
276 | REG_RTC_CTRL_REG); | |
f3ec434c KS |
277 | if (ret < 0) { |
278 | dev_err(dev, "%s clr GET_TIME, error %d\n", | |
279 | __func__, ret); | |
280 | return ret; | |
281 | } | |
282 | } | |
283 | } | |
f96411ab | 284 | |
f3ec434c KS |
285 | /* Copy RTC counting registers to static registers or latches */ |
286 | rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M; | |
f96411ab | 287 | |
f3ec434c | 288 | /* for twl6030/32 enable read access to static shadowed registers */ |
e3e7f95b | 289 | if (twl_rtc->class == TWL_6030) |
f3ec434c KS |
290 | rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT; |
291 | ||
e3e7f95b | 292 | ret = twl_rtc_write_u8(twl_rtc, rtc_control, REG_RTC_CTRL_REG); |
f3ec434c KS |
293 | if (ret < 0) { |
294 | dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret); | |
f96411ab | 295 | return ret; |
f3ec434c | 296 | } |
f96411ab | 297 | |
ef3b7d0d | 298 | ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data, |
e3e7f95b | 299 | (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); |
f96411ab DB |
300 | |
301 | if (ret < 0) { | |
f3ec434c | 302 | dev_err(dev, "%s: reading data, error %d\n", __func__, ret); |
f96411ab DB |
303 | return ret; |
304 | } | |
305 | ||
f3ec434c | 306 | /* for twl6030 restore original state of rtc control register */ |
e3e7f95b NR |
307 | if (twl_rtc->class == TWL_6030) { |
308 | ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG); | |
f3ec434c KS |
309 | if (ret < 0) { |
310 | dev_err(dev, "%s: restore CTRL_REG, error %d\n", | |
311 | __func__, ret); | |
312 | return ret; | |
313 | } | |
314 | } | |
315 | ||
f96411ab DB |
316 | tm->tm_sec = bcd2bin(rtc_data[0]); |
317 | tm->tm_min = bcd2bin(rtc_data[1]); | |
318 | tm->tm_hour = bcd2bin(rtc_data[2]); | |
319 | tm->tm_mday = bcd2bin(rtc_data[3]); | |
320 | tm->tm_mon = bcd2bin(rtc_data[4]) - 1; | |
321 | tm->tm_year = bcd2bin(rtc_data[5]) + 100; | |
322 | ||
323 | return ret; | |
324 | } | |
325 | ||
ef3b7d0d | 326 | static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm) |
f96411ab | 327 | { |
e3e7f95b | 328 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
f96411ab | 329 | unsigned char save_control; |
14591d88 | 330 | unsigned char rtc_data[ALL_TIME_REGS]; |
f96411ab DB |
331 | int ret; |
332 | ||
14591d88 PU |
333 | rtc_data[0] = bin2bcd(tm->tm_sec); |
334 | rtc_data[1] = bin2bcd(tm->tm_min); | |
335 | rtc_data[2] = bin2bcd(tm->tm_hour); | |
336 | rtc_data[3] = bin2bcd(tm->tm_mday); | |
337 | rtc_data[4] = bin2bcd(tm->tm_mon + 1); | |
338 | rtc_data[5] = bin2bcd(tm->tm_year - 100); | |
f96411ab DB |
339 | |
340 | /* Stop RTC while updating the TC registers */ | |
e3e7f95b | 341 | ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG); |
f96411ab DB |
342 | if (ret < 0) |
343 | goto out; | |
344 | ||
345 | save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M; | |
e3e7f95b | 346 | ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG); |
f96411ab DB |
347 | if (ret < 0) |
348 | goto out; | |
349 | ||
350 | /* update all the time registers in one shot */ | |
ef3b7d0d | 351 | ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data, |
e3e7f95b | 352 | (twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS); |
f96411ab DB |
353 | if (ret < 0) { |
354 | dev_err(dev, "rtc_set_time error %d\n", ret); | |
355 | goto out; | |
356 | } | |
357 | ||
358 | /* Start back RTC */ | |
359 | save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M; | |
e3e7f95b | 360 | ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG); |
f96411ab DB |
361 | |
362 | out: | |
363 | return ret; | |
364 | } | |
365 | ||
366 | /* | |
ef3b7d0d | 367 | * Gets current TWL RTC alarm time. |
f96411ab | 368 | */ |
ef3b7d0d | 369 | static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) |
f96411ab | 370 | { |
e3e7f95b | 371 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
14591d88 | 372 | unsigned char rtc_data[ALL_TIME_REGS]; |
f96411ab DB |
373 | int ret; |
374 | ||
ef3b7d0d | 375 | ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data, |
e3e7f95b | 376 | twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS); |
f96411ab DB |
377 | if (ret < 0) { |
378 | dev_err(dev, "rtc_read_alarm error %d\n", ret); | |
379 | return ret; | |
380 | } | |
381 | ||
382 | /* some of these fields may be wildcard/"match all" */ | |
383 | alm->time.tm_sec = bcd2bin(rtc_data[0]); | |
384 | alm->time.tm_min = bcd2bin(rtc_data[1]); | |
385 | alm->time.tm_hour = bcd2bin(rtc_data[2]); | |
386 | alm->time.tm_mday = bcd2bin(rtc_data[3]); | |
387 | alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1; | |
388 | alm->time.tm_year = bcd2bin(rtc_data[5]) + 100; | |
389 | ||
390 | /* report cached alarm enable state */ | |
e3e7f95b | 391 | if (twl_rtc->rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M) |
f96411ab DB |
392 | alm->enabled = 1; |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
ef3b7d0d | 397 | static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) |
f96411ab | 398 | { |
e3e7f95b NR |
399 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
400 | ||
14591d88 | 401 | unsigned char alarm_data[ALL_TIME_REGS]; |
f96411ab DB |
402 | int ret; |
403 | ||
ef3b7d0d | 404 | ret = twl_rtc_alarm_irq_enable(dev, 0); |
f96411ab DB |
405 | if (ret) |
406 | goto out; | |
407 | ||
14591d88 PU |
408 | alarm_data[0] = bin2bcd(alm->time.tm_sec); |
409 | alarm_data[1] = bin2bcd(alm->time.tm_min); | |
410 | alarm_data[2] = bin2bcd(alm->time.tm_hour); | |
411 | alarm_data[3] = bin2bcd(alm->time.tm_mday); | |
412 | alarm_data[4] = bin2bcd(alm->time.tm_mon + 1); | |
413 | alarm_data[5] = bin2bcd(alm->time.tm_year - 100); | |
f96411ab DB |
414 | |
415 | /* update all the alarm registers in one shot */ | |
ef3b7d0d | 416 | ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data, |
e3e7f95b | 417 | twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS); |
f96411ab DB |
418 | if (ret) { |
419 | dev_err(dev, "rtc_set_alarm error %d\n", ret); | |
420 | goto out; | |
421 | } | |
422 | ||
423 | if (alm->enabled) | |
ef3b7d0d | 424 | ret = twl_rtc_alarm_irq_enable(dev, 1); |
f96411ab DB |
425 | out: |
426 | return ret; | |
427 | } | |
428 | ||
e3e7f95b | 429 | static irqreturn_t twl_rtc_interrupt(int irq, void *data) |
f96411ab | 430 | { |
e3e7f95b | 431 | struct twl_rtc *twl_rtc = data; |
2778ebcc | 432 | unsigned long events; |
f96411ab DB |
433 | int ret = IRQ_NONE; |
434 | int res; | |
435 | u8 rd_reg; | |
436 | ||
e3e7f95b | 437 | res = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG); |
f96411ab DB |
438 | if (res) |
439 | goto out; | |
440 | /* | |
441 | * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG. | |
442 | * only one (ALARM or RTC) interrupt source may be enabled | |
443 | * at time, we also could check our results | |
444 | * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM] | |
445 | */ | |
446 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) | |
2778ebcc | 447 | events = RTC_IRQF | RTC_AF; |
f96411ab | 448 | else |
2778ebcc | 449 | events = RTC_IRQF | RTC_PF; |
f96411ab | 450 | |
e3e7f95b NR |
451 | res = twl_rtc_write_u8(twl_rtc, BIT_RTC_STATUS_REG_ALARM_M, |
452 | REG_RTC_STATUS_REG); | |
f96411ab DB |
453 | if (res) |
454 | goto out; | |
455 | ||
e3e7f95b | 456 | if (twl_rtc->class == TWL_4030) { |
a6b49ffd B |
457 | /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1 |
458 | * needs 2 reads to clear the interrupt. One read is done in | |
459 | * do_twl_pwrirq(). Doing the second read, to clear | |
460 | * the bit. | |
461 | * | |
462 | * FIXME the reason PWR_ISR1 needs an extra read is that | |
463 | * RTC_IF retriggered until we cleared REG_ALARM_M above. | |
464 | * But re-reading like this is a bad hack; by doing so we | |
465 | * risk wrongly clearing status for some other IRQ (losing | |
466 | * the interrupt). Be smarter about handling RTC_UF ... | |
467 | */ | |
468 | res = twl_i2c_read_u8(TWL4030_MODULE_INT, | |
f96411ab | 469 | &rd_reg, TWL4030_INT_PWR_ISR1); |
a6b49ffd B |
470 | if (res) |
471 | goto out; | |
472 | } | |
f96411ab DB |
473 | |
474 | /* Notify RTC core on event */ | |
e3e7f95b | 475 | rtc_update_irq(twl_rtc->rtc, 1, events); |
f96411ab DB |
476 | |
477 | ret = IRQ_HANDLED; | |
478 | out: | |
479 | return ret; | |
480 | } | |
481 | ||
34c7b3ac | 482 | static const struct rtc_class_ops twl_rtc_ops = { |
ef3b7d0d B |
483 | .read_time = twl_rtc_read_time, |
484 | .set_time = twl_rtc_set_time, | |
485 | .read_alarm = twl_rtc_read_alarm, | |
486 | .set_alarm = twl_rtc_set_alarm, | |
487 | .alarm_irq_enable = twl_rtc_alarm_irq_enable, | |
f96411ab DB |
488 | }; |
489 | ||
490 | /*----------------------------------------------------------------------*/ | |
491 | ||
5a167f45 | 492 | static int twl_rtc_probe(struct platform_device *pdev) |
f96411ab | 493 | { |
e3e7f95b | 494 | struct twl_rtc *twl_rtc; |
1c02cbfe | 495 | struct device_node *np = pdev->dev.of_node; |
7e72c686 | 496 | int ret = -EINVAL; |
f96411ab DB |
497 | int irq = platform_get_irq(pdev, 0); |
498 | u8 rd_reg; | |
499 | ||
1c02cbfe NR |
500 | if (!np) { |
501 | dev_err(&pdev->dev, "no DT info\n"); | |
502 | return -EINVAL; | |
503 | } | |
504 | ||
2fac6674 | 505 | if (irq <= 0) |
f53eeb85 | 506 | return ret; |
f96411ab | 507 | |
e3e7f95b NR |
508 | twl_rtc = devm_kzalloc(&pdev->dev, sizeof(*twl_rtc), GFP_KERNEL); |
509 | if (!twl_rtc) | |
510 | return -ENOMEM; | |
511 | ||
512 | if (twl_class_is_4030()) { | |
513 | twl_rtc->class = TWL_4030; | |
514 | twl_rtc->reg_map = (u8 *)twl4030_rtc_reg_map; | |
515 | } else if (twl_class_is_6030()) { | |
516 | twl_rtc->class = TWL_6030; | |
517 | twl_rtc->reg_map = (u8 *)twl6030_rtc_reg_map; | |
518 | } else { | |
519 | dev_err(&pdev->dev, "TWL Class not supported.\n"); | |
520 | return -EINVAL; | |
521 | } | |
d3869ff6 | 522 | |
e3e7f95b | 523 | ret = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG); |
f96411ab | 524 | if (ret < 0) |
f53eeb85 | 525 | return ret; |
f96411ab DB |
526 | |
527 | if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M) | |
528 | dev_warn(&pdev->dev, "Power up reset detected.\n"); | |
529 | ||
530 | if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) | |
531 | dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n"); | |
532 | ||
533 | /* Clear RTC Power up reset and pending alarm interrupts */ | |
e3e7f95b | 534 | ret = twl_rtc_write_u8(twl_rtc, rd_reg, REG_RTC_STATUS_REG); |
f96411ab | 535 | if (ret < 0) |
f53eeb85 | 536 | return ret; |
f96411ab | 537 | |
e3e7f95b | 538 | if (twl_rtc->class == TWL_6030) { |
a6b49ffd B |
539 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, |
540 | REG_INT_MSK_LINE_A); | |
541 | twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK, | |
542 | REG_INT_MSK_STS_A); | |
543 | } | |
544 | ||
f7439bcb | 545 | dev_info(&pdev->dev, "Enabling TWL-RTC\n"); |
e3e7f95b NR |
546 | ret = twl_rtc_write_u8(twl_rtc, BIT_RTC_CTRL_REG_STOP_RTC_M, |
547 | REG_RTC_CTRL_REG); | |
f96411ab | 548 | if (ret < 0) |
f53eeb85 | 549 | return ret; |
f96411ab | 550 | |
8dcebaa9 | 551 | /* ensure interrupts are disabled, bootloaders can be strange */ |
e3e7f95b | 552 | ret = twl_rtc_write_u8(twl_rtc, 0, REG_RTC_INTERRUPTS_REG); |
8dcebaa9 KH |
553 | if (ret < 0) |
554 | dev_warn(&pdev->dev, "unable to disable interrupt\n"); | |
555 | ||
f96411ab | 556 | /* init cached IRQ enable bits */ |
e3e7f95b NR |
557 | ret = twl_rtc_read_u8(twl_rtc, &twl_rtc->rtc_irq_bits, |
558 | REG_RTC_INTERRUPTS_REG); | |
f96411ab | 559 | if (ret < 0) |
f53eeb85 | 560 | return ret; |
7e72c686 | 561 | |
e3e7f95b | 562 | platform_set_drvdata(pdev, twl_rtc); |
b99b94b5 GS |
563 | device_init_wakeup(&pdev->dev, 1); |
564 | ||
e3e7f95b | 565 | twl_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
f53eeb85 | 566 | &twl_rtc_ops, THIS_MODULE); |
e3e7f95b | 567 | if (IS_ERR(twl_rtc->rtc)) { |
7e72c686 | 568 | dev_err(&pdev->dev, "can't register RTC device, err %ld\n", |
e3e7f95b NR |
569 | PTR_ERR(twl_rtc->rtc)); |
570 | return PTR_ERR(twl_rtc->rtc); | |
7e72c686 TP |
571 | } |
572 | ||
f53eeb85 JH |
573 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
574 | twl_rtc_interrupt, | |
575 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, | |
e3e7f95b | 576 | dev_name(&twl_rtc->rtc->dev), twl_rtc); |
7e72c686 TP |
577 | if (ret < 0) { |
578 | dev_err(&pdev->dev, "IRQ is not free.\n"); | |
f53eeb85 | 579 | return ret; |
7e72c686 | 580 | } |
f96411ab | 581 | |
7e72c686 | 582 | return 0; |
f96411ab DB |
583 | } |
584 | ||
585 | /* | |
ef3b7d0d | 586 | * Disable all TWL RTC module interrupts. |
f96411ab DB |
587 | * Sets status flag to free. |
588 | */ | |
5a167f45 | 589 | static int twl_rtc_remove(struct platform_device *pdev) |
f96411ab | 590 | { |
e3e7f95b NR |
591 | struct twl_rtc *twl_rtc = platform_get_drvdata(pdev); |
592 | ||
f96411ab | 593 | /* leave rtc running, but disable irqs */ |
e3e7f95b NR |
594 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); |
595 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); | |
596 | if (twl_rtc->class == TWL_6030) { | |
a6b49ffd B |
597 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, |
598 | REG_INT_MSK_LINE_A); | |
599 | twl6030_interrupt_mask(TWL6030_RTC_INT_MASK, | |
600 | REG_INT_MSK_STS_A); | |
601 | } | |
602 | ||
f96411ab DB |
603 | return 0; |
604 | } | |
605 | ||
ef3b7d0d | 606 | static void twl_rtc_shutdown(struct platform_device *pdev) |
f96411ab | 607 | { |
e3e7f95b NR |
608 | struct twl_rtc *twl_rtc = platform_get_drvdata(pdev); |
609 | ||
cafa1d8b MH |
610 | /* mask timer interrupts, but leave alarm interrupts on to enable |
611 | power-on when alarm is triggered */ | |
e3e7f95b | 612 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); |
f96411ab DB |
613 | } |
614 | ||
b9d8c460 | 615 | #ifdef CONFIG_PM_SLEEP |
b9d8c460 | 616 | static int twl_rtc_suspend(struct device *dev) |
f96411ab | 617 | { |
e3e7f95b | 618 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
f96411ab | 619 | |
e3e7f95b NR |
620 | twl_rtc->irqstat = twl_rtc->rtc_irq_bits; |
621 | ||
622 | mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); | |
f96411ab DB |
623 | return 0; |
624 | } | |
625 | ||
b9d8c460 | 626 | static int twl_rtc_resume(struct device *dev) |
f96411ab | 627 | { |
e3e7f95b NR |
628 | struct twl_rtc *twl_rtc = dev_get_drvdata(dev); |
629 | ||
630 | set_rtc_irq_bit(twl_rtc, twl_rtc->irqstat); | |
f96411ab DB |
631 | return 0; |
632 | } | |
f96411ab DB |
633 | #endif |
634 | ||
b9d8c460 JH |
635 | static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume); |
636 | ||
948170f8 BC |
637 | static const struct of_device_id twl_rtc_of_match[] = { |
638 | {.compatible = "ti,twl4030-rtc", }, | |
639 | { }, | |
640 | }; | |
641 | MODULE_DEVICE_TABLE(of, twl_rtc_of_match); | |
f96411ab DB |
642 | |
643 | static struct platform_driver twl4030rtc_driver = { | |
ef3b7d0d | 644 | .probe = twl_rtc_probe, |
5a167f45 | 645 | .remove = twl_rtc_remove, |
ef3b7d0d | 646 | .shutdown = twl_rtc_shutdown, |
f96411ab | 647 | .driver = { |
948170f8 | 648 | .name = "twl_rtc", |
b9d8c460 | 649 | .pm = &twl_rtc_pm_ops, |
1c02cbfe | 650 | .of_match_table = twl_rtc_of_match, |
f96411ab DB |
651 | }, |
652 | }; | |
653 | ||
5ee67484 | 654 | module_platform_driver(twl4030rtc_driver); |
f96411ab DB |
655 | |
656 | MODULE_AUTHOR("Texas Instruments, MontaVista Software"); | |
657 | MODULE_LICENSE("GPL"); |