[linux-2.6-block.git] / drivers / rtc / rtc-tegra.c

/*
 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
 *
 * Copyright (c) 2010, NVIDIA Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/rtc.h>
#include <linux/slab.h>

/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
#define TEGRA_RTC_REG_BUSY			0x004
#define TEGRA_RTC_REG_SECONDS			0x008
/* when msec is read, the seconds are buffered into shadow seconds. */
#define TEGRA_RTC_REG_SHADOW_SECONDS		0x00c
#define TEGRA_RTC_REG_MILLI_SECONDS		0x010
#define TEGRA_RTC_REG_SECONDS_ALARM0		0x014
#define TEGRA_RTC_REG_SECONDS_ALARM1		0x018
#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0	0x01c
#define TEGRA_RTC_REG_INTR_MASK			0x028
/* write 1 bits to clear status bits */
#define TEGRA_RTC_REG_INTR_STATUS		0x02c

/* bits in INTR_MASK */
#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM	(1<<4)
#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM	(1<<3)
#define TEGRA_RTC_INTR_MASK_MSEC_ALARM		(1<<2)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM1		(1<<1)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM0		(1<<0)

/* bits in INTR_STATUS */
#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM	(1<<4)
#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM	(1<<3)
#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM	(1<<2)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1	(1<<1)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0	(1<<0)

struct tegra_rtc_info {
	struct platform_device	*pdev;
	struct rtc_device	*rtc_dev;
	void __iomem		*rtc_base; /* NULL if not initialized. */
	struct clk		*clk;
	int			tegra_rtc_irq; /* alarm and periodic irq */
	spinlock_t		tegra_rtc_lock;
};

/* RTC hardware is busy when it is updating its values over AHB once
 * every eight 32kHz clocks (~250uS).
 * outside of these updates the CPU is free to write.
 * CPU is always free to read.
 */
static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
{
	return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
}

/* Wait for hardware to be ready for writing.
 * This function tries to maximize the amount of time before the next update.
 * It does this by waiting for the RTC to become busy with its periodic update,
 * then returning once the RTC first becomes not busy.
 * This periodic update (where the seconds and milliseconds are copied to the
 * AHB side) occurs every eight 32kHz clocks (~250uS).
 * The behavior of this function allows us to make some assumptions without
 * introducing a race, because 250uS is plenty of time to read/write a value.
 */
static int tegra_rtc_wait_while_busy(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	int retries = 500; /* ~490 us is the worst case, ~250 us is best. */

	/* first wait for the RTC to become busy. this is when it
	 * posts its updated seconds+msec registers to AHB side. */
	while (tegra_rtc_check_busy(info)) {
		if (!retries--)
			goto retry_failed;
		udelay(1);
	}

	/* now we have about 250 us to manipulate registers */
	return 0;

retry_failed:
	dev_err(dev, "write failed:retry count exceeded.\n");
	return -ETIMEDOUT;
}

static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec, msec;
	unsigned long sl_irq_flags;

	/* RTC hardware copies seconds to shadow seconds when a read
	 * of milliseconds occurs. use a lock to keep other threads out. */
	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);

	msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
	sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);

	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);

	rtc_time_to_tm(sec, tm);

	dev_vdbg(dev, "time read as %lu. %ptR\n", sec, tm);

	return 0;
}

static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec;
	int ret;

	/* convert tm to seconds. */
	rtc_tm_to_time(tm, &sec);

	dev_vdbg(dev, "time set to %lu. %ptR\n", sec, tm);

	/* seconds only written if wait succeeded. */
	ret = tegra_rtc_wait_while_busy(dev);
	if (!ret)
		writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);

	dev_vdbg(dev, "time read back as %d\n",
		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));

	return ret;
}

static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec;
	unsigned tmp;

	sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);

	if (sec == 0) {
		/* alarm is disabled. */
		alarm->enabled = 0;
	} else {
		/* alarm is enabled. */
		alarm->enabled = 1;
		rtc_time_to_tm(sec, &alarm->time);
	}

	tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;

	return 0;
}

static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned status;
	unsigned long sl_irq_flags;

	tegra_rtc_wait_while_busy(dev);
	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);

	/* read the original value, and OR in the flag. */
	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	if (enabled)
		status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
	else
		status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */

	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);

	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);

	return 0;
}

static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec;

	if (alarm->enabled)
		rtc_tm_to_time(&alarm->time, &sec);
	else
		sec = 0;

	tegra_rtc_wait_while_busy(dev);
	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	dev_vdbg(dev, "alarm read back as %d\n",
		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));

	/* if successfully written and alarm is enabled ... */
	if (sec) {
		tegra_rtc_alarm_irq_enable(dev, 1);
		dev_vdbg(dev, "alarm set as %lu. %ptR\n", sec, &alarm->time);
	} else {
		/* disable alarm if 0 or write error. */
		dev_vdbg(dev, "alarm disabled\n");
		tegra_rtc_alarm_irq_enable(dev, 0);
	}

	return 0;
}

static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
{
	if (!dev || !dev->driver)
		return 0;

	seq_printf(seq, "name\t\t: %s\n", dev_name(dev));

	return 0;
}

static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
{
	struct device *dev = data;
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long events = 0;
	unsigned status;
	unsigned long sl_irq_flags;

	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	if (status) {
		/* clear the interrupt masks and status on any irq. */
		tegra_rtc_wait_while_busy(dev);
		spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
		writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
		writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
		spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	}

	/* check if Alarm */
	if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
		events |= RTC_IRQF | RTC_AF;

	/* check if Periodic */
	if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
		events |= RTC_IRQF | RTC_PF;

	rtc_update_irq(info->rtc_dev, 1, events);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops tegra_rtc_ops = {
	.read_time	= tegra_rtc_read_time,
	.set_time	= tegra_rtc_set_time,
	.read_alarm	= tegra_rtc_read_alarm,
	.set_alarm	= tegra_rtc_set_alarm,
	.proc		= tegra_rtc_proc,
	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
};

static const struct of_device_id tegra_rtc_dt_match[] = {
	{ .compatible = "nvidia,tegra20-rtc", },
	{}
};
MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);

static int __init tegra_rtc_probe(struct platform_device *pdev)
{
	struct tegra_rtc_info *info;
	struct resource *res;
	int ret;

	info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
		GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(info->rtc_base))
		return PTR_ERR(info->rtc_base);

	ret = platform_get_irq(pdev, 0);
	if (ret <= 0) {
		dev_err(&pdev->dev, "failed to get platform IRQ: %d\n", ret);
		return ret;
	}

	info->tegra_rtc_irq = ret;

	info->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(info->clk))
		return PTR_ERR(info->clk);

	ret = clk_prepare_enable(info->clk);
	if (ret < 0)
		return ret;

	/* set context info. */
	info->pdev = pdev;
	spin_lock_init(&info->tegra_rtc_lock);

	platform_set_drvdata(pdev, info);

	/* clear out the hardware. */
	writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);

	device_init_wakeup(&pdev->dev, 1);

	info->rtc_dev = devm_rtc_device_register(&pdev->dev,
				dev_name(&pdev->dev), &tegra_rtc_ops,
				THIS_MODULE);
	if (IS_ERR(info->rtc_dev)) {
		ret = PTR_ERR(info->rtc_dev);
		dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
			ret);
		goto disable_clk;
	}

	ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
			tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
			dev_name(&pdev->dev), &pdev->dev);
	if (ret) {
		dev_err(&pdev->dev,
			"Unable to request interrupt for device (err=%d).\n",
			ret);
		goto disable_clk;
	}

	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");

	return 0;

disable_clk:
	clk_disable_unprepare(info->clk);
	return ret;
}

static int tegra_rtc_remove(struct platform_device *pdev)
{
	struct tegra_rtc_info *info = platform_get_drvdata(pdev);

	clk_disable_unprepare(info->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int tegra_rtc_suspend(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	tegra_rtc_wait_while_busy(dev);

	/* only use ALARM0 as a wake source. */
	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
		info->rtc_base + TEGRA_RTC_REG_INTR_MASK);

	dev_vdbg(dev, "alarm sec = %d\n",
		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));

	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
		device_may_wakeup(dev), info->tegra_rtc_irq);

	/* leave the alarms on as a wake source. */
	if (device_may_wakeup(dev))
		enable_irq_wake(info->tegra_rtc_irq);

	return 0;
}

static int tegra_rtc_resume(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
		device_may_wakeup(dev));
	/* alarms were left on as a wake source, turn them off. */
	if (device_may_wakeup(dev))
		disable_irq_wake(info->tegra_rtc_irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);

static void tegra_rtc_shutdown(struct platform_device *pdev)
{
	dev_vdbg(&pdev->dev, "disabling interrupts.\n");
	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
}

MODULE_ALIAS("platform:tegra_rtc");
static struct platform_driver tegra_rtc_driver = {
	.remove		= tegra_rtc_remove,
	.shutdown	= tegra_rtc_shutdown,
	.driver		= {
		.name	= "tegra_rtc",
		.of_match_table = tegra_rtc_dt_match,
		.pm	= &tegra_rtc_pm_ops,
	},
};

module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);

MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
MODULE_DESCRIPTION("driver for Tegra internal RTC");
MODULE_LICENSE("GPL");
Commit	Line	Data
ff859ba6 AC	1	/*
	2	* An RTC driver for the NVIDIA Tegra 200 series internal RTC.
	3	*
	4	* Copyright (c) 2010, NVIDIA Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	19	*/
0ae20595	20
5fa40869	21	#include <linux/clk.h>
0ae20595	22	#include <linux/delay.h>
ff859ba6	23	#include <linux/init.h>
ff859ba6	24	#include <linux/io.h>
0ae20595 TR	25	#include <linux/irq.h>
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
ac316725	28	#include <linux/mod_devicetable.h>
ff859ba6	29	#include <linux/platform_device.h>
3443ad09	30	#include <linux/pm.h>
0ae20595 TR	31	#include <linux/rtc.h>
0ae20595 TR	32	#include <linux/slab.h>
ff859ba6 AC	33
	34	/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
	35	#define TEGRA_RTC_REG_BUSY 0x004
	36	#define TEGRA_RTC_REG_SECONDS 0x008
	37	/* when msec is read, the seconds are buffered into shadow seconds. */
	38	#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
	39	#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
	40	#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
	41	#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
	42	#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
	43	#define TEGRA_RTC_REG_INTR_MASK 0x028
	44	/* write 1 bits to clear status bits */
	45	#define TEGRA_RTC_REG_INTR_STATUS 0x02c
	46
	47	/* bits in INTR_MASK */
	48	#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
	49	#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
	50	#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
	51	#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
	52	#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
	53
	54	/* bits in INTR_STATUS */
	55	#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
	56	#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
	57	#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
	58	#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
	59	#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
	60
	61	struct tegra_rtc_info {
	62	struct platform_device *pdev;
	63	struct rtc_device *rtc_dev;
	64	void __iomem rtc_base; / NULL if not initialized. */
5fa40869	65	struct clk *clk;
ff859ba6 AC	66	int tegra_rtc_irq; /* alarm and periodic irq */
	67	spinlock_t tegra_rtc_lock;
	68	};
	69
	70	/* RTC hardware is busy when it is updating its values over AHB once
	71	* every eight 32kHz clocks (~250uS).
	72	* outside of these updates the CPU is free to write.
	73	* CPU is always free to read.
	74	*/
	75	static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
	76	{
	77	return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
	78	}
	79
	80	/* Wait for hardware to be ready for writing.
	81	* This function tries to maximize the amount of time before the next update.
	82	* It does this by waiting for the RTC to become busy with its periodic update,
	83	* then returning once the RTC first becomes not busy.
	84	* This periodic update (where the seconds and milliseconds are copied to the
	85	* AHB side) occurs every eight 32kHz clocks (~250uS).
	86	* The behavior of this function allows us to make some assumptions without
	87	* introducing a race, because 250uS is plenty of time to read/write a value.
	88	*/
	89	static int tegra_rtc_wait_while_busy(struct device *dev)
	90	{
	91	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	92
	93	int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
	94
	95	/* first wait for the RTC to become busy. this is when it
	96	* posts its updated seconds+msec registers to AHB side. */
	97	while (tegra_rtc_check_busy(info)) {
	98	if (!retries--)
	99	goto retry_failed;
	100	udelay(1);
	101	}
	102
	103	/* now we have about 250 us to manipulate registers */
	104	return 0;
	105
	106	retry_failed:
	107	dev_err(dev, "write failed:retry count exceeded.\n");
	108	return -ETIMEDOUT;
	109	}
	110
	111	static int tegra_rtc_read_time(struct device dev, struct rtc_time tm)
	112	{
	113	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	114	unsigned long sec, msec;
	115	unsigned long sl_irq_flags;
	116
	117	/* RTC hardware copies seconds to shadow seconds when a read
	118	* of milliseconds occurs. use a lock to keep other threads out. */
	119	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
	120
	121	msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
	122	sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
	123
	124	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	125
	126	rtc_time_to_tm(sec, tm);
	127
d54fb486	128	dev_vdbg(dev, "time read as %lu. %ptR\n", sec, tm);
ff859ba6 AC	129
	130	return 0;
	131	}
	132
	133	static int tegra_rtc_set_time(struct device dev, struct rtc_time tm)
	134	{
	135	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	136	unsigned long sec;
	137	int ret;
	138
	139	/* convert tm to seconds. */
ff859ba6 AC	140	rtc_tm_to_time(tm, &sec);
ff859ba6 AC	141
d54fb486	142	dev_vdbg(dev, "time set to %lu. %ptR\n", sec, tm);
ff859ba6 AC	143
	144	/* seconds only written if wait succeeded. */
	145	ret = tegra_rtc_wait_while_busy(dev);
	146	if (!ret)
	147	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
	148
	149	dev_vdbg(dev, "time read back as %d\n",
	150	readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
	151
	152	return ret;
	153	}
	154
	155	static int tegra_rtc_read_alarm(struct device dev, struct rtc_wkalrm alarm)
	156	{
	157	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	158	unsigned long sec;
	159	unsigned tmp;
	160
	161	sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	162
	163	if (sec == 0) {
	164	/* alarm is disabled. */
	165	alarm->enabled = 0;
ff859ba6 AC	166	} else {
	167	/* alarm is enabled. */
	168	alarm->enabled = 1;
	169	rtc_time_to_tm(sec, &alarm->time);
	170	}
	171
	172	tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	173	alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
	174
	175	return 0;
	176	}
	177
	178	static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	179	{
	180	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	181	unsigned status;
	182	unsigned long sl_irq_flags;
	183
	184	tegra_rtc_wait_while_busy(dev);
	185	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
	186
	187	/* read the original value, and OR in the flag. */
	188	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	189	if (enabled)
	190	status \|= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
	191	else
	192	status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
	193
	194	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	195
	196	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	197
	198	return 0;
	199	}
	200
	201	static int tegra_rtc_set_alarm(struct device dev, struct rtc_wkalrm alarm)
	202	{
	203	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	204	unsigned long sec;
	205
	206	if (alarm->enabled)
	207	rtc_tm_to_time(&alarm->time, &sec);
	208	else
	209	sec = 0;
	210
	211	tegra_rtc_wait_while_busy(dev);
	212	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	213	dev_vdbg(dev, "alarm read back as %d\n",
	214	readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
	215
	216	/* if successfully written and alarm is enabled ... */
	217	if (sec) {
	218	tegra_rtc_alarm_irq_enable(dev, 1);
d54fb486	219	dev_vdbg(dev, "alarm set as %lu. %ptR\n", sec, &alarm->time);
ff859ba6 AC	220	} else {
	221	/* disable alarm if 0 or write error. */
	222	dev_vdbg(dev, "alarm disabled\n");
	223	tegra_rtc_alarm_irq_enable(dev, 0);
	224	}
	225
	226	return 0;
	227	}
	228
	229	static int tegra_rtc_proc(struct device dev, struct seq_file seq)
	230	{
	231	if (!dev \|\| !dev->driver)
	232	return 0;
	233
4395eb1f JP	234	seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
	235
	236	return 0;
ff859ba6 AC	237	}
	238
	239	static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
	240	{
	241	struct device *dev = data;
	242	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	243	unsigned long events = 0;
	244	unsigned status;
	245	unsigned long sl_irq_flags;
	246
	247	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	248	if (status) {
	249	/* clear the interrupt masks and status on any irq. */
	250	tegra_rtc_wait_while_busy(dev);
	251	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
	252	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	253	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	254	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	255	}
	256
	257	/* check if Alarm */
	258	if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
	259	events \|= RTC_IRQF \| RTC_AF;
	260
	261	/* check if Periodic */
	262	if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
	263	events \|= RTC_IRQF \| RTC_PF;
	264
	265	rtc_update_irq(info->rtc_dev, 1, events);
	266
	267	return IRQ_HANDLED;
	268	}
	269
34c7b3ac	270	static const struct rtc_class_ops tegra_rtc_ops = {
ff859ba6 AC	271	.read_time = tegra_rtc_read_time,
	272	.set_time = tegra_rtc_set_time,
	273	.read_alarm = tegra_rtc_read_alarm,
	274	.set_alarm = tegra_rtc_set_alarm,
	275	.proc = tegra_rtc_proc,
	276	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
	277	};
	278
2d79cf8a JL	279	static const struct of_device_id tegra_rtc_dt_match[] = {
	280	{ .compatible = "nvidia,tegra20-rtc", },
	281	{}
	282	};
	283	MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
	284
51b38c62	285	static int __init tegra_rtc_probe(struct platform_device *pdev)
ff859ba6 AC	286	{
	287	struct tegra_rtc_info *info;
	288	struct resource *res;
	289	int ret;
	290
621bae79 HH	291	info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
621bae79 HH	292	GFP_KERNEL);
ff859ba6 AC	293	if (!info)
	294	return -ENOMEM;
	295
	296	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cbce1e5 TR	297	info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
	298	if (IS_ERR(info->rtc_base))
	299	return PTR_ERR(info->rtc_base);
ff859ba6	300
fe0b5ced TR	301	ret = platform_get_irq(pdev, 0);
	302	if (ret <= 0) {
	303	dev_err(&pdev->dev, "failed to get platform IRQ: %d\n", ret);
	304	return ret;
	305	}
	306
	307	info->tegra_rtc_irq = ret;
ff859ba6	308
5fa40869 TR	309	info->clk = devm_clk_get(&pdev->dev, NULL);
	310	if (IS_ERR(info->clk))
	311	return PTR_ERR(info->clk);
	312
	313	ret = clk_prepare_enable(info->clk);
	314	if (ret < 0)
	315	return ret;
	316
ff859ba6 AC	317	/* set context info. */
ff859ba6 AC	318	info->pdev = pdev;
e57ee017	319	spin_lock_init(&info->tegra_rtc_lock);
ff859ba6 AC	320
	321	platform_set_drvdata(pdev, info);
	322
	323	/* clear out the hardware. */
	324	writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	325	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	326	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	327
	328	device_init_wakeup(&pdev->dev, 1);
	329
68567112 LD	330	info->rtc_dev = devm_rtc_device_register(&pdev->dev,
	331	dev_name(&pdev->dev), &tegra_rtc_ops,
	332	THIS_MODULE);
ff859ba6 AC	333	if (IS_ERR(info->rtc_dev)) {
ff859ba6 AC	334	ret = PTR_ERR(info->rtc_dev);
68567112	335	dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
ff859ba6	336	ret);
5fa40869	337	goto disable_clk;
ff859ba6 AC	338	}
ff859ba6 AC	339
621bae79 HH	340	ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
621bae79 HH	341	tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
57bff981	342	dev_name(&pdev->dev), &pdev->dev);
ff859ba6 AC	343	if (ret) {
	344	dev_err(&pdev->dev,
	345	"Unable to request interrupt for device (err=%d).\n",
	346	ret);
5fa40869	347	goto disable_clk;
ff859ba6 AC	348	}
	349
	350	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
	351
5fa40869 TR	352	return 0;
	353
	354	disable_clk:
	355	clk_disable_unprepare(info->clk);
	356	return ret;
	357	}
	358
	359	static int tegra_rtc_remove(struct platform_device *pdev)
	360	{
	361	struct tegra_rtc_info *info = platform_get_drvdata(pdev);
	362
	363	clk_disable_unprepare(info->clk);
	364
ff859ba6 AC	365	return 0;
	366	}
	367
38a6276e	368	#ifdef CONFIG_PM_SLEEP
3443ad09	369	static int tegra_rtc_suspend(struct device *dev)
ff859ba6	370	{
3443ad09	371	struct tegra_rtc_info *info = dev_get_drvdata(dev);
ff859ba6 AC	372
	373	tegra_rtc_wait_while_busy(dev);
	374
	375	/* only use ALARM0 as a wake source. */
	376	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	377	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
	378	info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	379
	380	dev_vdbg(dev, "alarm sec = %d\n",
	381	readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
	382
	383	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
	384	device_may_wakeup(dev), info->tegra_rtc_irq);
	385
	386	/* leave the alarms on as a wake source. */
	387	if (device_may_wakeup(dev))
	388	enable_irq_wake(info->tegra_rtc_irq);
	389
	390	return 0;
	391	}
	392
3443ad09	393	static int tegra_rtc_resume(struct device *dev)
ff859ba6	394	{
3443ad09	395	struct tegra_rtc_info *info = dev_get_drvdata(dev);
ff859ba6 AC	396
	397	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
	398	device_may_wakeup(dev));
	399	/* alarms were left on as a wake source, turn them off. */
	400	if (device_may_wakeup(dev))
	401	disable_irq_wake(info->tegra_rtc_irq);
	402
	403	return 0;
	404	}
	405	#endif
	406
3443ad09 LD	407	static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
3443ad09 LD	408
ff859ba6 AC	409	static void tegra_rtc_shutdown(struct platform_device *pdev)
	410	{
	411	dev_vdbg(&pdev->dev, "disabling interrupts.\n");
	412	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
	413	}
	414
	415	MODULE_ALIAS("platform:tegra_rtc");
	416	static struct platform_driver tegra_rtc_driver = {
5fa40869	417	.remove = tegra_rtc_remove,
ff859ba6 AC	418	.shutdown = tegra_rtc_shutdown,
	419	.driver = {
	420	.name = "tegra_rtc",
2d79cf8a	421	.of_match_table = tegra_rtc_dt_match,
3443ad09	422	.pm = &tegra_rtc_pm_ops,
ff859ba6	423	},
ff859ba6 AC	424	};
ff859ba6 AC	425
0e2c481d	426	module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
ff859ba6 AC	427
	428	MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
	429	MODULE_DESCRIPTION("driver for Tegra internal RTC");
	430	MODULE_LICENSE("GPL");