Commit | Line | Data |
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ff859ba6 AC |
1 | /* |
2 | * An RTC driver for the NVIDIA Tegra 200 series internal RTC. | |
3 | * | |
4 | * Copyright (c) 2010, NVIDIA Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/rtc.h> | |
28 | #include <linux/platform_device.h> | |
3443ad09 | 29 | #include <linux/pm.h> |
ff859ba6 AC |
30 | |
31 | /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */ | |
32 | #define TEGRA_RTC_REG_BUSY 0x004 | |
33 | #define TEGRA_RTC_REG_SECONDS 0x008 | |
34 | /* when msec is read, the seconds are buffered into shadow seconds. */ | |
35 | #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c | |
36 | #define TEGRA_RTC_REG_MILLI_SECONDS 0x010 | |
37 | #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014 | |
38 | #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018 | |
39 | #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c | |
40 | #define TEGRA_RTC_REG_INTR_MASK 0x028 | |
41 | /* write 1 bits to clear status bits */ | |
42 | #define TEGRA_RTC_REG_INTR_STATUS 0x02c | |
43 | ||
44 | /* bits in INTR_MASK */ | |
45 | #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4) | |
46 | #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3) | |
47 | #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2) | |
48 | #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1) | |
49 | #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0) | |
50 | ||
51 | /* bits in INTR_STATUS */ | |
52 | #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4) | |
53 | #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3) | |
54 | #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2) | |
55 | #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1) | |
56 | #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0) | |
57 | ||
58 | struct tegra_rtc_info { | |
59 | struct platform_device *pdev; | |
60 | struct rtc_device *rtc_dev; | |
61 | void __iomem *rtc_base; /* NULL if not initialized. */ | |
62 | int tegra_rtc_irq; /* alarm and periodic irq */ | |
63 | spinlock_t tegra_rtc_lock; | |
64 | }; | |
65 | ||
66 | /* RTC hardware is busy when it is updating its values over AHB once | |
67 | * every eight 32kHz clocks (~250uS). | |
68 | * outside of these updates the CPU is free to write. | |
69 | * CPU is always free to read. | |
70 | */ | |
71 | static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info) | |
72 | { | |
73 | return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1; | |
74 | } | |
75 | ||
76 | /* Wait for hardware to be ready for writing. | |
77 | * This function tries to maximize the amount of time before the next update. | |
78 | * It does this by waiting for the RTC to become busy with its periodic update, | |
79 | * then returning once the RTC first becomes not busy. | |
80 | * This periodic update (where the seconds and milliseconds are copied to the | |
81 | * AHB side) occurs every eight 32kHz clocks (~250uS). | |
82 | * The behavior of this function allows us to make some assumptions without | |
83 | * introducing a race, because 250uS is plenty of time to read/write a value. | |
84 | */ | |
85 | static int tegra_rtc_wait_while_busy(struct device *dev) | |
86 | { | |
87 | struct tegra_rtc_info *info = dev_get_drvdata(dev); | |
88 | ||
89 | int retries = 500; /* ~490 us is the worst case, ~250 us is best. */ | |
90 | ||
91 | /* first wait for the RTC to become busy. this is when it | |
92 | * posts its updated seconds+msec registers to AHB side. */ | |
93 | while (tegra_rtc_check_busy(info)) { | |
94 | if (!retries--) | |
95 | goto retry_failed; | |
96 | udelay(1); | |
97 | } | |
98 | ||
99 | /* now we have about 250 us to manipulate registers */ | |
100 | return 0; | |
101 | ||
102 | retry_failed: | |
103 | dev_err(dev, "write failed:retry count exceeded.\n"); | |
104 | return -ETIMEDOUT; | |
105 | } | |
106 | ||
107 | static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
108 | { | |
109 | struct tegra_rtc_info *info = dev_get_drvdata(dev); | |
110 | unsigned long sec, msec; | |
111 | unsigned long sl_irq_flags; | |
112 | ||
113 | /* RTC hardware copies seconds to shadow seconds when a read | |
114 | * of milliseconds occurs. use a lock to keep other threads out. */ | |
115 | spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); | |
116 | ||
117 | msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS); | |
118 | sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS); | |
119 | ||
120 | spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); | |
121 | ||
122 | rtc_time_to_tm(sec, tm); | |
123 | ||
124 | dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n", | |
125 | sec, | |
126 | tm->tm_mon + 1, | |
127 | tm->tm_mday, | |
128 | tm->tm_year + 1900, | |
129 | tm->tm_hour, | |
130 | tm->tm_min, | |
131 | tm->tm_sec | |
132 | ); | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
138 | { | |
139 | struct tegra_rtc_info *info = dev_get_drvdata(dev); | |
140 | unsigned long sec; | |
141 | int ret; | |
142 | ||
143 | /* convert tm to seconds. */ | |
144 | ret = rtc_valid_tm(tm); | |
145 | if (ret) | |
146 | return ret; | |
147 | ||
148 | rtc_tm_to_time(tm, &sec); | |
149 | ||
150 | dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n", | |
151 | sec, | |
152 | tm->tm_mon+1, | |
153 | tm->tm_mday, | |
154 | tm->tm_year+1900, | |
155 | tm->tm_hour, | |
156 | tm->tm_min, | |
157 | tm->tm_sec | |
158 | ); | |
159 | ||
160 | /* seconds only written if wait succeeded. */ | |
161 | ret = tegra_rtc_wait_while_busy(dev); | |
162 | if (!ret) | |
163 | writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS); | |
164 | ||
165 | dev_vdbg(dev, "time read back as %d\n", | |
166 | readl(info->rtc_base + TEGRA_RTC_REG_SECONDS)); | |
167 | ||
168 | return ret; | |
169 | } | |
170 | ||
171 | static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
172 | { | |
173 | struct tegra_rtc_info *info = dev_get_drvdata(dev); | |
174 | unsigned long sec; | |
175 | unsigned tmp; | |
176 | ||
177 | sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); | |
178 | ||
179 | if (sec == 0) { | |
180 | /* alarm is disabled. */ | |
181 | alarm->enabled = 0; | |
ff859ba6 AC |
182 | } else { |
183 | /* alarm is enabled. */ | |
184 | alarm->enabled = 1; | |
185 | rtc_time_to_tm(sec, &alarm->time); | |
186 | } | |
187 | ||
188 | tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); | |
189 | alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0; | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
195 | { | |
196 | struct tegra_rtc_info *info = dev_get_drvdata(dev); | |
197 | unsigned status; | |
198 | unsigned long sl_irq_flags; | |
199 | ||
200 | tegra_rtc_wait_while_busy(dev); | |
201 | spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); | |
202 | ||
203 | /* read the original value, and OR in the flag. */ | |
204 | status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK); | |
205 | if (enabled) | |
206 | status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */ | |
207 | else | |
208 | status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */ | |
209 | ||
210 | writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); | |
211 | ||
212 | spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
218 | { | |
219 | struct tegra_rtc_info *info = dev_get_drvdata(dev); | |
220 | unsigned long sec; | |
221 | ||
222 | if (alarm->enabled) | |
223 | rtc_tm_to_time(&alarm->time, &sec); | |
224 | else | |
225 | sec = 0; | |
226 | ||
227 | tegra_rtc_wait_while_busy(dev); | |
228 | writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); | |
229 | dev_vdbg(dev, "alarm read back as %d\n", | |
230 | readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); | |
231 | ||
232 | /* if successfully written and alarm is enabled ... */ | |
233 | if (sec) { | |
234 | tegra_rtc_alarm_irq_enable(dev, 1); | |
235 | ||
236 | dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n", | |
237 | sec, | |
238 | alarm->time.tm_mon+1, | |
239 | alarm->time.tm_mday, | |
240 | alarm->time.tm_year+1900, | |
241 | alarm->time.tm_hour, | |
242 | alarm->time.tm_min, | |
243 | alarm->time.tm_sec); | |
244 | } else { | |
245 | /* disable alarm if 0 or write error. */ | |
246 | dev_vdbg(dev, "alarm disabled\n"); | |
247 | tegra_rtc_alarm_irq_enable(dev, 0); | |
248 | } | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
253 | static int tegra_rtc_proc(struct device *dev, struct seq_file *seq) | |
254 | { | |
255 | if (!dev || !dev->driver) | |
256 | return 0; | |
257 | ||
4395eb1f JP |
258 | seq_printf(seq, "name\t\t: %s\n", dev_name(dev)); |
259 | ||
260 | return 0; | |
ff859ba6 AC |
261 | } |
262 | ||
263 | static irqreturn_t tegra_rtc_irq_handler(int irq, void *data) | |
264 | { | |
265 | struct device *dev = data; | |
266 | struct tegra_rtc_info *info = dev_get_drvdata(dev); | |
267 | unsigned long events = 0; | |
268 | unsigned status; | |
269 | unsigned long sl_irq_flags; | |
270 | ||
271 | status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); | |
272 | if (status) { | |
273 | /* clear the interrupt masks and status on any irq. */ | |
274 | tegra_rtc_wait_while_busy(dev); | |
275 | spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); | |
276 | writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); | |
277 | writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); | |
278 | spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); | |
279 | } | |
280 | ||
281 | /* check if Alarm */ | |
282 | if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)) | |
283 | events |= RTC_IRQF | RTC_AF; | |
284 | ||
285 | /* check if Periodic */ | |
286 | if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)) | |
287 | events |= RTC_IRQF | RTC_PF; | |
288 | ||
289 | rtc_update_irq(info->rtc_dev, 1, events); | |
290 | ||
291 | return IRQ_HANDLED; | |
292 | } | |
293 | ||
34c7b3ac | 294 | static const struct rtc_class_ops tegra_rtc_ops = { |
ff859ba6 AC |
295 | .read_time = tegra_rtc_read_time, |
296 | .set_time = tegra_rtc_set_time, | |
297 | .read_alarm = tegra_rtc_read_alarm, | |
298 | .set_alarm = tegra_rtc_set_alarm, | |
299 | .proc = tegra_rtc_proc, | |
300 | .alarm_irq_enable = tegra_rtc_alarm_irq_enable, | |
301 | }; | |
302 | ||
2d79cf8a JL |
303 | static const struct of_device_id tegra_rtc_dt_match[] = { |
304 | { .compatible = "nvidia,tegra20-rtc", }, | |
305 | {} | |
306 | }; | |
307 | MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match); | |
308 | ||
51b38c62 | 309 | static int __init tegra_rtc_probe(struct platform_device *pdev) |
ff859ba6 AC |
310 | { |
311 | struct tegra_rtc_info *info; | |
312 | struct resource *res; | |
313 | int ret; | |
314 | ||
621bae79 HH |
315 | info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info), |
316 | GFP_KERNEL); | |
ff859ba6 AC |
317 | if (!info) |
318 | return -ENOMEM; | |
319 | ||
320 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8cbce1e5 TR |
321 | info->rtc_base = devm_ioremap_resource(&pdev->dev, res); |
322 | if (IS_ERR(info->rtc_base)) | |
323 | return PTR_ERR(info->rtc_base); | |
ff859ba6 AC |
324 | |
325 | info->tegra_rtc_irq = platform_get_irq(pdev, 0); | |
621bae79 HH |
326 | if (info->tegra_rtc_irq <= 0) |
327 | return -EBUSY; | |
ff859ba6 AC |
328 | |
329 | /* set context info. */ | |
330 | info->pdev = pdev; | |
e57ee017 | 331 | spin_lock_init(&info->tegra_rtc_lock); |
ff859ba6 AC |
332 | |
333 | platform_set_drvdata(pdev, info); | |
334 | ||
335 | /* clear out the hardware. */ | |
336 | writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); | |
337 | writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); | |
338 | writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); | |
339 | ||
340 | device_init_wakeup(&pdev->dev, 1); | |
341 | ||
68567112 LD |
342 | info->rtc_dev = devm_rtc_device_register(&pdev->dev, |
343 | dev_name(&pdev->dev), &tegra_rtc_ops, | |
344 | THIS_MODULE); | |
ff859ba6 AC |
345 | if (IS_ERR(info->rtc_dev)) { |
346 | ret = PTR_ERR(info->rtc_dev); | |
68567112 | 347 | dev_err(&pdev->dev, "Unable to register device (err=%d).\n", |
ff859ba6 | 348 | ret); |
621bae79 | 349 | return ret; |
ff859ba6 AC |
350 | } |
351 | ||
621bae79 HH |
352 | ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq, |
353 | tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH, | |
57bff981 | 354 | dev_name(&pdev->dev), &pdev->dev); |
ff859ba6 AC |
355 | if (ret) { |
356 | dev_err(&pdev->dev, | |
357 | "Unable to request interrupt for device (err=%d).\n", | |
358 | ret); | |
68567112 | 359 | return ret; |
ff859ba6 AC |
360 | } |
361 | ||
362 | dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n"); | |
363 | ||
ff859ba6 AC |
364 | return 0; |
365 | } | |
366 | ||
38a6276e | 367 | #ifdef CONFIG_PM_SLEEP |
3443ad09 | 368 | static int tegra_rtc_suspend(struct device *dev) |
ff859ba6 | 369 | { |
3443ad09 | 370 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
ff859ba6 AC |
371 | |
372 | tegra_rtc_wait_while_busy(dev); | |
373 | ||
374 | /* only use ALARM0 as a wake source. */ | |
375 | writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); | |
376 | writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0, | |
377 | info->rtc_base + TEGRA_RTC_REG_INTR_MASK); | |
378 | ||
379 | dev_vdbg(dev, "alarm sec = %d\n", | |
380 | readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); | |
381 | ||
382 | dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n", | |
383 | device_may_wakeup(dev), info->tegra_rtc_irq); | |
384 | ||
385 | /* leave the alarms on as a wake source. */ | |
386 | if (device_may_wakeup(dev)) | |
387 | enable_irq_wake(info->tegra_rtc_irq); | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
3443ad09 | 392 | static int tegra_rtc_resume(struct device *dev) |
ff859ba6 | 393 | { |
3443ad09 | 394 | struct tegra_rtc_info *info = dev_get_drvdata(dev); |
ff859ba6 AC |
395 | |
396 | dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n", | |
397 | device_may_wakeup(dev)); | |
398 | /* alarms were left on as a wake source, turn them off. */ | |
399 | if (device_may_wakeup(dev)) | |
400 | disable_irq_wake(info->tegra_rtc_irq); | |
401 | ||
402 | return 0; | |
403 | } | |
404 | #endif | |
405 | ||
3443ad09 LD |
406 | static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume); |
407 | ||
ff859ba6 AC |
408 | static void tegra_rtc_shutdown(struct platform_device *pdev) |
409 | { | |
410 | dev_vdbg(&pdev->dev, "disabling interrupts.\n"); | |
411 | tegra_rtc_alarm_irq_enable(&pdev->dev, 0); | |
412 | } | |
413 | ||
414 | MODULE_ALIAS("platform:tegra_rtc"); | |
415 | static struct platform_driver tegra_rtc_driver = { | |
ff859ba6 AC |
416 | .shutdown = tegra_rtc_shutdown, |
417 | .driver = { | |
418 | .name = "tegra_rtc", | |
2d79cf8a | 419 | .of_match_table = tegra_rtc_dt_match, |
3443ad09 | 420 | .pm = &tegra_rtc_pm_ops, |
ff859ba6 | 421 | }, |
ff859ba6 AC |
422 | }; |
423 | ||
0e2c481d | 424 | module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe); |
ff859ba6 AC |
425 | |
426 | MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>"); | |
427 | MODULE_DESCRIPTION("driver for Tegra internal RTC"); | |
428 | MODULE_LICENSE("GPL"); |