[linux-2.6-block.git] / drivers / rtc / rtc-tegra.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
 *
 * Copyright (c) 2010, NVIDIA Corporation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/rtc.h>
#include <linux/slab.h>

/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
#define TEGRA_RTC_REG_BUSY			0x004
#define TEGRA_RTC_REG_SECONDS			0x008
/* when msec is read, the seconds are buffered into shadow seconds. */
#define TEGRA_RTC_REG_SHADOW_SECONDS		0x00c
#define TEGRA_RTC_REG_MILLI_SECONDS		0x010
#define TEGRA_RTC_REG_SECONDS_ALARM0		0x014
#define TEGRA_RTC_REG_SECONDS_ALARM1		0x018
#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0	0x01c
#define TEGRA_RTC_REG_INTR_MASK			0x028
/* write 1 bits to clear status bits */
#define TEGRA_RTC_REG_INTR_STATUS		0x02c

/* bits in INTR_MASK */
#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM	(1<<4)
#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM	(1<<3)
#define TEGRA_RTC_INTR_MASK_MSEC_ALARM		(1<<2)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM1		(1<<1)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM0		(1<<0)

/* bits in INTR_STATUS */
#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM	(1<<4)
#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM	(1<<3)
#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM	(1<<2)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1	(1<<1)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0	(1<<0)

struct tegra_rtc_info {
	struct platform_device	*pdev;
	struct rtc_device	*rtc_dev;
	void __iomem		*rtc_base; /* NULL if not initialized. */
	struct clk		*clk;
	int			tegra_rtc_irq; /* alarm and periodic irq */
	spinlock_t		tegra_rtc_lock;
};

/* RTC hardware is busy when it is updating its values over AHB once
 * every eight 32kHz clocks (~250uS).
 * outside of these updates the CPU is free to write.
 * CPU is always free to read.
 */
static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
{
	return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
}

/* Wait for hardware to be ready for writing.
 * This function tries to maximize the amount of time before the next update.
 * It does this by waiting for the RTC to become busy with its periodic update,
 * then returning once the RTC first becomes not busy.
 * This periodic update (where the seconds and milliseconds are copied to the
 * AHB side) occurs every eight 32kHz clocks (~250uS).
 * The behavior of this function allows us to make some assumptions without
 * introducing a race, because 250uS is plenty of time to read/write a value.
 */
static int tegra_rtc_wait_while_busy(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	int retries = 500; /* ~490 us is the worst case, ~250 us is best. */

	/* first wait for the RTC to become busy. this is when it
	 * posts its updated seconds+msec registers to AHB side. */
	while (tegra_rtc_check_busy(info)) {
		if (!retries--)
			goto retry_failed;
		udelay(1);
	}

	/* now we have about 250 us to manipulate registers */
	return 0;

retry_failed:
	dev_err(dev, "write failed:retry count exceeded.\n");
	return -ETIMEDOUT;
}

static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec, msec;
	unsigned long sl_irq_flags;

	/* RTC hardware copies seconds to shadow seconds when a read
	 * of milliseconds occurs. use a lock to keep other threads out. */
	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);

	msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
	sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);

	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);

	rtc_time64_to_tm(sec, tm);

	dev_vdbg(dev, "time read as %lu. %ptR\n", sec, tm);

	return 0;
}

static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec;
	int ret;

	/* convert tm to seconds. */
	sec = rtc_tm_to_time64(tm);

	dev_vdbg(dev, "time set to %lu. %ptR\n", sec, tm);

	/* seconds only written if wait succeeded. */
	ret = tegra_rtc_wait_while_busy(dev);
	if (!ret)
		writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);

	dev_vdbg(dev, "time read back as %d\n",
		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));

	return ret;
}

static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec;
	unsigned tmp;

	sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);

	if (sec == 0) {
		/* alarm is disabled. */
		alarm->enabled = 0;
	} else {
		/* alarm is enabled. */
		alarm->enabled = 1;
		rtc_time64_to_tm(sec, &alarm->time);
	}

	tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;

	return 0;
}

static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned status;
	unsigned long sl_irq_flags;

	tegra_rtc_wait_while_busy(dev);
	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);

	/* read the original value, and OR in the flag. */
	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	if (enabled)
		status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
	else
		status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */

	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);

	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);

	return 0;
}

static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long sec;

	if (alarm->enabled)
		sec = rtc_tm_to_time64(&alarm->time);
	else
		sec = 0;

	tegra_rtc_wait_while_busy(dev);
	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	dev_vdbg(dev, "alarm read back as %d\n",
		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));

	/* if successfully written and alarm is enabled ... */
	if (sec) {
		tegra_rtc_alarm_irq_enable(dev, 1);
		dev_vdbg(dev, "alarm set as %lu. %ptR\n", sec, &alarm->time);
	} else {
		/* disable alarm if 0 or write error. */
		dev_vdbg(dev, "alarm disabled\n");
		tegra_rtc_alarm_irq_enable(dev, 0);
	}

	return 0;
}

static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
{
	if (!dev || !dev->driver)
		return 0;

	seq_printf(seq, "name\t\t: %s\n", dev_name(dev));

	return 0;
}

static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
{
	struct device *dev = data;
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long events = 0;
	unsigned status;
	unsigned long sl_irq_flags;

	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	if (status) {
		/* clear the interrupt masks and status on any irq. */
		tegra_rtc_wait_while_busy(dev);
		spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
		writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
		writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
		spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	}

	/* check if Alarm */
	if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
		events |= RTC_IRQF | RTC_AF;

	/* check if Periodic */
	if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
		events |= RTC_IRQF | RTC_PF;

	rtc_update_irq(info->rtc_dev, 1, events);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops tegra_rtc_ops = {
	.read_time	= tegra_rtc_read_time,
	.set_time	= tegra_rtc_set_time,
	.read_alarm	= tegra_rtc_read_alarm,
	.set_alarm	= tegra_rtc_set_alarm,
	.proc		= tegra_rtc_proc,
	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
};

static const struct of_device_id tegra_rtc_dt_match[] = {
	{ .compatible = "nvidia,tegra20-rtc", },
	{}
};
MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);

static int __init tegra_rtc_probe(struct platform_device *pdev)
{
	struct tegra_rtc_info *info;
	struct resource *res;
	int ret;

	info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
		GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(info->rtc_base))
		return PTR_ERR(info->rtc_base);

	ret = platform_get_irq(pdev, 0);
	if (ret <= 0) {
		dev_err(&pdev->dev, "failed to get platform IRQ: %d\n", ret);
		return ret;
	}

	info->tegra_rtc_irq = ret;

	info->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(info->rtc_dev))
		return PTR_ERR(info->rtc_dev);

	info->rtc_dev->ops = &tegra_rtc_ops;
	info->rtc_dev->range_max = U32_MAX;

	info->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(info->clk))
		return PTR_ERR(info->clk);

	ret = clk_prepare_enable(info->clk);
	if (ret < 0)
		return ret;

	/* set context info. */
	info->pdev = pdev;
	spin_lock_init(&info->tegra_rtc_lock);

	platform_set_drvdata(pdev, info);

	/* clear out the hardware. */
	writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);

	device_init_wakeup(&pdev->dev, 1);

	ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
			tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
			dev_name(&pdev->dev), &pdev->dev);
	if (ret) {
		dev_err(&pdev->dev,
			"Unable to request interrupt for device (err=%d).\n",
			ret);
		goto disable_clk;
	}

	ret = rtc_register_device(info->rtc_dev);
	if (ret) {
		dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
			ret);
		goto disable_clk;
	}

	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");

	return 0;

disable_clk:
	clk_disable_unprepare(info->clk);
	return ret;
}

static int tegra_rtc_remove(struct platform_device *pdev)
{
	struct tegra_rtc_info *info = platform_get_drvdata(pdev);

	clk_disable_unprepare(info->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int tegra_rtc_suspend(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	tegra_rtc_wait_while_busy(dev);

	/* only use ALARM0 as a wake source. */
	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
		info->rtc_base + TEGRA_RTC_REG_INTR_MASK);

	dev_vdbg(dev, "alarm sec = %d\n",
		readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));

	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
		device_may_wakeup(dev), info->tegra_rtc_irq);

	/* leave the alarms on as a wake source. */
	if (device_may_wakeup(dev))
		enable_irq_wake(info->tegra_rtc_irq);

	return 0;
}

static int tegra_rtc_resume(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
		device_may_wakeup(dev));
	/* alarms were left on as a wake source, turn them off. */
	if (device_may_wakeup(dev))
		disable_irq_wake(info->tegra_rtc_irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);

static void tegra_rtc_shutdown(struct platform_device *pdev)
{
	dev_vdbg(&pdev->dev, "disabling interrupts.\n");
	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
}

MODULE_ALIAS("platform:tegra_rtc");
static struct platform_driver tegra_rtc_driver = {
	.remove		= tegra_rtc_remove,
	.shutdown	= tegra_rtc_shutdown,
	.driver		= {
		.name	= "tegra_rtc",
		.of_match_table = tegra_rtc_dt_match,
		.pm	= &tegra_rtc_pm_ops,
	},
};

module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);

MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
MODULE_DESCRIPTION("driver for Tegra internal RTC");
MODULE_LICENSE("GPL");
Commit	Line	Data
b6838275	1	// SPDX-License-Identifier: GPL-2.0+
ff859ba6 AC	2	/*
	3	* An RTC driver for the NVIDIA Tegra 200 series internal RTC.
	4	*
	5	* Copyright (c) 2010, NVIDIA Corporation.
ff859ba6	6	*/
0ae20595	7
5fa40869	8	#include <linux/clk.h>
0ae20595	9	#include <linux/delay.h>
ff859ba6	10	#include <linux/init.h>
ff859ba6	11	#include <linux/io.h>
0ae20595 TR	12	#include <linux/irq.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
ac316725	15	#include <linux/mod_devicetable.h>
ff859ba6	16	#include <linux/platform_device.h>
3443ad09	17	#include <linux/pm.h>
0ae20595 TR	18	#include <linux/rtc.h>
0ae20595 TR	19	#include <linux/slab.h>
ff859ba6 AC	20
	21	/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
	22	#define TEGRA_RTC_REG_BUSY 0x004
	23	#define TEGRA_RTC_REG_SECONDS 0x008
	24	/* when msec is read, the seconds are buffered into shadow seconds. */
	25	#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
	26	#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
	27	#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
	28	#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
	29	#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
	30	#define TEGRA_RTC_REG_INTR_MASK 0x028
	31	/* write 1 bits to clear status bits */
	32	#define TEGRA_RTC_REG_INTR_STATUS 0x02c
	33
	34	/* bits in INTR_MASK */
	35	#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
	36	#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
	37	#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
	38	#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
	39	#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
	40
	41	/* bits in INTR_STATUS */
	42	#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
	43	#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
	44	#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
	45	#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
	46	#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
	47
	48	struct tegra_rtc_info {
	49	struct platform_device *pdev;
	50	struct rtc_device *rtc_dev;
	51	void __iomem rtc_base; / NULL if not initialized. */
5fa40869	52	struct clk *clk;
ff859ba6 AC	53	int tegra_rtc_irq; /* alarm and periodic irq */
	54	spinlock_t tegra_rtc_lock;
	55	};
	56
	57	/* RTC hardware is busy when it is updating its values over AHB once
	58	* every eight 32kHz clocks (~250uS).
	59	* outside of these updates the CPU is free to write.
	60	* CPU is always free to read.
	61	*/
	62	static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
	63	{
	64	return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
	65	}
	66
	67	/* Wait for hardware to be ready for writing.
	68	* This function tries to maximize the amount of time before the next update.
	69	* It does this by waiting for the RTC to become busy with its periodic update,
	70	* then returning once the RTC first becomes not busy.
	71	* This periodic update (where the seconds and milliseconds are copied to the
	72	* AHB side) occurs every eight 32kHz clocks (~250uS).
	73	* The behavior of this function allows us to make some assumptions without
	74	* introducing a race, because 250uS is plenty of time to read/write a value.
	75	*/
	76	static int tegra_rtc_wait_while_busy(struct device *dev)
	77	{
	78	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	79
	80	int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
	81
	82	/* first wait for the RTC to become busy. this is when it
	83	* posts its updated seconds+msec registers to AHB side. */
	84	while (tegra_rtc_check_busy(info)) {
	85	if (!retries--)
	86	goto retry_failed;
	87	udelay(1);
	88	}
	89
	90	/* now we have about 250 us to manipulate registers */
	91	return 0;
	92
	93	retry_failed:
	94	dev_err(dev, "write failed:retry count exceeded.\n");
	95	return -ETIMEDOUT;
	96	}
	97
	98	static int tegra_rtc_read_time(struct device dev, struct rtc_time tm)
	99	{
	100	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	101	unsigned long sec, msec;
	102	unsigned long sl_irq_flags;
	103
	104	/* RTC hardware copies seconds to shadow seconds when a read
	105	* of milliseconds occurs. use a lock to keep other threads out. */
	106	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
	107
	108	msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
	109	sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
	110
	111	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	112
34ea0ac3	113	rtc_time64_to_tm(sec, tm);
ff859ba6	114
d54fb486	115	dev_vdbg(dev, "time read as %lu. %ptR\n", sec, tm);
ff859ba6 AC	116
	117	return 0;
	118	}
	119
	120	static int tegra_rtc_set_time(struct device dev, struct rtc_time tm)
	121	{
	122	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	123	unsigned long sec;
	124	int ret;
	125
	126	/* convert tm to seconds. */
34ea0ac3	127	sec = rtc_tm_to_time64(tm);
ff859ba6	128
d54fb486	129	dev_vdbg(dev, "time set to %lu. %ptR\n", sec, tm);
ff859ba6 AC	130
	131	/* seconds only written if wait succeeded. */
	132	ret = tegra_rtc_wait_while_busy(dev);
	133	if (!ret)
	134	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
	135
	136	dev_vdbg(dev, "time read back as %d\n",
	137	readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
	138
	139	return ret;
	140	}
	141
	142	static int tegra_rtc_read_alarm(struct device dev, struct rtc_wkalrm alarm)
	143	{
	144	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	145	unsigned long sec;
	146	unsigned tmp;
	147
	148	sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	149
	150	if (sec == 0) {
	151	/* alarm is disabled. */
	152	alarm->enabled = 0;
ff859ba6 AC	153	} else {
	154	/* alarm is enabled. */
	155	alarm->enabled = 1;
34ea0ac3	156	rtc_time64_to_tm(sec, &alarm->time);
ff859ba6 AC	157	}
	158
	159	tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	160	alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
	161
	162	return 0;
	163	}
	164
	165	static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	166	{
	167	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	168	unsigned status;
	169	unsigned long sl_irq_flags;
	170
	171	tegra_rtc_wait_while_busy(dev);
	172	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
	173
	174	/* read the original value, and OR in the flag. */
	175	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	176	if (enabled)
	177	status \|= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
	178	else
	179	status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
	180
	181	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	182
	183	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	184
	185	return 0;
	186	}
	187
	188	static int tegra_rtc_set_alarm(struct device dev, struct rtc_wkalrm alarm)
	189	{
	190	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	191	unsigned long sec;
	192
	193	if (alarm->enabled)
34ea0ac3	194	sec = rtc_tm_to_time64(&alarm->time);
ff859ba6 AC	195	else
	196	sec = 0;
	197
	198	tegra_rtc_wait_while_busy(dev);
	199	writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	200	dev_vdbg(dev, "alarm read back as %d\n",
	201	readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
	202
	203	/* if successfully written and alarm is enabled ... */
	204	if (sec) {
	205	tegra_rtc_alarm_irq_enable(dev, 1);
d54fb486	206	dev_vdbg(dev, "alarm set as %lu. %ptR\n", sec, &alarm->time);
ff859ba6 AC	207	} else {
	208	/* disable alarm if 0 or write error. */
	209	dev_vdbg(dev, "alarm disabled\n");
	210	tegra_rtc_alarm_irq_enable(dev, 0);
	211	}
	212
	213	return 0;
	214	}
	215
	216	static int tegra_rtc_proc(struct device dev, struct seq_file seq)
	217	{
	218	if (!dev \|\| !dev->driver)
	219	return 0;
	220
4395eb1f JP	221	seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
	222
	223	return 0;
ff859ba6 AC	224	}
	225
	226	static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
	227	{
	228	struct device *dev = data;
	229	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	230	unsigned long events = 0;
	231	unsigned status;
	232	unsigned long sl_irq_flags;
	233
	234	status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	235	if (status) {
	236	/* clear the interrupt masks and status on any irq. */
	237	tegra_rtc_wait_while_busy(dev);
	238	spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
	239	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	240	writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	241	spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
	242	}
	243
	244	/* check if Alarm */
	245	if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
	246	events \|= RTC_IRQF \| RTC_AF;
	247
	248	/* check if Periodic */
	249	if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
	250	events \|= RTC_IRQF \| RTC_PF;
	251
	252	rtc_update_irq(info->rtc_dev, 1, events);
	253
	254	return IRQ_HANDLED;
	255	}
	256
34c7b3ac	257	static const struct rtc_class_ops tegra_rtc_ops = {
ff859ba6 AC	258	.read_time = tegra_rtc_read_time,
	259	.set_time = tegra_rtc_set_time,
	260	.read_alarm = tegra_rtc_read_alarm,
	261	.set_alarm = tegra_rtc_set_alarm,
	262	.proc = tegra_rtc_proc,
	263	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
	264	};
	265
2d79cf8a JL	266	static const struct of_device_id tegra_rtc_dt_match[] = {
	267	{ .compatible = "nvidia,tegra20-rtc", },
	268	{}
	269	};
	270	MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
	271
51b38c62	272	static int __init tegra_rtc_probe(struct platform_device *pdev)
ff859ba6 AC	273	{
	274	struct tegra_rtc_info *info;
	275	struct resource *res;
	276	int ret;
	277
621bae79 HH	278	info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
621bae79 HH	279	GFP_KERNEL);
ff859ba6 AC	280	if (!info)
	281	return -ENOMEM;
	282
	283	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cbce1e5 TR	284	info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
	285	if (IS_ERR(info->rtc_base))
	286	return PTR_ERR(info->rtc_base);
ff859ba6	287
fe0b5ced TR	288	ret = platform_get_irq(pdev, 0);
	289	if (ret <= 0) {
	290	dev_err(&pdev->dev, "failed to get platform IRQ: %d\n", ret);
	291	return ret;
	292	}
	293
	294	info->tegra_rtc_irq = ret;
ff859ba6	295
e1089802 AB	296	info->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
	297	if (IS_ERR(info->rtc_dev))
	298	return PTR_ERR(info->rtc_dev);
	299
	300	info->rtc_dev->ops = &tegra_rtc_ops;
	301	info->rtc_dev->range_max = U32_MAX;
	302
5fa40869 TR	303	info->clk = devm_clk_get(&pdev->dev, NULL);
	304	if (IS_ERR(info->clk))
	305	return PTR_ERR(info->clk);
	306
	307	ret = clk_prepare_enable(info->clk);
	308	if (ret < 0)
	309	return ret;
	310
ff859ba6 AC	311	/* set context info. */
ff859ba6 AC	312	info->pdev = pdev;
e57ee017	313	spin_lock_init(&info->tegra_rtc_lock);
ff859ba6 AC	314
	315	platform_set_drvdata(pdev, info);
	316
	317	/* clear out the hardware. */
	318	writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
	319	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	320	writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	321
	322	device_init_wakeup(&pdev->dev, 1);
	323
621bae79 HH	324	ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
621bae79 HH	325	tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
57bff981	326	dev_name(&pdev->dev), &pdev->dev);
ff859ba6 AC	327	if (ret) {
	328	dev_err(&pdev->dev,
	329	"Unable to request interrupt for device (err=%d).\n",
	330	ret);
e1089802 AB	331	goto disable_clk;
	332	}
	333
	334	ret = rtc_register_device(info->rtc_dev);
	335	if (ret) {
	336	dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
	337	ret);
5fa40869	338	goto disable_clk;
ff859ba6 AC	339	}
	340
	341	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
	342
5fa40869 TR	343	return 0;
	344
	345	disable_clk:
	346	clk_disable_unprepare(info->clk);
	347	return ret;
	348	}
	349
	350	static int tegra_rtc_remove(struct platform_device *pdev)
	351	{
	352	struct tegra_rtc_info *info = platform_get_drvdata(pdev);
	353
	354	clk_disable_unprepare(info->clk);
	355
ff859ba6 AC	356	return 0;
	357	}
	358
38a6276e	359	#ifdef CONFIG_PM_SLEEP
3443ad09	360	static int tegra_rtc_suspend(struct device *dev)
ff859ba6	361	{
3443ad09	362	struct tegra_rtc_info *info = dev_get_drvdata(dev);
ff859ba6 AC	363
	364	tegra_rtc_wait_while_busy(dev);
	365
	366	/* only use ALARM0 as a wake source. */
	367	writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
	368	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
	369	info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
	370
	371	dev_vdbg(dev, "alarm sec = %d\n",
	372	readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
	373
	374	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
	375	device_may_wakeup(dev), info->tegra_rtc_irq);
	376
	377	/* leave the alarms on as a wake source. */
	378	if (device_may_wakeup(dev))
	379	enable_irq_wake(info->tegra_rtc_irq);
	380
	381	return 0;
	382	}
	383
3443ad09	384	static int tegra_rtc_resume(struct device *dev)
ff859ba6	385	{
3443ad09	386	struct tegra_rtc_info *info = dev_get_drvdata(dev);
ff859ba6 AC	387
	388	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
	389	device_may_wakeup(dev));
	390	/* alarms were left on as a wake source, turn them off. */
	391	if (device_may_wakeup(dev))
	392	disable_irq_wake(info->tegra_rtc_irq);
	393
	394	return 0;
	395	}
	396	#endif
	397
3443ad09 LD	398	static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
3443ad09 LD	399
ff859ba6 AC	400	static void tegra_rtc_shutdown(struct platform_device *pdev)
	401	{
	402	dev_vdbg(&pdev->dev, "disabling interrupts.\n");
	403	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
	404	}
	405
	406	MODULE_ALIAS("platform:tegra_rtc");
	407	static struct platform_driver tegra_rtc_driver = {
5fa40869	408	.remove = tegra_rtc_remove,
ff859ba6 AC	409	.shutdown = tegra_rtc_shutdown,
	410	.driver = {
	411	.name = "tegra_rtc",
2d79cf8a	412	.of_match_table = tegra_rtc_dt_match,
3443ad09	413	.pm = &tegra_rtc_pm_ops,
ff859ba6	414	},
ff859ba6 AC	415	};
ff859ba6 AC	416
0e2c481d	417	module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
ff859ba6 AC	418
	419	MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
	420	MODULE_DESCRIPTION("driver for Tegra internal RTC");
	421	MODULE_LICENSE("GPL");