[linux-2.6-block.git] / drivers / rtc / rtc-tegra.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
 *
 * Copyright (c) 2010-2019, NVIDIA Corporation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/rtc.h>
#include <linux/slab.h>

/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
#define TEGRA_RTC_REG_BUSY			0x004
#define TEGRA_RTC_REG_SECONDS			0x008
/* When msec is read, the seconds are buffered into shadow seconds. */
#define TEGRA_RTC_REG_SHADOW_SECONDS		0x00c
#define TEGRA_RTC_REG_MILLI_SECONDS		0x010
#define TEGRA_RTC_REG_SECONDS_ALARM0		0x014
#define TEGRA_RTC_REG_SECONDS_ALARM1		0x018
#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0	0x01c
#define TEGRA_RTC_REG_INTR_MASK			0x028
/* write 1 bits to clear status bits */
#define TEGRA_RTC_REG_INTR_STATUS		0x02c

/* bits in INTR_MASK */
#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM	(1<<4)
#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM	(1<<3)
#define TEGRA_RTC_INTR_MASK_MSEC_ALARM		(1<<2)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM1		(1<<1)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM0		(1<<0)

/* bits in INTR_STATUS */
#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM	(1<<4)
#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM	(1<<3)
#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM	(1<<2)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1	(1<<1)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0	(1<<0)

struct tegra_rtc_info {
	struct platform_device *pdev;
	struct rtc_device *rtc;
	void __iomem *base; /* NULL if not initialized */
	struct clk *clk;
	int irq; /* alarm and periodic IRQ */
	spinlock_t lock;
};

/*
 * RTC hardware is busy when it is updating its values over AHB once every
 * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
 * write. CPU is always free to read.
 */
static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
{
	return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
}

/*
 * Wait for hardware to be ready for writing. This function tries to maximize
 * the amount of time before the next update. It does this by waiting for the
 * RTC to become busy with its periodic update, then returning once the RTC
 * first becomes not busy.
 *
 * This periodic update (where the seconds and milliseconds are copied to the
 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
 * function allows us to make some assumptions without introducing a race,
 * because 250 us is plenty of time to read/write a value.
 */
static int tegra_rtc_wait_while_busy(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	int retries = 500; /* ~490 us is the worst case, ~250 us is best */

	/*
	 * First wait for the RTC to become busy. This is when it posts its
	 * updated seconds+msec registers to AHB side.
	 */
	while (tegra_rtc_check_busy(info)) {
		if (!retries--)
			goto retry_failed;

		udelay(1);
	}

	/* now we have about 250 us to manipulate registers */
	return 0;

retry_failed:
	dev_err(dev, "write failed: retry count exceeded\n");
	return -ETIMEDOUT;
}

static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long flags;
	u32 sec;

	/*
	 * RTC hardware copies seconds to shadow seconds when a read of
	 * milliseconds occurs. use a lock to keep other threads out.
	 */
	spin_lock_irqsave(&info->lock, flags);

	readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
	sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);

	spin_unlock_irqrestore(&info->lock, flags);

	rtc_time64_to_tm(sec, tm);

	dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);

	return 0;
}

static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	u32 sec;
	int ret;

	/* convert tm to seconds */
	sec = rtc_tm_to_time64(tm);

	dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);

	/* seconds only written if wait succeeded */
	ret = tegra_rtc_wait_while_busy(dev);
	if (!ret)
		writel(sec, info->base + TEGRA_RTC_REG_SECONDS);

	dev_vdbg(dev, "time read back as %d\n",
		 readl(info->base + TEGRA_RTC_REG_SECONDS));

	return ret;
}

static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	u32 sec, value;

	sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);

	if (sec == 0) {
		/* alarm is disabled */
		alarm->enabled = 0;
	} else {
		/* alarm is enabled */
		alarm->enabled = 1;
		rtc_time64_to_tm(sec, &alarm->time);
	}

	value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
	alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;

	return 0;
}

static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long flags;
	u32 status;

	tegra_rtc_wait_while_busy(dev);
	spin_lock_irqsave(&info->lock, flags);

	/* read the original value, and OR in the flag */
	status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
	if (enabled)
		status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
	else
		status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */

	writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);

	spin_unlock_irqrestore(&info->lock, flags);

	return 0;
}

static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	u32 sec;

	if (alarm->enabled)
		sec = rtc_tm_to_time64(&alarm->time);
	else
		sec = 0;

	tegra_rtc_wait_while_busy(dev);
	writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
	dev_vdbg(dev, "alarm read back as %d\n",
		 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));

	/* if successfully written and alarm is enabled ... */
	if (sec) {
		tegra_rtc_alarm_irq_enable(dev, 1);
		dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
	} else {
		/* disable alarm if 0 or write error */
		dev_vdbg(dev, "alarm disabled\n");
		tegra_rtc_alarm_irq_enable(dev, 0);
	}

	return 0;
}

static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
{
	if (!dev || !dev->driver)
		return 0;

	seq_printf(seq, "name\t\t: %s\n", dev_name(dev));

	return 0;
}

static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
{
	struct device *dev = data;
	struct tegra_rtc_info *info = dev_get_drvdata(dev);
	unsigned long events = 0;
	u32 status;

	status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
	if (status) {
		/* clear the interrupt masks and status on any IRQ */
		tegra_rtc_wait_while_busy(dev);

		spin_lock(&info->lock);
		writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
		writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
		spin_unlock(&info->lock);
	}

	/* check if alarm */
	if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
		events |= RTC_IRQF | RTC_AF;

	/* check if periodic */
	if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
		events |= RTC_IRQF | RTC_PF;

	rtc_update_irq(info->rtc, 1, events);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops tegra_rtc_ops = {
	.read_time = tegra_rtc_read_time,
	.set_time = tegra_rtc_set_time,
	.read_alarm = tegra_rtc_read_alarm,
	.set_alarm = tegra_rtc_set_alarm,
	.proc = tegra_rtc_proc,
	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
};

static const struct of_device_id tegra_rtc_dt_match[] = {
	{ .compatible = "nvidia,tegra20-rtc", },
	{}
};
MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);

static int tegra_rtc_probe(struct platform_device *pdev)
{
	struct tegra_rtc_info *info;
	int ret;

	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	info->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(info->base))
		return PTR_ERR(info->base);

	ret = platform_get_irq(pdev, 0);
	if (ret <= 0)
		return ret;

	info->irq = ret;

	info->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(info->rtc))
		return PTR_ERR(info->rtc);

	info->rtc->ops = &tegra_rtc_ops;
	info->rtc->range_max = U32_MAX;

	info->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(info->clk))
		return PTR_ERR(info->clk);

	ret = clk_prepare_enable(info->clk);
	if (ret < 0)
		return ret;

	/* set context info */
	info->pdev = pdev;
	spin_lock_init(&info->lock);

	platform_set_drvdata(pdev, info);

	/* clear out the hardware */
	writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
	writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
	writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);

	device_init_wakeup(&pdev->dev, 1);

	ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
			       IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
			       &pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
		goto disable_clk;
	}

	ret = devm_rtc_register_device(info->rtc);
	if (ret)
		goto disable_clk;

	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");

	return 0;

disable_clk:
	clk_disable_unprepare(info->clk);
	return ret;
}

static int tegra_rtc_remove(struct platform_device *pdev)
{
	struct tegra_rtc_info *info = platform_get_drvdata(pdev);

	clk_disable_unprepare(info->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int tegra_rtc_suspend(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	tegra_rtc_wait_while_busy(dev);

	/* only use ALARM0 as a wake source */
	writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
	       info->base + TEGRA_RTC_REG_INTR_MASK);

	dev_vdbg(dev, "alarm sec = %d\n",
		 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));

	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
		 device_may_wakeup(dev), info->irq);

	/* leave the alarms on as a wake source */
	if (device_may_wakeup(dev))
		enable_irq_wake(info->irq);

	return 0;
}

static int tegra_rtc_resume(struct device *dev)
{
	struct tegra_rtc_info *info = dev_get_drvdata(dev);

	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
		 device_may_wakeup(dev));

	/* alarms were left on as a wake source, turn them off */
	if (device_may_wakeup(dev))
		disable_irq_wake(info->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);

static void tegra_rtc_shutdown(struct platform_device *pdev)
{
	dev_vdbg(&pdev->dev, "disabling interrupts\n");
	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
}

static struct platform_driver tegra_rtc_driver = {
	.probe = tegra_rtc_probe,
	.remove = tegra_rtc_remove,
	.shutdown = tegra_rtc_shutdown,
	.driver = {
		.name = "tegra_rtc",
		.of_match_table = tegra_rtc_dt_match,
		.pm = &tegra_rtc_pm_ops,
	},
};
module_platform_driver(tegra_rtc_driver);

MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
MODULE_DESCRIPTION("driver for Tegra internal RTC");
MODULE_LICENSE("GPL");
Commit	Line	Data
b6838275	1	// SPDX-License-Identifier: GPL-2.0+
ff859ba6 AC	2	/*
	3	* An RTC driver for the NVIDIA Tegra 200 series internal RTC.
	4	*
3e483e59	5	* Copyright (c) 2010-2019, NVIDIA Corporation.
ff859ba6	6	*/
0ae20595	7
5fa40869	8	#include <linux/clk.h>
0ae20595	9	#include <linux/delay.h>
ff859ba6	10	#include <linux/init.h>
ff859ba6	11	#include <linux/io.h>
0ae20595 TR	12	#include <linux/irq.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
ac316725	15	#include <linux/mod_devicetable.h>
ff859ba6	16	#include <linux/platform_device.h>
3443ad09	17	#include <linux/pm.h>
0ae20595 TR	18	#include <linux/rtc.h>
0ae20595 TR	19	#include <linux/slab.h>
ff859ba6	20
a2d29238	21	/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
ff859ba6 AC	22	#define TEGRA_RTC_REG_BUSY 0x004
ff859ba6 AC	23	#define TEGRA_RTC_REG_SECONDS 0x008
a2d29238	24	/* When msec is read, the seconds are buffered into shadow seconds. */
ff859ba6 AC	25	#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
	26	#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
	27	#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
	28	#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
	29	#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
	30	#define TEGRA_RTC_REG_INTR_MASK 0x028
	31	/* write 1 bits to clear status bits */
	32	#define TEGRA_RTC_REG_INTR_STATUS 0x02c
	33
	34	/* bits in INTR_MASK */
	35	#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
	36	#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
	37	#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
	38	#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
	39	#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
	40
	41	/* bits in INTR_STATUS */
	42	#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
	43	#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
	44	#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
	45	#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
	46	#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
	47
	48	struct tegra_rtc_info {
a2d29238	49	struct platform_device *pdev;
c6af561a TR	50	struct rtc_device *rtc;
c6af561a TR	51	void __iomem base; / NULL if not initialized */
a2d29238	52	struct clk *clk;
c6af561a TR	53	int irq; /* alarm and periodic IRQ */
c6af561a TR	54	spinlock_t lock;
ff859ba6 AC	55	};
ff859ba6 AC	56
a2d29238 TR	57	/*
	58	* RTC hardware is busy when it is updating its values over AHB once every
	59	* eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
	60	* write. CPU is always free to read.
ff859ba6 AC	61	*/
	62	static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
	63	{
c6af561a	64	return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
ff859ba6 AC	65	}
ff859ba6 AC	66
a2d29238 TR	67	/*
	68	* Wait for hardware to be ready for writing. This function tries to maximize
	69	* the amount of time before the next update. It does this by waiting for the
	70	* RTC to become busy with its periodic update, then returning once the RTC
	71	* first becomes not busy.
	72	*
ff859ba6	73	* This periodic update (where the seconds and milliseconds are copied to the
a2d29238 TR	74	* AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
	75	* function allows us to make some assumptions without introducing a race,
	76	* because 250 us is plenty of time to read/write a value.
ff859ba6 AC	77	*/
	78	static int tegra_rtc_wait_while_busy(struct device *dev)
	79	{
	80	struct tegra_rtc_info *info = dev_get_drvdata(dev);
a2d29238	81	int retries = 500; /* ~490 us is the worst case, ~250 us is best */
ff859ba6	82
a2d29238 TR	83	/*
	84	* First wait for the RTC to become busy. This is when it posts its
	85	* updated seconds+msec registers to AHB side.
	86	*/
ff859ba6 AC	87	while (tegra_rtc_check_busy(info)) {
	88	if (!retries--)
	89	goto retry_failed;
a2d29238	90
ff859ba6 AC	91	udelay(1);
	92	}
	93
	94	/* now we have about 250 us to manipulate registers */
	95	return 0;
	96
	97	retry_failed:
a2d29238	98	dev_err(dev, "write failed: retry count exceeded\n");
ff859ba6 AC	99	return -ETIMEDOUT;
	100	}
	101
	102	static int tegra_rtc_read_time(struct device dev, struct rtc_time tm)
	103	{
	104	struct tegra_rtc_info *info = dev_get_drvdata(dev);
c6af561a	105	unsigned long flags;
8321c2ec	106	u32 sec;
ff859ba6	107
a2d29238 TR	108	/*
	109	* RTC hardware copies seconds to shadow seconds when a read of
	110	* milliseconds occurs. use a lock to keep other threads out.
	111	*/
c6af561a	112	spin_lock_irqsave(&info->lock, flags);
ff859ba6	113
8321c2ec	114	readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
c6af561a	115	sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
ff859ba6	116
c6af561a	117	spin_unlock_irqrestore(&info->lock, flags);
ff859ba6	118
34ea0ac3	119	rtc_time64_to_tm(sec, tm);
ff859ba6	120
a2d29238	121	dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
ff859ba6 AC	122
	123	return 0;
	124	}
	125
	126	static int tegra_rtc_set_time(struct device dev, struct rtc_time tm)
	127	{
	128	struct tegra_rtc_info *info = dev_get_drvdata(dev);
c6af561a	129	u32 sec;
ff859ba6 AC	130	int ret;
ff859ba6 AC	131
a2d29238	132	/* convert tm to seconds */
34ea0ac3	133	sec = rtc_tm_to_time64(tm);
ff859ba6	134
a2d29238	135	dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
ff859ba6	136
a2d29238	137	/* seconds only written if wait succeeded */
ff859ba6 AC	138	ret = tegra_rtc_wait_while_busy(dev);
ff859ba6 AC	139	if (!ret)
c6af561a	140	writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
ff859ba6 AC	141
ff859ba6 AC	142	dev_vdbg(dev, "time read back as %d\n",
c6af561a	143	readl(info->base + TEGRA_RTC_REG_SECONDS));
ff859ba6 AC	144
	145	return ret;
	146	}
	147
	148	static int tegra_rtc_read_alarm(struct device dev, struct rtc_wkalrm alarm)
	149	{
	150	struct tegra_rtc_info *info = dev_get_drvdata(dev);
c6af561a	151	u32 sec, value;
ff859ba6	152
c6af561a	153	sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
ff859ba6 AC	154
ff859ba6 AC	155	if (sec == 0) {
a2d29238	156	/* alarm is disabled */
ff859ba6	157	alarm->enabled = 0;
ff859ba6	158	} else {
a2d29238	159	/* alarm is enabled */
ff859ba6	160	alarm->enabled = 1;
34ea0ac3	161	rtc_time64_to_tm(sec, &alarm->time);
ff859ba6 AC	162	}
ff859ba6 AC	163
c6af561a TR	164	value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
c6af561a TR	165	alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
ff859ba6 AC	166
	167	return 0;
	168	}
	169
	170	static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	171	{
	172	struct tegra_rtc_info *info = dev_get_drvdata(dev);
c6af561a TR	173	unsigned long flags;
c6af561a TR	174	u32 status;
ff859ba6 AC	175
ff859ba6 AC	176	tegra_rtc_wait_while_busy(dev);
c6af561a	177	spin_lock_irqsave(&info->lock, flags);
ff859ba6	178
a2d29238	179	/* read the original value, and OR in the flag */
c6af561a	180	status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
ff859ba6 AC	181	if (enabled)
	182	status \|= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
	183	else
	184	status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
	185
c6af561a	186	writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
ff859ba6	187
c6af561a	188	spin_unlock_irqrestore(&info->lock, flags);
ff859ba6 AC	189
	190	return 0;
	191	}
	192
	193	static int tegra_rtc_set_alarm(struct device dev, struct rtc_wkalrm alarm)
	194	{
	195	struct tegra_rtc_info *info = dev_get_drvdata(dev);
c6af561a	196	u32 sec;
ff859ba6 AC	197
ff859ba6 AC	198	if (alarm->enabled)
34ea0ac3	199	sec = rtc_tm_to_time64(&alarm->time);
ff859ba6 AC	200	else
	201	sec = 0;
	202
	203	tegra_rtc_wait_while_busy(dev);
c6af561a	204	writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
ff859ba6	205	dev_vdbg(dev, "alarm read back as %d\n",
c6af561a	206	readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
ff859ba6 AC	207
	208	/* if successfully written and alarm is enabled ... */
	209	if (sec) {
	210	tegra_rtc_alarm_irq_enable(dev, 1);
a2d29238	211	dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
ff859ba6	212	} else {
a2d29238	213	/* disable alarm if 0 or write error */
ff859ba6 AC	214	dev_vdbg(dev, "alarm disabled\n");
	215	tegra_rtc_alarm_irq_enable(dev, 0);
	216	}
	217
	218	return 0;
	219	}
	220
	221	static int tegra_rtc_proc(struct device dev, struct seq_file seq)
	222	{
	223	if (!dev \|\| !dev->driver)
	224	return 0;
	225
4395eb1f JP	226	seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
	227
	228	return 0;
ff859ba6 AC	229	}
	230
	231	static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
	232	{
	233	struct device *dev = data;
	234	struct tegra_rtc_info *info = dev_get_drvdata(dev);
669022c2	235	unsigned long events = 0;
c6af561a	236	u32 status;
ff859ba6	237
c6af561a	238	status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
ff859ba6	239	if (status) {
a2d29238	240	/* clear the interrupt masks and status on any IRQ */
ff859ba6	241	tegra_rtc_wait_while_busy(dev);
a2d29238	242
669022c2	243	spin_lock(&info->lock);
c6af561a TR	244	writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
c6af561a TR	245	writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
669022c2	246	spin_unlock(&info->lock);
ff859ba6 AC	247	}
ff859ba6 AC	248
a2d29238 TR	249	/* check if alarm */
a2d29238 TR	250	if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
ff859ba6 AC	251	events \|= RTC_IRQF \| RTC_AF;
ff859ba6 AC	252
a2d29238 TR	253	/* check if periodic */
a2d29238 TR	254	if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
ff859ba6 AC	255	events \|= RTC_IRQF \| RTC_PF;
ff859ba6 AC	256
c6af561a	257	rtc_update_irq(info->rtc, 1, events);
ff859ba6 AC	258
	259	return IRQ_HANDLED;
	260	}
	261
34c7b3ac	262	static const struct rtc_class_ops tegra_rtc_ops = {
a2d29238 TR	263	.read_time = tegra_rtc_read_time,
	264	.set_time = tegra_rtc_set_time,
	265	.read_alarm = tegra_rtc_read_alarm,
	266	.set_alarm = tegra_rtc_set_alarm,
	267	.proc = tegra_rtc_proc,
ff859ba6 AC	268	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
	269	};
	270
2d79cf8a JL	271	static const struct of_device_id tegra_rtc_dt_match[] = {
	272	{ .compatible = "nvidia,tegra20-rtc", },
	273	{}
	274	};
	275	MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
	276
3e483e59	277	static int tegra_rtc_probe(struct platform_device *pdev)
ff859ba6 AC	278	{
ff859ba6 AC	279	struct tegra_rtc_info *info;
ff859ba6 AC	280	int ret;
ff859ba6 AC	281
a2d29238	282	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
ff859ba6 AC	283	if (!info)
	284	return -ENOMEM;
	285
09ef18bc	286	info->base = devm_platform_ioremap_resource(pdev, 0);
c6af561a TR	287	if (IS_ERR(info->base))
c6af561a TR	288	return PTR_ERR(info->base);
ff859ba6	289
fe0b5ced	290	ret = platform_get_irq(pdev, 0);
faac9102	291	if (ret <= 0)
fe0b5ced	292	return ret;
fe0b5ced	293
c6af561a	294	info->irq = ret;
ff859ba6	295
c6af561a TR	296	info->rtc = devm_rtc_allocate_device(&pdev->dev);
	297	if (IS_ERR(info->rtc))
	298	return PTR_ERR(info->rtc);
e1089802	299
c6af561a TR	300	info->rtc->ops = &tegra_rtc_ops;
c6af561a TR	301	info->rtc->range_max = U32_MAX;
e1089802	302
5fa40869 TR	303	info->clk = devm_clk_get(&pdev->dev, NULL);
	304	if (IS_ERR(info->clk))
	305	return PTR_ERR(info->clk);
	306
	307	ret = clk_prepare_enable(info->clk);
	308	if (ret < 0)
	309	return ret;
	310
a2d29238	311	/* set context info */
ff859ba6	312	info->pdev = pdev;
c6af561a	313	spin_lock_init(&info->lock);
ff859ba6 AC	314
	315	platform_set_drvdata(pdev, info);
	316
a2d29238	317	/* clear out the hardware */
c6af561a TR	318	writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
	319	writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
	320	writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
ff859ba6 AC	321
	322	device_init_wakeup(&pdev->dev, 1);
	323
c6af561a TR	324	ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
	325	IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
	326	&pdev->dev);
ff859ba6	327	if (ret) {
a2d29238	328	dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
e1089802 AB	329	goto disable_clk;
	330	}
	331
fdcfd854	332	ret = devm_rtc_register_device(info->rtc);
44c638ce	333	if (ret)
5fa40869	334	goto disable_clk;
ff859ba6 AC	335
	336	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
	337
5fa40869 TR	338	return 0;
	339
	340	disable_clk:
	341	clk_disable_unprepare(info->clk);
	342	return ret;
	343	}
	344
	345	static int tegra_rtc_remove(struct platform_device *pdev)
	346	{
	347	struct tegra_rtc_info *info = platform_get_drvdata(pdev);
	348
	349	clk_disable_unprepare(info->clk);
	350
ff859ba6 AC	351	return 0;
	352	}
	353
38a6276e	354	#ifdef CONFIG_PM_SLEEP
3443ad09	355	static int tegra_rtc_suspend(struct device *dev)
ff859ba6	356	{
3443ad09	357	struct tegra_rtc_info *info = dev_get_drvdata(dev);
ff859ba6 AC	358
	359	tegra_rtc_wait_while_busy(dev);
	360
a2d29238	361	/* only use ALARM0 as a wake source */
c6af561a	362	writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
ff859ba6	363	writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
c6af561a	364	info->base + TEGRA_RTC_REG_INTR_MASK);
ff859ba6 AC	365
ff859ba6 AC	366	dev_vdbg(dev, "alarm sec = %d\n",
c6af561a	367	readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
ff859ba6	368
a2d29238	369	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
c6af561a	370	device_may_wakeup(dev), info->irq);
ff859ba6	371
a2d29238	372	/* leave the alarms on as a wake source */
ff859ba6	373	if (device_may_wakeup(dev))
c6af561a	374	enable_irq_wake(info->irq);
ff859ba6 AC	375
	376	return 0;
	377	}
	378
3443ad09	379	static int tegra_rtc_resume(struct device *dev)
ff859ba6	380	{
3443ad09	381	struct tegra_rtc_info *info = dev_get_drvdata(dev);
ff859ba6 AC	382
ff859ba6 AC	383	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
a2d29238 TR	384	device_may_wakeup(dev));
	385
	386	/* alarms were left on as a wake source, turn them off */
ff859ba6	387	if (device_may_wakeup(dev))
c6af561a	388	disable_irq_wake(info->irq);
ff859ba6 AC	389
	390	return 0;
	391	}
	392	#endif
	393
3443ad09 LD	394	static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
3443ad09 LD	395
ff859ba6 AC	396	static void tegra_rtc_shutdown(struct platform_device *pdev)
ff859ba6 AC	397	{
a2d29238	398	dev_vdbg(&pdev->dev, "disabling interrupts\n");
ff859ba6 AC	399	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
	400	}
	401
ff859ba6	402	static struct platform_driver tegra_rtc_driver = {
3e483e59	403	.probe = tegra_rtc_probe,
a2d29238 TR	404	.remove = tegra_rtc_remove,
	405	.shutdown = tegra_rtc_shutdown,
	406	.driver = {
	407	.name = "tegra_rtc",
2d79cf8a	408	.of_match_table = tegra_rtc_dt_match,
a2d29238	409	.pm = &tegra_rtc_pm_ops,
ff859ba6	410	},
ff859ba6	411	};
3e483e59	412	module_platform_driver(tegra_rtc_driver);
ff859ba6 AC	413
	414	MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
	415	MODULE_DESCRIPTION("driver for Tegra internal RTC");
	416	MODULE_LICENSE("GPL");