Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
9765d2d9 CYT |
2 | /* |
3 | * An RTC driver for Allwinner A31/A23 | |
4 | * | |
5 | * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> | |
6 | * | |
7 | * based on rtc-sunxi.c | |
8 | * | |
9 | * An RTC driver for Allwinner A10/A20 | |
10 | * | |
11 | * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> | |
9765d2d9 CYT |
12 | */ |
13 | ||
3855c2c3 MR |
14 | #include <linux/clk.h> |
15 | #include <linux/clk-provider.h> | |
9765d2d9 CYT |
16 | #include <linux/delay.h> |
17 | #include <linux/err.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/rtc.h> | |
3855c2c3 | 29 | #include <linux/slab.h> |
9765d2d9 CYT |
30 | #include <linux/types.h> |
31 | ||
32 | /* Control register */ | |
33 | #define SUN6I_LOSC_CTRL 0x0000 | |
fb61bb82 | 34 | #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) |
b60ff2cf | 35 | #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) |
9765d2d9 CYT |
36 | #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) |
37 | #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) | |
38 | #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) | |
b60ff2cf | 39 | #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) |
fb61bb82 | 40 | #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) |
9765d2d9 CYT |
41 | #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) |
42 | ||
3855c2c3 MR |
43 | #define SUN6I_LOSC_CLK_PRESCAL 0x0008 |
44 | ||
9765d2d9 CYT |
45 | /* RTC */ |
46 | #define SUN6I_RTC_YMD 0x0010 | |
47 | #define SUN6I_RTC_HMS 0x0014 | |
48 | ||
49 | /* Alarm 0 (counter) */ | |
50 | #define SUN6I_ALRM_COUNTER 0x0020 | |
51 | #define SUN6I_ALRM_CUR_VAL 0x0024 | |
52 | #define SUN6I_ALRM_EN 0x0028 | |
53 | #define SUN6I_ALRM_EN_CNT_EN BIT(0) | |
54 | #define SUN6I_ALRM_IRQ_EN 0x002c | |
55 | #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) | |
56 | #define SUN6I_ALRM_IRQ_STA 0x0030 | |
57 | #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) | |
58 | ||
59 | /* Alarm 1 (wall clock) */ | |
60 | #define SUN6I_ALRM1_EN 0x0044 | |
61 | #define SUN6I_ALRM1_IRQ_EN 0x0048 | |
62 | #define SUN6I_ALRM1_IRQ_STA 0x004c | |
63 | #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) | |
64 | ||
65 | /* Alarm config */ | |
66 | #define SUN6I_ALARM_CONFIG 0x0050 | |
67 | #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) | |
68 | ||
17ecd246 | 69 | #define SUN6I_LOSC_OUT_GATING 0x0060 |
09018d4b | 70 | #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 |
17ecd246 | 71 | |
9765d2d9 CYT |
72 | /* |
73 | * Get date values | |
74 | */ | |
75 | #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) | |
76 | #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) | |
77 | #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) | |
78 | #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) | |
79 | ||
80 | /* | |
81 | * Get time values | |
82 | */ | |
83 | #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) | |
84 | #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) | |
85 | #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) | |
86 | ||
87 | /* | |
88 | * Set date values | |
89 | */ | |
90 | #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) | |
91 | #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) | |
92 | #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) | |
93 | #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) | |
94 | ||
95 | /* | |
96 | * Set time values | |
97 | */ | |
98 | #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) | |
99 | #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) | |
100 | #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) | |
101 | ||
102 | /* | |
103 | * The year parameter passed to the driver is usually an offset relative to | |
104 | * the year 1900. This macro is used to convert this offset to another one | |
105 | * relative to the minimum year allowed by the hardware. | |
106 | * | |
107 | * The year range is 1970 - 2033. This range is selected to match Allwinner's | |
108 | * driver, even though it is somewhat limited. | |
109 | */ | |
110 | #define SUN6I_YEAR_MIN 1970 | |
9765d2d9 CYT |
111 | #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) |
112 | ||
403a3c3d CYT |
113 | /* |
114 | * There are other differences between models, including: | |
115 | * | |
116 | * - number of GPIO pins that can be configured to hold a certain level | |
117 | * - crypto-key related registers (H5, H6) | |
118 | * - boot process related (super standby, secondary processor entry address) | |
119 | * registers (R40, H6) | |
120 | * - SYS power domain controls (R40) | |
121 | * - DCXO controls (H6) | |
122 | * - RC oscillator calibration (H6) | |
123 | * | |
124 | * These functions are not covered by this driver. | |
125 | */ | |
126 | struct sun6i_rtc_clk_data { | |
127 | unsigned long rc_osc_rate; | |
128 | unsigned int fixed_prescaler : 16; | |
129 | unsigned int has_prescaler : 1; | |
130 | unsigned int has_out_clk : 1; | |
c56afc18 | 131 | unsigned int export_iosc : 1; |
b60ff2cf OJ |
132 | unsigned int has_losc_en : 1; |
133 | unsigned int has_auto_swt : 1; | |
403a3c3d CYT |
134 | }; |
135 | ||
9765d2d9 CYT |
136 | struct sun6i_rtc_dev { |
137 | struct rtc_device *rtc; | |
403a3c3d | 138 | const struct sun6i_rtc_clk_data *data; |
9765d2d9 CYT |
139 | void __iomem *base; |
140 | int irq; | |
141 | unsigned long alarm; | |
a9422a19 | 142 | |
3855c2c3 MR |
143 | struct clk_hw hw; |
144 | struct clk_hw *int_osc; | |
145 | struct clk *losc; | |
17ecd246 | 146 | struct clk *ext_losc; |
3855c2c3 | 147 | |
a9422a19 | 148 | spinlock_t lock; |
9765d2d9 CYT |
149 | }; |
150 | ||
3855c2c3 MR |
151 | static struct sun6i_rtc_dev *sun6i_rtc; |
152 | ||
153 | static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, | |
154 | unsigned long parent_rate) | |
155 | { | |
156 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
403a3c3d | 157 | u32 val = 0; |
3855c2c3 MR |
158 | |
159 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
160 | if (val & SUN6I_LOSC_CTRL_EXT_OSC) | |
161 | return parent_rate; | |
162 | ||
403a3c3d CYT |
163 | if (rtc->data->fixed_prescaler) |
164 | parent_rate /= rtc->data->fixed_prescaler; | |
165 | ||
166 | if (rtc->data->has_prescaler) { | |
167 | val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); | |
168 | val &= GENMASK(4, 0); | |
169 | } | |
3855c2c3 MR |
170 | |
171 | return parent_rate / (val + 1); | |
172 | } | |
173 | ||
174 | static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) | |
175 | { | |
176 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
177 | ||
178 | return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; | |
179 | } | |
180 | ||
181 | static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) | |
182 | { | |
183 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
184 | unsigned long flags; | |
185 | u32 val; | |
186 | ||
187 | if (index > 1) | |
188 | return -EINVAL; | |
189 | ||
190 | spin_lock_irqsave(&rtc->lock, flags); | |
191 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
192 | val &= ~SUN6I_LOSC_CTRL_EXT_OSC; | |
193 | val |= SUN6I_LOSC_CTRL_KEY; | |
194 | val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; | |
b60ff2cf OJ |
195 | if (rtc->data->has_losc_en) { |
196 | val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; | |
197 | val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; | |
198 | } | |
3855c2c3 MR |
199 | writel(val, rtc->base + SUN6I_LOSC_CTRL); |
200 | spin_unlock_irqrestore(&rtc->lock, flags); | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static const struct clk_ops sun6i_rtc_osc_ops = { | |
206 | .recalc_rate = sun6i_rtc_osc_recalc_rate, | |
207 | ||
208 | .get_parent = sun6i_rtc_osc_get_parent, | |
209 | .set_parent = sun6i_rtc_osc_set_parent, | |
210 | }; | |
211 | ||
403a3c3d CYT |
212 | static void __init sun6i_rtc_clk_init(struct device_node *node, |
213 | const struct sun6i_rtc_clk_data *data) | |
3855c2c3 MR |
214 | { |
215 | struct clk_hw_onecell_data *clk_data; | |
216 | struct sun6i_rtc_dev *rtc; | |
217 | struct clk_init_data init = { | |
218 | .ops = &sun6i_rtc_osc_ops, | |
459b6ea0 | 219 | .name = "losc", |
3855c2c3 | 220 | }; |
c56afc18 | 221 | const char *iosc_name = "rtc-int-osc"; |
17ecd246 | 222 | const char *clkout_name = "osc32k-out"; |
3855c2c3 | 223 | const char *parents[2]; |
b60ff2cf | 224 | u32 reg; |
3855c2c3 MR |
225 | |
226 | rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); | |
227 | if (!rtc) | |
228 | return; | |
3855c2c3 | 229 | |
403a3c3d | 230 | rtc->data = data; |
c56afc18 | 231 | clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); |
e9982024 CIK |
232 | if (!clk_data) { |
233 | kfree(rtc); | |
3855c2c3 | 234 | return; |
e9982024 | 235 | } |
319ff835 | 236 | |
3855c2c3 MR |
237 | spin_lock_init(&rtc->lock); |
238 | ||
239 | rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); | |
aaa65a9c | 240 | if (IS_ERR(rtc->base)) { |
3855c2c3 | 241 | pr_crit("Can't map RTC registers"); |
1a37c348 | 242 | goto err; |
3855c2c3 MR |
243 | } |
244 | ||
b60ff2cf OJ |
245 | reg = SUN6I_LOSC_CTRL_KEY; |
246 | if (rtc->data->has_auto_swt) { | |
247 | /* Bypass auto-switch to int osc, on ext losc failure */ | |
248 | reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; | |
249 | writel(reg, rtc->base + SUN6I_LOSC_CTRL); | |
250 | } | |
251 | ||
ec98a875 JS |
252 | /* Switch to the external, more precise, oscillator, if present */ |
253 | if (of_get_property(node, "clocks", NULL)) { | |
254 | reg |= SUN6I_LOSC_CTRL_EXT_OSC; | |
255 | if (rtc->data->has_losc_en) | |
256 | reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; | |
257 | } | |
b60ff2cf | 258 | writel(reg, rtc->base + SUN6I_LOSC_CTRL); |
3855c2c3 | 259 | |
15829cf4 CYT |
260 | /* Yes, I know, this is ugly. */ |
261 | sun6i_rtc = rtc; | |
262 | ||
c56afc18 CYT |
263 | /* Only read IOSC name from device tree if it is exported */ |
264 | if (rtc->data->export_iosc) | |
265 | of_property_read_string_index(node, "clock-output-names", 2, | |
266 | &iosc_name); | |
267 | ||
3855c2c3 | 268 | rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, |
c56afc18 | 269 | iosc_name, |
3855c2c3 | 270 | NULL, 0, |
403a3c3d | 271 | rtc->data->rc_osc_rate, |
3855c2c3 MR |
272 | 300000000); |
273 | if (IS_ERR(rtc->int_osc)) { | |
274 | pr_crit("Couldn't register the internal oscillator\n"); | |
28d21191 | 275 | goto err; |
3855c2c3 MR |
276 | } |
277 | ||
278 | parents[0] = clk_hw_get_name(rtc->int_osc); | |
ec98a875 | 279 | /* If there is no external oscillator, this will be NULL and ... */ |
3855c2c3 MR |
280 | parents[1] = of_clk_get_parent_name(node, 0); |
281 | ||
282 | rtc->hw.init = &init; | |
283 | ||
284 | init.parent_names = parents; | |
ec98a875 | 285 | /* ... number of clock parents will be 1. */ |
3855c2c3 | 286 | init.num_parents = of_clk_get_parent_count(node) + 1; |
17ecd246 MR |
287 | of_property_read_string_index(node, "clock-output-names", 0, |
288 | &init.name); | |
3855c2c3 MR |
289 | |
290 | rtc->losc = clk_register(NULL, &rtc->hw); | |
291 | if (IS_ERR(rtc->losc)) { | |
292 | pr_crit("Couldn't register the LOSC clock\n"); | |
28d21191 | 293 | goto err_register; |
3855c2c3 MR |
294 | } |
295 | ||
17ecd246 MR |
296 | of_property_read_string_index(node, "clock-output-names", 1, |
297 | &clkout_name); | |
21ef77de | 298 | rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, |
17ecd246 | 299 | 0, rtc->base + SUN6I_LOSC_OUT_GATING, |
09018d4b | 300 | SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, |
17ecd246 MR |
301 | &rtc->lock); |
302 | if (IS_ERR(rtc->ext_losc)) { | |
303 | pr_crit("Couldn't register the LOSC external gate\n"); | |
28d21191 | 304 | goto err_register; |
17ecd246 MR |
305 | } |
306 | ||
307 | clk_data->num = 2; | |
3855c2c3 | 308 | clk_data->hws[0] = &rtc->hw; |
17ecd246 | 309 | clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); |
c56afc18 CYT |
310 | if (rtc->data->export_iosc) { |
311 | clk_data->hws[2] = rtc->int_osc; | |
312 | clk_data->num = 3; | |
313 | } | |
3855c2c3 | 314 | of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); |
1a37c348 CIK |
315 | return; |
316 | ||
28d21191 DL |
317 | err_register: |
318 | clk_hw_unregister_fixed_rate(rtc->int_osc); | |
1a37c348 CIK |
319 | err: |
320 | kfree(clk_data); | |
3855c2c3 | 321 | } |
403a3c3d CYT |
322 | |
323 | static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { | |
324 | .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ | |
325 | .has_prescaler = 1, | |
326 | }; | |
327 | ||
328 | static void __init sun6i_a31_rtc_clk_init(struct device_node *node) | |
329 | { | |
330 | sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); | |
331 | } | |
332 | CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", | |
333 | sun6i_a31_rtc_clk_init); | |
3855c2c3 | 334 | |
7cd1acae CYT |
335 | static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { |
336 | .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ | |
337 | .has_prescaler = 1, | |
338 | .has_out_clk = 1, | |
339 | }; | |
340 | ||
341 | static void __init sun8i_a23_rtc_clk_init(struct device_node *node) | |
342 | { | |
343 | sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); | |
344 | } | |
345 | CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", | |
346 | sun8i_a23_rtc_clk_init); | |
347 | ||
348 | static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { | |
349 | .rc_osc_rate = 16000000, | |
350 | .fixed_prescaler = 32, | |
351 | .has_prescaler = 1, | |
352 | .has_out_clk = 1, | |
c56afc18 | 353 | .export_iosc = 1, |
7cd1acae CYT |
354 | }; |
355 | ||
356 | static void __init sun8i_h3_rtc_clk_init(struct device_node *node) | |
357 | { | |
358 | sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); | |
359 | } | |
360 | CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", | |
361 | sun8i_h3_rtc_clk_init); | |
362 | /* As far as we are concerned, clocks for H5 are the same as H3 */ | |
363 | CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", | |
364 | sun8i_h3_rtc_clk_init); | |
365 | ||
b60ff2cf OJ |
366 | static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { |
367 | .rc_osc_rate = 16000000, | |
368 | .fixed_prescaler = 32, | |
369 | .has_prescaler = 1, | |
370 | .has_out_clk = 1, | |
371 | .export_iosc = 1, | |
372 | .has_losc_en = 1, | |
373 | .has_auto_swt = 1, | |
374 | }; | |
375 | ||
376 | static void __init sun50i_h6_rtc_clk_init(struct device_node *node) | |
377 | { | |
378 | sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); | |
379 | } | |
380 | CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", | |
381 | sun50i_h6_rtc_clk_init); | |
382 | ||
111bf02b CYT |
383 | /* |
384 | * The R40 user manual is self-conflicting on whether the prescaler is | |
385 | * fixed or configurable. The clock diagram shows it as fixed, but there | |
386 | * is also a configurable divider in the RTC block. | |
387 | */ | |
388 | static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { | |
389 | .rc_osc_rate = 16000000, | |
390 | .fixed_prescaler = 512, | |
391 | }; | |
392 | static void __init sun8i_r40_rtc_clk_init(struct device_node *node) | |
393 | { | |
394 | sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); | |
395 | } | |
396 | CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", | |
397 | sun8i_r40_rtc_clk_init); | |
398 | ||
7cd1acae CYT |
399 | static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { |
400 | .rc_osc_rate = 32000, | |
401 | .has_out_clk = 1, | |
402 | }; | |
403 | ||
404 | static void __init sun8i_v3_rtc_clk_init(struct device_node *node) | |
405 | { | |
406 | sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); | |
407 | } | |
408 | CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", | |
409 | sun8i_v3_rtc_clk_init); | |
410 | ||
9765d2d9 CYT |
411 | static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) |
412 | { | |
413 | struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; | |
a9422a19 | 414 | irqreturn_t ret = IRQ_NONE; |
9765d2d9 CYT |
415 | u32 val; |
416 | ||
a9422a19 | 417 | spin_lock(&chip->lock); |
9765d2d9 CYT |
418 | val = readl(chip->base + SUN6I_ALRM_IRQ_STA); |
419 | ||
420 | if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { | |
421 | val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; | |
422 | writel(val, chip->base + SUN6I_ALRM_IRQ_STA); | |
423 | ||
424 | rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); | |
425 | ||
a9422a19 | 426 | ret = IRQ_HANDLED; |
9765d2d9 | 427 | } |
a9422a19 | 428 | spin_unlock(&chip->lock); |
9765d2d9 | 429 | |
a9422a19 | 430 | return ret; |
9765d2d9 CYT |
431 | } |
432 | ||
433 | static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) | |
434 | { | |
435 | u32 alrm_val = 0; | |
436 | u32 alrm_irq_val = 0; | |
437 | u32 alrm_wake_val = 0; | |
a9422a19 | 438 | unsigned long flags; |
9765d2d9 CYT |
439 | |
440 | if (to) { | |
441 | alrm_val = SUN6I_ALRM_EN_CNT_EN; | |
442 | alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; | |
443 | alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; | |
444 | } else { | |
445 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
446 | chip->base + SUN6I_ALRM_IRQ_STA); | |
447 | } | |
448 | ||
a9422a19 | 449 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
450 | writel(alrm_val, chip->base + SUN6I_ALRM_EN); |
451 | writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); | |
452 | writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); | |
a9422a19 | 453 | spin_unlock_irqrestore(&chip->lock, flags); |
9765d2d9 CYT |
454 | } |
455 | ||
456 | static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
457 | { | |
458 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
459 | u32 date, time; | |
460 | ||
461 | /* | |
462 | * read again in case it changes | |
463 | */ | |
464 | do { | |
465 | date = readl(chip->base + SUN6I_RTC_YMD); | |
466 | time = readl(chip->base + SUN6I_RTC_HMS); | |
467 | } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || | |
468 | (time != readl(chip->base + SUN6I_RTC_HMS))); | |
469 | ||
470 | rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); | |
471 | rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); | |
472 | rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); | |
473 | ||
474 | rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); | |
475 | rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date); | |
476 | rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); | |
477 | ||
478 | rtc_tm->tm_mon -= 1; | |
479 | ||
480 | /* | |
481 | * switch from (data_year->min)-relative offset to | |
482 | * a (1900)-relative one | |
483 | */ | |
484 | rtc_tm->tm_year += SUN6I_YEAR_OFF; | |
485 | ||
22652ba7 | 486 | return 0; |
9765d2d9 CYT |
487 | } |
488 | ||
489 | static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
490 | { | |
491 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
a9422a19 | 492 | unsigned long flags; |
9765d2d9 CYT |
493 | u32 alrm_st; |
494 | u32 alrm_en; | |
495 | ||
a9422a19 | 496 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
497 | alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); |
498 | alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); | |
a9422a19 MR |
499 | spin_unlock_irqrestore(&chip->lock, flags); |
500 | ||
9765d2d9 CYT |
501 | wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); |
502 | wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); | |
99b7ac9c | 503 | rtc_time64_to_tm(chip->alarm, &wkalrm->time); |
9765d2d9 CYT |
504 | |
505 | return 0; | |
506 | } | |
507 | ||
508 | static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
509 | { | |
510 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
511 | struct rtc_time *alrm_tm = &wkalrm->time; | |
512 | struct rtc_time tm_now; | |
513 | unsigned long time_now = 0; | |
514 | unsigned long time_set = 0; | |
515 | unsigned long time_gap = 0; | |
516 | int ret = 0; | |
517 | ||
518 | ret = sun6i_rtc_gettime(dev, &tm_now); | |
519 | if (ret < 0) { | |
520 | dev_err(dev, "Error in getting time\n"); | |
521 | return -EINVAL; | |
522 | } | |
523 | ||
99b7ac9c AB |
524 | time_set = rtc_tm_to_time64(alrm_tm); |
525 | time_now = rtc_tm_to_time64(&tm_now); | |
9765d2d9 CYT |
526 | if (time_set <= time_now) { |
527 | dev_err(dev, "Date to set in the past\n"); | |
528 | return -EINVAL; | |
529 | } | |
530 | ||
531 | time_gap = time_set - time_now; | |
532 | ||
533 | if (time_gap > U32_MAX) { | |
534 | dev_err(dev, "Date too far in the future\n"); | |
535 | return -EINVAL; | |
536 | } | |
537 | ||
538 | sun6i_rtc_setaie(0, chip); | |
539 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
540 | usleep_range(100, 300); | |
541 | ||
542 | writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); | |
543 | chip->alarm = time_set; | |
544 | ||
545 | sun6i_rtc_setaie(wkalrm->enabled, chip); | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
550 | static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, | |
551 | unsigned int mask, unsigned int ms_timeout) | |
552 | { | |
553 | const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); | |
554 | u32 reg; | |
555 | ||
556 | do { | |
557 | reg = readl(chip->base + offset); | |
558 | reg &= mask; | |
559 | ||
560 | if (!reg) | |
561 | return 0; | |
562 | ||
563 | } while (time_before(jiffies, timeout)); | |
564 | ||
565 | return -ETIMEDOUT; | |
566 | } | |
567 | ||
568 | static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) | |
569 | { | |
570 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
571 | u32 date = 0; | |
572 | u32 time = 0; | |
9765d2d9 CYT |
573 | |
574 | rtc_tm->tm_year -= SUN6I_YEAR_OFF; | |
575 | rtc_tm->tm_mon += 1; | |
576 | ||
577 | date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | | |
578 | SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | | |
579 | SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); | |
580 | ||
8ae79be7 | 581 | if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) |
9765d2d9 CYT |
582 | date |= SUN6I_LEAP_SET_VALUE(1); |
583 | ||
584 | time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | | |
585 | SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | | |
586 | SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); | |
587 | ||
588 | /* Check whether registers are writable */ | |
589 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
590 | SUN6I_LOSC_CTRL_ACC_MASK, 50)) { | |
591 | dev_err(dev, "rtc is still busy.\n"); | |
592 | return -EBUSY; | |
593 | } | |
594 | ||
595 | writel(time, chip->base + SUN6I_RTC_HMS); | |
596 | ||
597 | /* | |
598 | * After writing the RTC HH-MM-SS register, the | |
599 | * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not | |
600 | * be cleared until the real writing operation is finished | |
601 | */ | |
602 | ||
603 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
604 | SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { | |
605 | dev_err(dev, "Failed to set rtc time.\n"); | |
606 | return -ETIMEDOUT; | |
607 | } | |
608 | ||
609 | writel(date, chip->base + SUN6I_RTC_YMD); | |
610 | ||
611 | /* | |
612 | * After writing the RTC YY-MM-DD register, the | |
613 | * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not | |
614 | * be cleared until the real writing operation is finished | |
615 | */ | |
616 | ||
617 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
618 | SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { | |
619 | dev_err(dev, "Failed to set rtc time.\n"); | |
620 | return -ETIMEDOUT; | |
621 | } | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
626 | static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
627 | { | |
628 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
629 | ||
630 | if (!enabled) | |
631 | sun6i_rtc_setaie(enabled, chip); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static const struct rtc_class_ops sun6i_rtc_ops = { | |
637 | .read_time = sun6i_rtc_gettime, | |
638 | .set_time = sun6i_rtc_settime, | |
639 | .read_alarm = sun6i_rtc_getalarm, | |
640 | .set_alarm = sun6i_rtc_setalarm, | |
641 | .alarm_irq_enable = sun6i_rtc_alarm_irq_enable | |
642 | }; | |
643 | ||
d76a81d0 AG |
644 | #ifdef CONFIG_PM_SLEEP |
645 | /* Enable IRQ wake on suspend, to wake up from RTC. */ | |
646 | static int sun6i_rtc_suspend(struct device *dev) | |
647 | { | |
648 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
649 | ||
650 | if (device_may_wakeup(dev)) | |
651 | enable_irq_wake(chip->irq); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | /* Disable IRQ wake on resume. */ | |
657 | static int sun6i_rtc_resume(struct device *dev) | |
658 | { | |
659 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
660 | ||
661 | if (device_may_wakeup(dev)) | |
662 | disable_irq_wake(chip->irq); | |
663 | ||
664 | return 0; | |
665 | } | |
666 | #endif | |
667 | ||
668 | static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, | |
669 | sun6i_rtc_suspend, sun6i_rtc_resume); | |
670 | ||
9765d2d9 CYT |
671 | static int sun6i_rtc_probe(struct platform_device *pdev) |
672 | { | |
3855c2c3 | 673 | struct sun6i_rtc_dev *chip = sun6i_rtc; |
9765d2d9 CYT |
674 | int ret; |
675 | ||
9765d2d9 | 676 | if (!chip) |
3855c2c3 | 677 | return -ENODEV; |
9765d2d9 CYT |
678 | |
679 | platform_set_drvdata(pdev, chip); | |
9765d2d9 | 680 | |
9765d2d9 | 681 | chip->irq = platform_get_irq(pdev, 0); |
faac9102 | 682 | if (chip->irq < 0) |
9765d2d9 | 683 | return chip->irq; |
9765d2d9 CYT |
684 | |
685 | ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, | |
686 | 0, dev_name(&pdev->dev), chip); | |
687 | if (ret) { | |
688 | dev_err(&pdev->dev, "Could not request IRQ\n"); | |
689 | return ret; | |
690 | } | |
691 | ||
692 | /* clear the alarm counter value */ | |
693 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
694 | ||
695 | /* disable counter alarm */ | |
696 | writel(0, chip->base + SUN6I_ALRM_EN); | |
697 | ||
698 | /* disable counter alarm interrupt */ | |
699 | writel(0, chip->base + SUN6I_ALRM_IRQ_EN); | |
700 | ||
701 | /* disable week alarm */ | |
702 | writel(0, chip->base + SUN6I_ALRM1_EN); | |
703 | ||
704 | /* disable week alarm interrupt */ | |
705 | writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); | |
706 | ||
707 | /* clear counter alarm pending interrupts */ | |
708 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
709 | chip->base + SUN6I_ALRM_IRQ_STA); | |
710 | ||
711 | /* clear week alarm pending interrupts */ | |
712 | writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, | |
713 | chip->base + SUN6I_ALRM1_IRQ_STA); | |
714 | ||
715 | /* disable alarm wakeup */ | |
716 | writel(0, chip->base + SUN6I_ALARM_CONFIG); | |
717 | ||
3855c2c3 | 718 | clk_prepare_enable(chip->losc); |
fb61bb82 | 719 | |
d76a81d0 AG |
720 | device_init_wakeup(&pdev->dev, 1); |
721 | ||
8ae79be7 AB |
722 | chip->rtc = devm_rtc_allocate_device(&pdev->dev); |
723 | if (IS_ERR(chip->rtc)) | |
9765d2d9 | 724 | return PTR_ERR(chip->rtc); |
8ae79be7 AB |
725 | |
726 | chip->rtc->ops = &sun6i_rtc_ops; | |
727 | chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ | |
728 | ||
fdcfd854 | 729 | ret = devm_rtc_register_device(chip->rtc); |
8ae79be7 AB |
730 | if (ret) |
731 | return ret; | |
9765d2d9 CYT |
732 | |
733 | dev_info(&pdev->dev, "RTC enabled\n"); | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
403a3c3d CYT |
738 | /* |
739 | * As far as RTC functionality goes, all models are the same. The | |
740 | * datasheets claim that different models have different number of | |
741 | * registers available for non-volatile storage, but experiments show | |
742 | * that all SoCs have 16 registers available for this purpose. | |
743 | */ | |
9765d2d9 CYT |
744 | static const struct of_device_id sun6i_rtc_dt_ids[] = { |
745 | { .compatible = "allwinner,sun6i-a31-rtc" }, | |
7cd1acae CYT |
746 | { .compatible = "allwinner,sun8i-a23-rtc" }, |
747 | { .compatible = "allwinner,sun8i-h3-rtc" }, | |
d6624cc7 | 748 | { .compatible = "allwinner,sun8i-r40-rtc" }, |
7cd1acae CYT |
749 | { .compatible = "allwinner,sun8i-v3-rtc" }, |
750 | { .compatible = "allwinner,sun50i-h5-rtc" }, | |
b60ff2cf | 751 | { .compatible = "allwinner,sun50i-h6-rtc" }, |
9765d2d9 CYT |
752 | { /* sentinel */ }, |
753 | }; | |
754 | MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); | |
755 | ||
756 | static struct platform_driver sun6i_rtc_driver = { | |
757 | .probe = sun6i_rtc_probe, | |
9765d2d9 CYT |
758 | .driver = { |
759 | .name = "sun6i-rtc", | |
760 | .of_match_table = sun6i_rtc_dt_ids, | |
d76a81d0 | 761 | .pm = &sun6i_rtc_pm_ops, |
9765d2d9 CYT |
762 | }, |
763 | }; | |
37539414 | 764 | builtin_platform_driver(sun6i_rtc_driver); |