Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
9765d2d9 CYT |
2 | /* |
3 | * An RTC driver for Allwinner A31/A23 | |
4 | * | |
5 | * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> | |
6 | * | |
7 | * based on rtc-sunxi.c | |
8 | * | |
9 | * An RTC driver for Allwinner A10/A20 | |
10 | * | |
11 | * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> | |
9765d2d9 CYT |
12 | */ |
13 | ||
3855c2c3 MR |
14 | #include <linux/clk.h> |
15 | #include <linux/clk-provider.h> | |
9765d2d9 CYT |
16 | #include <linux/delay.h> |
17 | #include <linux/err.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/rtc.h> | |
3855c2c3 | 29 | #include <linux/slab.h> |
9765d2d9 CYT |
30 | #include <linux/types.h> |
31 | ||
32 | /* Control register */ | |
33 | #define SUN6I_LOSC_CTRL 0x0000 | |
fb61bb82 | 34 | #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) |
9765d2d9 CYT |
35 | #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) |
36 | #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) | |
37 | #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) | |
fb61bb82 | 38 | #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) |
9765d2d9 CYT |
39 | #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) |
40 | ||
3855c2c3 MR |
41 | #define SUN6I_LOSC_CLK_PRESCAL 0x0008 |
42 | ||
9765d2d9 CYT |
43 | /* RTC */ |
44 | #define SUN6I_RTC_YMD 0x0010 | |
45 | #define SUN6I_RTC_HMS 0x0014 | |
46 | ||
47 | /* Alarm 0 (counter) */ | |
48 | #define SUN6I_ALRM_COUNTER 0x0020 | |
49 | #define SUN6I_ALRM_CUR_VAL 0x0024 | |
50 | #define SUN6I_ALRM_EN 0x0028 | |
51 | #define SUN6I_ALRM_EN_CNT_EN BIT(0) | |
52 | #define SUN6I_ALRM_IRQ_EN 0x002c | |
53 | #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) | |
54 | #define SUN6I_ALRM_IRQ_STA 0x0030 | |
55 | #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) | |
56 | ||
57 | /* Alarm 1 (wall clock) */ | |
58 | #define SUN6I_ALRM1_EN 0x0044 | |
59 | #define SUN6I_ALRM1_IRQ_EN 0x0048 | |
60 | #define SUN6I_ALRM1_IRQ_STA 0x004c | |
61 | #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) | |
62 | ||
63 | /* Alarm config */ | |
64 | #define SUN6I_ALARM_CONFIG 0x0050 | |
65 | #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) | |
66 | ||
17ecd246 | 67 | #define SUN6I_LOSC_OUT_GATING 0x0060 |
09018d4b | 68 | #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 |
17ecd246 | 69 | |
9765d2d9 CYT |
70 | /* |
71 | * Get date values | |
72 | */ | |
73 | #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) | |
74 | #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) | |
75 | #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) | |
76 | #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) | |
77 | ||
78 | /* | |
79 | * Get time values | |
80 | */ | |
81 | #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) | |
82 | #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) | |
83 | #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) | |
84 | ||
85 | /* | |
86 | * Set date values | |
87 | */ | |
88 | #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) | |
89 | #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) | |
90 | #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) | |
91 | #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) | |
92 | ||
93 | /* | |
94 | * Set time values | |
95 | */ | |
96 | #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) | |
97 | #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) | |
98 | #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) | |
99 | ||
100 | /* | |
101 | * The year parameter passed to the driver is usually an offset relative to | |
102 | * the year 1900. This macro is used to convert this offset to another one | |
103 | * relative to the minimum year allowed by the hardware. | |
104 | * | |
105 | * The year range is 1970 - 2033. This range is selected to match Allwinner's | |
106 | * driver, even though it is somewhat limited. | |
107 | */ | |
108 | #define SUN6I_YEAR_MIN 1970 | |
109 | #define SUN6I_YEAR_MAX 2033 | |
110 | #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) | |
111 | ||
403a3c3d CYT |
112 | /* |
113 | * There are other differences between models, including: | |
114 | * | |
115 | * - number of GPIO pins that can be configured to hold a certain level | |
116 | * - crypto-key related registers (H5, H6) | |
117 | * - boot process related (super standby, secondary processor entry address) | |
118 | * registers (R40, H6) | |
119 | * - SYS power domain controls (R40) | |
120 | * - DCXO controls (H6) | |
121 | * - RC oscillator calibration (H6) | |
122 | * | |
123 | * These functions are not covered by this driver. | |
124 | */ | |
125 | struct sun6i_rtc_clk_data { | |
126 | unsigned long rc_osc_rate; | |
127 | unsigned int fixed_prescaler : 16; | |
128 | unsigned int has_prescaler : 1; | |
129 | unsigned int has_out_clk : 1; | |
c56afc18 | 130 | unsigned int export_iosc : 1; |
403a3c3d CYT |
131 | }; |
132 | ||
9765d2d9 CYT |
133 | struct sun6i_rtc_dev { |
134 | struct rtc_device *rtc; | |
135 | struct device *dev; | |
403a3c3d | 136 | const struct sun6i_rtc_clk_data *data; |
9765d2d9 CYT |
137 | void __iomem *base; |
138 | int irq; | |
139 | unsigned long alarm; | |
a9422a19 | 140 | |
3855c2c3 MR |
141 | struct clk_hw hw; |
142 | struct clk_hw *int_osc; | |
143 | struct clk *losc; | |
17ecd246 | 144 | struct clk *ext_losc; |
3855c2c3 | 145 | |
a9422a19 | 146 | spinlock_t lock; |
9765d2d9 CYT |
147 | }; |
148 | ||
3855c2c3 MR |
149 | static struct sun6i_rtc_dev *sun6i_rtc; |
150 | ||
151 | static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, | |
152 | unsigned long parent_rate) | |
153 | { | |
154 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
403a3c3d | 155 | u32 val = 0; |
3855c2c3 MR |
156 | |
157 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
158 | if (val & SUN6I_LOSC_CTRL_EXT_OSC) | |
159 | return parent_rate; | |
160 | ||
403a3c3d CYT |
161 | if (rtc->data->fixed_prescaler) |
162 | parent_rate /= rtc->data->fixed_prescaler; | |
163 | ||
164 | if (rtc->data->has_prescaler) { | |
165 | val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); | |
166 | val &= GENMASK(4, 0); | |
167 | } | |
3855c2c3 MR |
168 | |
169 | return parent_rate / (val + 1); | |
170 | } | |
171 | ||
172 | static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) | |
173 | { | |
174 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
175 | ||
176 | return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; | |
177 | } | |
178 | ||
179 | static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) | |
180 | { | |
181 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
182 | unsigned long flags; | |
183 | u32 val; | |
184 | ||
185 | if (index > 1) | |
186 | return -EINVAL; | |
187 | ||
188 | spin_lock_irqsave(&rtc->lock, flags); | |
189 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
190 | val &= ~SUN6I_LOSC_CTRL_EXT_OSC; | |
191 | val |= SUN6I_LOSC_CTRL_KEY; | |
192 | val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; | |
193 | writel(val, rtc->base + SUN6I_LOSC_CTRL); | |
194 | spin_unlock_irqrestore(&rtc->lock, flags); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | static const struct clk_ops sun6i_rtc_osc_ops = { | |
200 | .recalc_rate = sun6i_rtc_osc_recalc_rate, | |
201 | ||
202 | .get_parent = sun6i_rtc_osc_get_parent, | |
203 | .set_parent = sun6i_rtc_osc_set_parent, | |
204 | }; | |
205 | ||
403a3c3d CYT |
206 | static void __init sun6i_rtc_clk_init(struct device_node *node, |
207 | const struct sun6i_rtc_clk_data *data) | |
3855c2c3 MR |
208 | { |
209 | struct clk_hw_onecell_data *clk_data; | |
210 | struct sun6i_rtc_dev *rtc; | |
211 | struct clk_init_data init = { | |
212 | .ops = &sun6i_rtc_osc_ops, | |
459b6ea0 | 213 | .name = "losc", |
3855c2c3 | 214 | }; |
c56afc18 | 215 | const char *iosc_name = "rtc-int-osc"; |
17ecd246 | 216 | const char *clkout_name = "osc32k-out"; |
3855c2c3 MR |
217 | const char *parents[2]; |
218 | ||
219 | rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); | |
220 | if (!rtc) | |
221 | return; | |
3855c2c3 | 222 | |
403a3c3d | 223 | rtc->data = data; |
c56afc18 | 224 | clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); |
e9982024 CIK |
225 | if (!clk_data) { |
226 | kfree(rtc); | |
3855c2c3 | 227 | return; |
e9982024 | 228 | } |
319ff835 | 229 | |
3855c2c3 MR |
230 | spin_lock_init(&rtc->lock); |
231 | ||
232 | rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); | |
aaa65a9c | 233 | if (IS_ERR(rtc->base)) { |
3855c2c3 | 234 | pr_crit("Can't map RTC registers"); |
1a37c348 | 235 | goto err; |
3855c2c3 MR |
236 | } |
237 | ||
238 | /* Switch to the external, more precise, oscillator */ | |
239 | writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC, | |
240 | rtc->base + SUN6I_LOSC_CTRL); | |
241 | ||
15829cf4 CYT |
242 | /* Yes, I know, this is ugly. */ |
243 | sun6i_rtc = rtc; | |
244 | ||
3855c2c3 MR |
245 | /* Deal with old DTs */ |
246 | if (!of_get_property(node, "clocks", NULL)) | |
1a37c348 | 247 | goto err; |
3855c2c3 | 248 | |
c56afc18 CYT |
249 | /* Only read IOSC name from device tree if it is exported */ |
250 | if (rtc->data->export_iosc) | |
251 | of_property_read_string_index(node, "clock-output-names", 2, | |
252 | &iosc_name); | |
253 | ||
3855c2c3 | 254 | rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, |
c56afc18 | 255 | iosc_name, |
3855c2c3 | 256 | NULL, 0, |
403a3c3d | 257 | rtc->data->rc_osc_rate, |
3855c2c3 MR |
258 | 300000000); |
259 | if (IS_ERR(rtc->int_osc)) { | |
260 | pr_crit("Couldn't register the internal oscillator\n"); | |
261 | return; | |
262 | } | |
263 | ||
264 | parents[0] = clk_hw_get_name(rtc->int_osc); | |
265 | parents[1] = of_clk_get_parent_name(node, 0); | |
266 | ||
267 | rtc->hw.init = &init; | |
268 | ||
269 | init.parent_names = parents; | |
270 | init.num_parents = of_clk_get_parent_count(node) + 1; | |
17ecd246 MR |
271 | of_property_read_string_index(node, "clock-output-names", 0, |
272 | &init.name); | |
3855c2c3 MR |
273 | |
274 | rtc->losc = clk_register(NULL, &rtc->hw); | |
275 | if (IS_ERR(rtc->losc)) { | |
276 | pr_crit("Couldn't register the LOSC clock\n"); | |
277 | return; | |
278 | } | |
279 | ||
17ecd246 MR |
280 | of_property_read_string_index(node, "clock-output-names", 1, |
281 | &clkout_name); | |
282 | rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name, | |
283 | 0, rtc->base + SUN6I_LOSC_OUT_GATING, | |
09018d4b | 284 | SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, |
17ecd246 MR |
285 | &rtc->lock); |
286 | if (IS_ERR(rtc->ext_losc)) { | |
287 | pr_crit("Couldn't register the LOSC external gate\n"); | |
288 | return; | |
289 | } | |
290 | ||
291 | clk_data->num = 2; | |
3855c2c3 | 292 | clk_data->hws[0] = &rtc->hw; |
17ecd246 | 293 | clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); |
c56afc18 CYT |
294 | if (rtc->data->export_iosc) { |
295 | clk_data->hws[2] = rtc->int_osc; | |
296 | clk_data->num = 3; | |
297 | } | |
3855c2c3 | 298 | of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); |
1a37c348 CIK |
299 | return; |
300 | ||
301 | err: | |
302 | kfree(clk_data); | |
3855c2c3 | 303 | } |
403a3c3d CYT |
304 | |
305 | static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { | |
306 | .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ | |
307 | .has_prescaler = 1, | |
308 | }; | |
309 | ||
310 | static void __init sun6i_a31_rtc_clk_init(struct device_node *node) | |
311 | { | |
312 | sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); | |
313 | } | |
314 | CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", | |
315 | sun6i_a31_rtc_clk_init); | |
3855c2c3 | 316 | |
7cd1acae CYT |
317 | static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { |
318 | .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ | |
319 | .has_prescaler = 1, | |
320 | .has_out_clk = 1, | |
321 | }; | |
322 | ||
323 | static void __init sun8i_a23_rtc_clk_init(struct device_node *node) | |
324 | { | |
325 | sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); | |
326 | } | |
327 | CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", | |
328 | sun8i_a23_rtc_clk_init); | |
329 | ||
330 | static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { | |
331 | .rc_osc_rate = 16000000, | |
332 | .fixed_prescaler = 32, | |
333 | .has_prescaler = 1, | |
334 | .has_out_clk = 1, | |
c56afc18 | 335 | .export_iosc = 1, |
7cd1acae CYT |
336 | }; |
337 | ||
338 | static void __init sun8i_h3_rtc_clk_init(struct device_node *node) | |
339 | { | |
340 | sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); | |
341 | } | |
342 | CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", | |
343 | sun8i_h3_rtc_clk_init); | |
344 | /* As far as we are concerned, clocks for H5 are the same as H3 */ | |
345 | CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", | |
346 | sun8i_h3_rtc_clk_init); | |
347 | ||
348 | static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { | |
349 | .rc_osc_rate = 32000, | |
350 | .has_out_clk = 1, | |
351 | }; | |
352 | ||
353 | static void __init sun8i_v3_rtc_clk_init(struct device_node *node) | |
354 | { | |
355 | sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); | |
356 | } | |
357 | CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", | |
358 | sun8i_v3_rtc_clk_init); | |
359 | ||
9765d2d9 CYT |
360 | static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) |
361 | { | |
362 | struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; | |
a9422a19 | 363 | irqreturn_t ret = IRQ_NONE; |
9765d2d9 CYT |
364 | u32 val; |
365 | ||
a9422a19 | 366 | spin_lock(&chip->lock); |
9765d2d9 CYT |
367 | val = readl(chip->base + SUN6I_ALRM_IRQ_STA); |
368 | ||
369 | if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { | |
370 | val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; | |
371 | writel(val, chip->base + SUN6I_ALRM_IRQ_STA); | |
372 | ||
373 | rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); | |
374 | ||
a9422a19 | 375 | ret = IRQ_HANDLED; |
9765d2d9 | 376 | } |
a9422a19 | 377 | spin_unlock(&chip->lock); |
9765d2d9 | 378 | |
a9422a19 | 379 | return ret; |
9765d2d9 CYT |
380 | } |
381 | ||
382 | static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) | |
383 | { | |
384 | u32 alrm_val = 0; | |
385 | u32 alrm_irq_val = 0; | |
386 | u32 alrm_wake_val = 0; | |
a9422a19 | 387 | unsigned long flags; |
9765d2d9 CYT |
388 | |
389 | if (to) { | |
390 | alrm_val = SUN6I_ALRM_EN_CNT_EN; | |
391 | alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; | |
392 | alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; | |
393 | } else { | |
394 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
395 | chip->base + SUN6I_ALRM_IRQ_STA); | |
396 | } | |
397 | ||
a9422a19 | 398 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
399 | writel(alrm_val, chip->base + SUN6I_ALRM_EN); |
400 | writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); | |
401 | writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); | |
a9422a19 | 402 | spin_unlock_irqrestore(&chip->lock, flags); |
9765d2d9 CYT |
403 | } |
404 | ||
405 | static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
406 | { | |
407 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
408 | u32 date, time; | |
409 | ||
410 | /* | |
411 | * read again in case it changes | |
412 | */ | |
413 | do { | |
414 | date = readl(chip->base + SUN6I_RTC_YMD); | |
415 | time = readl(chip->base + SUN6I_RTC_HMS); | |
416 | } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || | |
417 | (time != readl(chip->base + SUN6I_RTC_HMS))); | |
418 | ||
419 | rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); | |
420 | rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); | |
421 | rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); | |
422 | ||
423 | rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); | |
424 | rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date); | |
425 | rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); | |
426 | ||
427 | rtc_tm->tm_mon -= 1; | |
428 | ||
429 | /* | |
430 | * switch from (data_year->min)-relative offset to | |
431 | * a (1900)-relative one | |
432 | */ | |
433 | rtc_tm->tm_year += SUN6I_YEAR_OFF; | |
434 | ||
22652ba7 | 435 | return 0; |
9765d2d9 CYT |
436 | } |
437 | ||
438 | static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
439 | { | |
440 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
a9422a19 | 441 | unsigned long flags; |
9765d2d9 CYT |
442 | u32 alrm_st; |
443 | u32 alrm_en; | |
444 | ||
a9422a19 | 445 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
446 | alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); |
447 | alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); | |
a9422a19 MR |
448 | spin_unlock_irqrestore(&chip->lock, flags); |
449 | ||
9765d2d9 CYT |
450 | wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); |
451 | wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); | |
452 | rtc_time_to_tm(chip->alarm, &wkalrm->time); | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
458 | { | |
459 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
460 | struct rtc_time *alrm_tm = &wkalrm->time; | |
461 | struct rtc_time tm_now; | |
462 | unsigned long time_now = 0; | |
463 | unsigned long time_set = 0; | |
464 | unsigned long time_gap = 0; | |
465 | int ret = 0; | |
466 | ||
467 | ret = sun6i_rtc_gettime(dev, &tm_now); | |
468 | if (ret < 0) { | |
469 | dev_err(dev, "Error in getting time\n"); | |
470 | return -EINVAL; | |
471 | } | |
472 | ||
473 | rtc_tm_to_time(alrm_tm, &time_set); | |
474 | rtc_tm_to_time(&tm_now, &time_now); | |
475 | if (time_set <= time_now) { | |
476 | dev_err(dev, "Date to set in the past\n"); | |
477 | return -EINVAL; | |
478 | } | |
479 | ||
480 | time_gap = time_set - time_now; | |
481 | ||
482 | if (time_gap > U32_MAX) { | |
483 | dev_err(dev, "Date too far in the future\n"); | |
484 | return -EINVAL; | |
485 | } | |
486 | ||
487 | sun6i_rtc_setaie(0, chip); | |
488 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
489 | usleep_range(100, 300); | |
490 | ||
491 | writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); | |
492 | chip->alarm = time_set; | |
493 | ||
494 | sun6i_rtc_setaie(wkalrm->enabled, chip); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, | |
500 | unsigned int mask, unsigned int ms_timeout) | |
501 | { | |
502 | const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); | |
503 | u32 reg; | |
504 | ||
505 | do { | |
506 | reg = readl(chip->base + offset); | |
507 | reg &= mask; | |
508 | ||
509 | if (!reg) | |
510 | return 0; | |
511 | ||
512 | } while (time_before(jiffies, timeout)); | |
513 | ||
514 | return -ETIMEDOUT; | |
515 | } | |
516 | ||
517 | static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) | |
518 | { | |
519 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
520 | u32 date = 0; | |
521 | u32 time = 0; | |
522 | int year; | |
523 | ||
524 | year = rtc_tm->tm_year + 1900; | |
525 | if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) { | |
526 | dev_err(dev, "rtc only supports year in range %d - %d\n", | |
527 | SUN6I_YEAR_MIN, SUN6I_YEAR_MAX); | |
528 | return -EINVAL; | |
529 | } | |
530 | ||
531 | rtc_tm->tm_year -= SUN6I_YEAR_OFF; | |
532 | rtc_tm->tm_mon += 1; | |
533 | ||
534 | date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | | |
535 | SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | | |
536 | SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); | |
537 | ||
538 | if (is_leap_year(year)) | |
539 | date |= SUN6I_LEAP_SET_VALUE(1); | |
540 | ||
541 | time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | | |
542 | SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | | |
543 | SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); | |
544 | ||
545 | /* Check whether registers are writable */ | |
546 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
547 | SUN6I_LOSC_CTRL_ACC_MASK, 50)) { | |
548 | dev_err(dev, "rtc is still busy.\n"); | |
549 | return -EBUSY; | |
550 | } | |
551 | ||
552 | writel(time, chip->base + SUN6I_RTC_HMS); | |
553 | ||
554 | /* | |
555 | * After writing the RTC HH-MM-SS register, the | |
556 | * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not | |
557 | * be cleared until the real writing operation is finished | |
558 | */ | |
559 | ||
560 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
561 | SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { | |
562 | dev_err(dev, "Failed to set rtc time.\n"); | |
563 | return -ETIMEDOUT; | |
564 | } | |
565 | ||
566 | writel(date, chip->base + SUN6I_RTC_YMD); | |
567 | ||
568 | /* | |
569 | * After writing the RTC YY-MM-DD register, the | |
570 | * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not | |
571 | * be cleared until the real writing operation is finished | |
572 | */ | |
573 | ||
574 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
575 | SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { | |
576 | dev_err(dev, "Failed to set rtc time.\n"); | |
577 | return -ETIMEDOUT; | |
578 | } | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
583 | static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
584 | { | |
585 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
586 | ||
587 | if (!enabled) | |
588 | sun6i_rtc_setaie(enabled, chip); | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
593 | static const struct rtc_class_ops sun6i_rtc_ops = { | |
594 | .read_time = sun6i_rtc_gettime, | |
595 | .set_time = sun6i_rtc_settime, | |
596 | .read_alarm = sun6i_rtc_getalarm, | |
597 | .set_alarm = sun6i_rtc_setalarm, | |
598 | .alarm_irq_enable = sun6i_rtc_alarm_irq_enable | |
599 | }; | |
600 | ||
601 | static int sun6i_rtc_probe(struct platform_device *pdev) | |
602 | { | |
3855c2c3 | 603 | struct sun6i_rtc_dev *chip = sun6i_rtc; |
9765d2d9 CYT |
604 | int ret; |
605 | ||
9765d2d9 | 606 | if (!chip) |
3855c2c3 | 607 | return -ENODEV; |
9765d2d9 CYT |
608 | |
609 | platform_set_drvdata(pdev, chip); | |
610 | chip->dev = &pdev->dev; | |
611 | ||
9765d2d9 CYT |
612 | chip->irq = platform_get_irq(pdev, 0); |
613 | if (chip->irq < 0) { | |
614 | dev_err(&pdev->dev, "No IRQ resource\n"); | |
615 | return chip->irq; | |
616 | } | |
617 | ||
618 | ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, | |
619 | 0, dev_name(&pdev->dev), chip); | |
620 | if (ret) { | |
621 | dev_err(&pdev->dev, "Could not request IRQ\n"); | |
622 | return ret; | |
623 | } | |
624 | ||
625 | /* clear the alarm counter value */ | |
626 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
627 | ||
628 | /* disable counter alarm */ | |
629 | writel(0, chip->base + SUN6I_ALRM_EN); | |
630 | ||
631 | /* disable counter alarm interrupt */ | |
632 | writel(0, chip->base + SUN6I_ALRM_IRQ_EN); | |
633 | ||
634 | /* disable week alarm */ | |
635 | writel(0, chip->base + SUN6I_ALRM1_EN); | |
636 | ||
637 | /* disable week alarm interrupt */ | |
638 | writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); | |
639 | ||
640 | /* clear counter alarm pending interrupts */ | |
641 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
642 | chip->base + SUN6I_ALRM_IRQ_STA); | |
643 | ||
644 | /* clear week alarm pending interrupts */ | |
645 | writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, | |
646 | chip->base + SUN6I_ALRM1_IRQ_STA); | |
647 | ||
648 | /* disable alarm wakeup */ | |
649 | writel(0, chip->base + SUN6I_ALARM_CONFIG); | |
650 | ||
3855c2c3 | 651 | clk_prepare_enable(chip->losc); |
fb61bb82 | 652 | |
5dff3a31 MR |
653 | chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i", |
654 | &sun6i_rtc_ops, THIS_MODULE); | |
9765d2d9 CYT |
655 | if (IS_ERR(chip->rtc)) { |
656 | dev_err(&pdev->dev, "unable to register device\n"); | |
657 | return PTR_ERR(chip->rtc); | |
658 | } | |
659 | ||
660 | dev_info(&pdev->dev, "RTC enabled\n"); | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
403a3c3d CYT |
665 | /* |
666 | * As far as RTC functionality goes, all models are the same. The | |
667 | * datasheets claim that different models have different number of | |
668 | * registers available for non-volatile storage, but experiments show | |
669 | * that all SoCs have 16 registers available for this purpose. | |
670 | */ | |
9765d2d9 CYT |
671 | static const struct of_device_id sun6i_rtc_dt_ids[] = { |
672 | { .compatible = "allwinner,sun6i-a31-rtc" }, | |
7cd1acae CYT |
673 | { .compatible = "allwinner,sun8i-a23-rtc" }, |
674 | { .compatible = "allwinner,sun8i-h3-rtc" }, | |
675 | { .compatible = "allwinner,sun8i-v3-rtc" }, | |
676 | { .compatible = "allwinner,sun50i-h5-rtc" }, | |
9765d2d9 CYT |
677 | { /* sentinel */ }, |
678 | }; | |
679 | MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); | |
680 | ||
681 | static struct platform_driver sun6i_rtc_driver = { | |
682 | .probe = sun6i_rtc_probe, | |
9765d2d9 CYT |
683 | .driver = { |
684 | .name = "sun6i-rtc", | |
685 | .of_match_table = sun6i_rtc_dt_ids, | |
686 | }, | |
687 | }; | |
37539414 | 688 | builtin_platform_driver(sun6i_rtc_driver); |