Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
9765d2d9 CYT |
2 | /* |
3 | * An RTC driver for Allwinner A31/A23 | |
4 | * | |
5 | * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> | |
6 | * | |
7 | * based on rtc-sunxi.c | |
8 | * | |
9 | * An RTC driver for Allwinner A10/A20 | |
10 | * | |
11 | * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> | |
9765d2d9 CYT |
12 | */ |
13 | ||
3855c2c3 MR |
14 | #include <linux/clk.h> |
15 | #include <linux/clk-provider.h> | |
d91612d7 | 16 | #include <linux/clk/sunxi-ng.h> |
9765d2d9 CYT |
17 | #include <linux/delay.h> |
18 | #include <linux/err.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_device.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/rtc.h> | |
3855c2c3 | 30 | #include <linux/slab.h> |
9765d2d9 CYT |
31 | #include <linux/types.h> |
32 | ||
33 | /* Control register */ | |
34 | #define SUN6I_LOSC_CTRL 0x0000 | |
fb61bb82 | 35 | #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) |
b60ff2cf | 36 | #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) |
9765d2d9 CYT |
37 | #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) |
38 | #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) | |
39 | #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) | |
b60ff2cf | 40 | #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) |
fb61bb82 | 41 | #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) |
9765d2d9 CYT |
42 | #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) |
43 | ||
3855c2c3 MR |
44 | #define SUN6I_LOSC_CLK_PRESCAL 0x0008 |
45 | ||
9765d2d9 CYT |
46 | /* RTC */ |
47 | #define SUN6I_RTC_YMD 0x0010 | |
48 | #define SUN6I_RTC_HMS 0x0014 | |
49 | ||
50 | /* Alarm 0 (counter) */ | |
51 | #define SUN6I_ALRM_COUNTER 0x0020 | |
7878fec4 AP |
52 | /* This holds the remaining alarm seconds on older SoCs (current value) */ |
53 | #define SUN6I_ALRM_COUNTER_HMS 0x0024 | |
9765d2d9 CYT |
54 | #define SUN6I_ALRM_EN 0x0028 |
55 | #define SUN6I_ALRM_EN_CNT_EN BIT(0) | |
56 | #define SUN6I_ALRM_IRQ_EN 0x002c | |
57 | #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) | |
58 | #define SUN6I_ALRM_IRQ_STA 0x0030 | |
59 | #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) | |
60 | ||
61 | /* Alarm 1 (wall clock) */ | |
62 | #define SUN6I_ALRM1_EN 0x0044 | |
63 | #define SUN6I_ALRM1_IRQ_EN 0x0048 | |
64 | #define SUN6I_ALRM1_IRQ_STA 0x004c | |
65 | #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) | |
66 | ||
67 | /* Alarm config */ | |
68 | #define SUN6I_ALARM_CONFIG 0x0050 | |
69 | #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) | |
70 | ||
17ecd246 | 71 | #define SUN6I_LOSC_OUT_GATING 0x0060 |
09018d4b | 72 | #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 |
17ecd246 | 73 | |
581d6d8f SH |
74 | /* General-purpose data */ |
75 | #define SUN6I_GP_DATA 0x0100 | |
76 | #define SUN6I_GP_DATA_SIZE 0x20 | |
77 | ||
9765d2d9 CYT |
78 | /* |
79 | * Get date values | |
80 | */ | |
81 | #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) | |
82 | #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) | |
83 | #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) | |
84 | #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) | |
85 | ||
86 | /* | |
87 | * Get time values | |
88 | */ | |
89 | #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) | |
90 | #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) | |
91 | #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) | |
92 | ||
93 | /* | |
94 | * Set date values | |
95 | */ | |
96 | #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) | |
97 | #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) | |
98 | #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) | |
99 | #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) | |
100 | ||
101 | /* | |
102 | * Set time values | |
103 | */ | |
104 | #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) | |
105 | #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) | |
106 | #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) | |
107 | ||
108 | /* | |
109 | * The year parameter passed to the driver is usually an offset relative to | |
110 | * the year 1900. This macro is used to convert this offset to another one | |
111 | * relative to the minimum year allowed by the hardware. | |
112 | * | |
113 | * The year range is 1970 - 2033. This range is selected to match Allwinner's | |
114 | * driver, even though it is somewhat limited. | |
115 | */ | |
116 | #define SUN6I_YEAR_MIN 1970 | |
9765d2d9 CYT |
117 | #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) |
118 | ||
648c151a AP |
119 | #define SECS_PER_DAY (24 * 3600ULL) |
120 | ||
403a3c3d CYT |
121 | /* |
122 | * There are other differences between models, including: | |
123 | * | |
124 | * - number of GPIO pins that can be configured to hold a certain level | |
125 | * - crypto-key related registers (H5, H6) | |
126 | * - boot process related (super standby, secondary processor entry address) | |
127 | * registers (R40, H6) | |
128 | * - SYS power domain controls (R40) | |
129 | * - DCXO controls (H6) | |
130 | * - RC oscillator calibration (H6) | |
131 | * | |
132 | * These functions are not covered by this driver. | |
133 | */ | |
134 | struct sun6i_rtc_clk_data { | |
135 | unsigned long rc_osc_rate; | |
136 | unsigned int fixed_prescaler : 16; | |
137 | unsigned int has_prescaler : 1; | |
138 | unsigned int has_out_clk : 1; | |
b60ff2cf OJ |
139 | unsigned int has_losc_en : 1; |
140 | unsigned int has_auto_swt : 1; | |
403a3c3d CYT |
141 | }; |
142 | ||
648c151a AP |
143 | #define RTC_LINEAR_DAY BIT(0) |
144 | ||
9765d2d9 CYT |
145 | struct sun6i_rtc_dev { |
146 | struct rtc_device *rtc; | |
403a3c3d | 147 | const struct sun6i_rtc_clk_data *data; |
9765d2d9 CYT |
148 | void __iomem *base; |
149 | int irq; | |
9f6cd82e | 150 | time64_t alarm; |
648c151a | 151 | unsigned long flags; |
a9422a19 | 152 | |
3855c2c3 MR |
153 | struct clk_hw hw; |
154 | struct clk_hw *int_osc; | |
155 | struct clk *losc; | |
17ecd246 | 156 | struct clk *ext_losc; |
3855c2c3 | 157 | |
a9422a19 | 158 | spinlock_t lock; |
9765d2d9 CYT |
159 | }; |
160 | ||
3855c2c3 MR |
161 | static struct sun6i_rtc_dev *sun6i_rtc; |
162 | ||
163 | static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, | |
164 | unsigned long parent_rate) | |
165 | { | |
166 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
403a3c3d | 167 | u32 val = 0; |
3855c2c3 MR |
168 | |
169 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
170 | if (val & SUN6I_LOSC_CTRL_EXT_OSC) | |
171 | return parent_rate; | |
172 | ||
403a3c3d CYT |
173 | if (rtc->data->fixed_prescaler) |
174 | parent_rate /= rtc->data->fixed_prescaler; | |
175 | ||
176 | if (rtc->data->has_prescaler) { | |
177 | val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); | |
178 | val &= GENMASK(4, 0); | |
179 | } | |
3855c2c3 MR |
180 | |
181 | return parent_rate / (val + 1); | |
182 | } | |
183 | ||
184 | static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) | |
185 | { | |
186 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
187 | ||
188 | return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; | |
189 | } | |
190 | ||
191 | static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) | |
192 | { | |
193 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
194 | unsigned long flags; | |
195 | u32 val; | |
196 | ||
197 | if (index > 1) | |
198 | return -EINVAL; | |
199 | ||
200 | spin_lock_irqsave(&rtc->lock, flags); | |
201 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
202 | val &= ~SUN6I_LOSC_CTRL_EXT_OSC; | |
203 | val |= SUN6I_LOSC_CTRL_KEY; | |
204 | val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; | |
b60ff2cf OJ |
205 | if (rtc->data->has_losc_en) { |
206 | val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; | |
207 | val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; | |
208 | } | |
3855c2c3 MR |
209 | writel(val, rtc->base + SUN6I_LOSC_CTRL); |
210 | spin_unlock_irqrestore(&rtc->lock, flags); | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | static const struct clk_ops sun6i_rtc_osc_ops = { | |
216 | .recalc_rate = sun6i_rtc_osc_recalc_rate, | |
217 | ||
218 | .get_parent = sun6i_rtc_osc_get_parent, | |
219 | .set_parent = sun6i_rtc_osc_set_parent, | |
220 | }; | |
221 | ||
403a3c3d CYT |
222 | static void __init sun6i_rtc_clk_init(struct device_node *node, |
223 | const struct sun6i_rtc_clk_data *data) | |
3855c2c3 MR |
224 | { |
225 | struct clk_hw_onecell_data *clk_data; | |
226 | struct sun6i_rtc_dev *rtc; | |
227 | struct clk_init_data init = { | |
228 | .ops = &sun6i_rtc_osc_ops, | |
459b6ea0 | 229 | .name = "losc", |
3855c2c3 | 230 | }; |
c56afc18 | 231 | const char *iosc_name = "rtc-int-osc"; |
17ecd246 | 232 | const char *clkout_name = "osc32k-out"; |
3855c2c3 | 233 | const char *parents[2]; |
b60ff2cf | 234 | u32 reg; |
3855c2c3 MR |
235 | |
236 | rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); | |
237 | if (!rtc) | |
238 | return; | |
3855c2c3 | 239 | |
403a3c3d | 240 | rtc->data = data; |
c56afc18 | 241 | clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); |
e9982024 CIK |
242 | if (!clk_data) { |
243 | kfree(rtc); | |
3855c2c3 | 244 | return; |
e9982024 | 245 | } |
319ff835 | 246 | |
3855c2c3 MR |
247 | spin_lock_init(&rtc->lock); |
248 | ||
249 | rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); | |
aaa65a9c | 250 | if (IS_ERR(rtc->base)) { |
3855c2c3 | 251 | pr_crit("Can't map RTC registers"); |
1a37c348 | 252 | goto err; |
3855c2c3 MR |
253 | } |
254 | ||
b60ff2cf OJ |
255 | reg = SUN6I_LOSC_CTRL_KEY; |
256 | if (rtc->data->has_auto_swt) { | |
257 | /* Bypass auto-switch to int osc, on ext losc failure */ | |
258 | reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; | |
259 | writel(reg, rtc->base + SUN6I_LOSC_CTRL); | |
260 | } | |
261 | ||
ec98a875 JS |
262 | /* Switch to the external, more precise, oscillator, if present */ |
263 | if (of_get_property(node, "clocks", NULL)) { | |
264 | reg |= SUN6I_LOSC_CTRL_EXT_OSC; | |
265 | if (rtc->data->has_losc_en) | |
266 | reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; | |
267 | } | |
b60ff2cf | 268 | writel(reg, rtc->base + SUN6I_LOSC_CTRL); |
3855c2c3 | 269 | |
15829cf4 CYT |
270 | /* Yes, I know, this is ugly. */ |
271 | sun6i_rtc = rtc; | |
272 | ||
344f4030 SH |
273 | of_property_read_string_index(node, "clock-output-names", 2, |
274 | &iosc_name); | |
c56afc18 | 275 | |
3855c2c3 | 276 | rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, |
c56afc18 | 277 | iosc_name, |
3855c2c3 | 278 | NULL, 0, |
403a3c3d | 279 | rtc->data->rc_osc_rate, |
3855c2c3 MR |
280 | 300000000); |
281 | if (IS_ERR(rtc->int_osc)) { | |
282 | pr_crit("Couldn't register the internal oscillator\n"); | |
28d21191 | 283 | goto err; |
3855c2c3 MR |
284 | } |
285 | ||
286 | parents[0] = clk_hw_get_name(rtc->int_osc); | |
ec98a875 | 287 | /* If there is no external oscillator, this will be NULL and ... */ |
3855c2c3 MR |
288 | parents[1] = of_clk_get_parent_name(node, 0); |
289 | ||
290 | rtc->hw.init = &init; | |
291 | ||
292 | init.parent_names = parents; | |
ec98a875 | 293 | /* ... number of clock parents will be 1. */ |
3855c2c3 | 294 | init.num_parents = of_clk_get_parent_count(node) + 1; |
17ecd246 MR |
295 | of_property_read_string_index(node, "clock-output-names", 0, |
296 | &init.name); | |
3855c2c3 MR |
297 | |
298 | rtc->losc = clk_register(NULL, &rtc->hw); | |
299 | if (IS_ERR(rtc->losc)) { | |
300 | pr_crit("Couldn't register the LOSC clock\n"); | |
28d21191 | 301 | goto err_register; |
3855c2c3 MR |
302 | } |
303 | ||
17ecd246 MR |
304 | of_property_read_string_index(node, "clock-output-names", 1, |
305 | &clkout_name); | |
21ef77de | 306 | rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, |
17ecd246 | 307 | 0, rtc->base + SUN6I_LOSC_OUT_GATING, |
09018d4b | 308 | SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, |
17ecd246 MR |
309 | &rtc->lock); |
310 | if (IS_ERR(rtc->ext_losc)) { | |
311 | pr_crit("Couldn't register the LOSC external gate\n"); | |
28d21191 | 312 | goto err_register; |
17ecd246 MR |
313 | } |
314 | ||
344f4030 | 315 | clk_data->num = 3; |
3855c2c3 | 316 | clk_data->hws[0] = &rtc->hw; |
17ecd246 | 317 | clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); |
344f4030 | 318 | clk_data->hws[2] = rtc->int_osc; |
3855c2c3 | 319 | of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); |
1a37c348 CIK |
320 | return; |
321 | ||
28d21191 DL |
322 | err_register: |
323 | clk_hw_unregister_fixed_rate(rtc->int_osc); | |
1a37c348 CIK |
324 | err: |
325 | kfree(clk_data); | |
3855c2c3 | 326 | } |
403a3c3d CYT |
327 | |
328 | static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { | |
329 | .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ | |
330 | .has_prescaler = 1, | |
331 | }; | |
332 | ||
333 | static void __init sun6i_a31_rtc_clk_init(struct device_node *node) | |
334 | { | |
335 | sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); | |
336 | } | |
337 | CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", | |
338 | sun6i_a31_rtc_clk_init); | |
3855c2c3 | 339 | |
7cd1acae CYT |
340 | static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { |
341 | .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ | |
342 | .has_prescaler = 1, | |
343 | .has_out_clk = 1, | |
344 | }; | |
345 | ||
346 | static void __init sun8i_a23_rtc_clk_init(struct device_node *node) | |
347 | { | |
348 | sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); | |
349 | } | |
350 | CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", | |
351 | sun8i_a23_rtc_clk_init); | |
352 | ||
353 | static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { | |
354 | .rc_osc_rate = 16000000, | |
355 | .fixed_prescaler = 32, | |
356 | .has_prescaler = 1, | |
357 | .has_out_clk = 1, | |
358 | }; | |
359 | ||
360 | static void __init sun8i_h3_rtc_clk_init(struct device_node *node) | |
361 | { | |
362 | sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); | |
363 | } | |
364 | CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", | |
365 | sun8i_h3_rtc_clk_init); | |
366 | /* As far as we are concerned, clocks for H5 are the same as H3 */ | |
367 | CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", | |
368 | sun8i_h3_rtc_clk_init); | |
369 | ||
60d9f050 JS |
370 | static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { |
371 | .rc_osc_rate = 16000000, | |
372 | .fixed_prescaler = 32, | |
373 | .has_prescaler = 1, | |
374 | .has_out_clk = 1, | |
60d9f050 JS |
375 | .has_losc_en = 1, |
376 | .has_auto_swt = 1, | |
377 | }; | |
378 | ||
379 | static void __init sun50i_h6_rtc_clk_init(struct device_node *node) | |
380 | { | |
381 | sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); | |
382 | } | |
383 | CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", | |
384 | sun50i_h6_rtc_clk_init); | |
385 | ||
111bf02b CYT |
386 | /* |
387 | * The R40 user manual is self-conflicting on whether the prescaler is | |
388 | * fixed or configurable. The clock diagram shows it as fixed, but there | |
389 | * is also a configurable divider in the RTC block. | |
390 | */ | |
391 | static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { | |
392 | .rc_osc_rate = 16000000, | |
393 | .fixed_prescaler = 512, | |
394 | }; | |
395 | static void __init sun8i_r40_rtc_clk_init(struct device_node *node) | |
396 | { | |
397 | sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); | |
398 | } | |
399 | CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", | |
400 | sun8i_r40_rtc_clk_init); | |
401 | ||
7cd1acae CYT |
402 | static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { |
403 | .rc_osc_rate = 32000, | |
404 | .has_out_clk = 1, | |
405 | }; | |
406 | ||
407 | static void __init sun8i_v3_rtc_clk_init(struct device_node *node) | |
408 | { | |
409 | sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); | |
410 | } | |
411 | CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", | |
412 | sun8i_v3_rtc_clk_init); | |
413 | ||
9765d2d9 CYT |
414 | static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) |
415 | { | |
416 | struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; | |
a9422a19 | 417 | irqreturn_t ret = IRQ_NONE; |
9765d2d9 CYT |
418 | u32 val; |
419 | ||
a9422a19 | 420 | spin_lock(&chip->lock); |
9765d2d9 CYT |
421 | val = readl(chip->base + SUN6I_ALRM_IRQ_STA); |
422 | ||
423 | if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { | |
424 | val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; | |
425 | writel(val, chip->base + SUN6I_ALRM_IRQ_STA); | |
426 | ||
427 | rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); | |
428 | ||
a9422a19 | 429 | ret = IRQ_HANDLED; |
9765d2d9 | 430 | } |
a9422a19 | 431 | spin_unlock(&chip->lock); |
9765d2d9 | 432 | |
a9422a19 | 433 | return ret; |
9765d2d9 CYT |
434 | } |
435 | ||
436 | static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) | |
437 | { | |
438 | u32 alrm_val = 0; | |
439 | u32 alrm_irq_val = 0; | |
440 | u32 alrm_wake_val = 0; | |
a9422a19 | 441 | unsigned long flags; |
9765d2d9 CYT |
442 | |
443 | if (to) { | |
444 | alrm_val = SUN6I_ALRM_EN_CNT_EN; | |
445 | alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; | |
446 | alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; | |
447 | } else { | |
448 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
449 | chip->base + SUN6I_ALRM_IRQ_STA); | |
450 | } | |
451 | ||
a9422a19 | 452 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
453 | writel(alrm_val, chip->base + SUN6I_ALRM_EN); |
454 | writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); | |
455 | writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); | |
a9422a19 | 456 | spin_unlock_irqrestore(&chip->lock, flags); |
9765d2d9 CYT |
457 | } |
458 | ||
459 | static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
460 | { | |
461 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
462 | u32 date, time; | |
463 | ||
464 | /* | |
465 | * read again in case it changes | |
466 | */ | |
467 | do { | |
468 | date = readl(chip->base + SUN6I_RTC_YMD); | |
469 | time = readl(chip->base + SUN6I_RTC_HMS); | |
470 | } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || | |
471 | (time != readl(chip->base + SUN6I_RTC_HMS))); | |
472 | ||
648c151a AP |
473 | if (chip->flags & RTC_LINEAR_DAY) { |
474 | /* | |
475 | * Newer chips store a linear day number, the manual | |
476 | * does not mandate any epoch base. The BSP driver uses | |
477 | * the UNIX epoch, let's just copy that, as it's the | |
478 | * easiest anyway. | |
479 | */ | |
480 | rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); | |
481 | } else { | |
482 | rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); | |
483 | rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; | |
484 | rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); | |
485 | ||
486 | /* | |
487 | * switch from (data_year->min)-relative offset to | |
488 | * a (1900)-relative one | |
489 | */ | |
490 | rtc_tm->tm_year += SUN6I_YEAR_OFF; | |
491 | } | |
492 | ||
9765d2d9 CYT |
493 | rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); |
494 | rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); | |
495 | rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); | |
496 | ||
22652ba7 | 497 | return 0; |
9765d2d9 CYT |
498 | } |
499 | ||
500 | static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
501 | { | |
502 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
a9422a19 | 503 | unsigned long flags; |
9765d2d9 CYT |
504 | u32 alrm_st; |
505 | u32 alrm_en; | |
506 | ||
a9422a19 | 507 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
508 | alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); |
509 | alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); | |
a9422a19 MR |
510 | spin_unlock_irqrestore(&chip->lock, flags); |
511 | ||
9765d2d9 CYT |
512 | wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); |
513 | wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); | |
99b7ac9c | 514 | rtc_time64_to_tm(chip->alarm, &wkalrm->time); |
9765d2d9 CYT |
515 | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
520 | { | |
521 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
522 | struct rtc_time *alrm_tm = &wkalrm->time; | |
523 | struct rtc_time tm_now; | |
7878fec4 AP |
524 | time64_t time_set; |
525 | u32 counter_val, counter_val_hms; | |
9f6cd82e | 526 | int ret; |
9765d2d9 | 527 | |
99b7ac9c | 528 | time_set = rtc_tm_to_time64(alrm_tm); |
9765d2d9 | 529 | |
7878fec4 AP |
530 | if (chip->flags & RTC_LINEAR_DAY) { |
531 | /* | |
532 | * The alarm registers hold the actual alarm time, encoded | |
533 | * in the same way (linear day + HMS) as the current time. | |
534 | */ | |
535 | counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | | |
536 | SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | | |
537 | SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); | |
538 | /* The division will cut off the H:M:S part of alrm_tm. */ | |
539 | counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); | |
540 | } else { | |
541 | /* The alarm register holds the number of seconds left. */ | |
542 | time64_t time_now; | |
543 | ||
544 | ret = sun6i_rtc_gettime(dev, &tm_now); | |
545 | if (ret < 0) { | |
546 | dev_err(dev, "Error in getting time\n"); | |
547 | return -EINVAL; | |
548 | } | |
549 | ||
550 | time_now = rtc_tm_to_time64(&tm_now); | |
551 | if (time_set <= time_now) { | |
552 | dev_err(dev, "Date to set in the past\n"); | |
553 | return -EINVAL; | |
554 | } | |
555 | if ((time_set - time_now) > U32_MAX) { | |
556 | dev_err(dev, "Date too far in the future\n"); | |
557 | return -EINVAL; | |
558 | } | |
559 | ||
560 | counter_val = time_set - time_now; | |
9765d2d9 CYT |
561 | } |
562 | ||
563 | sun6i_rtc_setaie(0, chip); | |
564 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
7878fec4 AP |
565 | if (chip->flags & RTC_LINEAR_DAY) |
566 | writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); | |
9765d2d9 CYT |
567 | usleep_range(100, 300); |
568 | ||
7878fec4 AP |
569 | writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); |
570 | if (chip->flags & RTC_LINEAR_DAY) | |
571 | writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); | |
9765d2d9 CYT |
572 | chip->alarm = time_set; |
573 | ||
574 | sun6i_rtc_setaie(wkalrm->enabled, chip); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, | |
580 | unsigned int mask, unsigned int ms_timeout) | |
581 | { | |
582 | const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); | |
583 | u32 reg; | |
584 | ||
585 | do { | |
586 | reg = readl(chip->base + offset); | |
587 | reg &= mask; | |
588 | ||
589 | if (!reg) | |
590 | return 0; | |
591 | ||
592 | } while (time_before(jiffies, timeout)); | |
593 | ||
594 | return -ETIMEDOUT; | |
595 | } | |
596 | ||
597 | static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) | |
598 | { | |
599 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
600 | u32 date = 0; | |
601 | u32 time = 0; | |
9765d2d9 | 602 | |
9765d2d9 CYT |
603 | time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | |
604 | SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | | |
605 | SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); | |
606 | ||
648c151a AP |
607 | if (chip->flags & RTC_LINEAR_DAY) { |
608 | /* The division will cut off the H:M:S part of rtc_tm. */ | |
609 | date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); | |
610 | } else { | |
611 | rtc_tm->tm_year -= SUN6I_YEAR_OFF; | |
612 | rtc_tm->tm_mon += 1; | |
613 | ||
614 | date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | | |
615 | SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | | |
616 | SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); | |
617 | ||
618 | if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) | |
619 | date |= SUN6I_LEAP_SET_VALUE(1); | |
620 | } | |
621 | ||
9765d2d9 CYT |
622 | /* Check whether registers are writable */ |
623 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
624 | SUN6I_LOSC_CTRL_ACC_MASK, 50)) { | |
625 | dev_err(dev, "rtc is still busy.\n"); | |
626 | return -EBUSY; | |
627 | } | |
628 | ||
629 | writel(time, chip->base + SUN6I_RTC_HMS); | |
630 | ||
631 | /* | |
632 | * After writing the RTC HH-MM-SS register, the | |
633 | * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not | |
634 | * be cleared until the real writing operation is finished | |
635 | */ | |
636 | ||
637 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
638 | SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { | |
639 | dev_err(dev, "Failed to set rtc time.\n"); | |
640 | return -ETIMEDOUT; | |
641 | } | |
642 | ||
643 | writel(date, chip->base + SUN6I_RTC_YMD); | |
644 | ||
645 | /* | |
646 | * After writing the RTC YY-MM-DD register, the | |
647 | * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not | |
648 | * be cleared until the real writing operation is finished | |
649 | */ | |
650 | ||
651 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
652 | SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { | |
653 | dev_err(dev, "Failed to set rtc time.\n"); | |
654 | return -ETIMEDOUT; | |
655 | } | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
661 | { | |
662 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
663 | ||
664 | if (!enabled) | |
665 | sun6i_rtc_setaie(enabled, chip); | |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
670 | static const struct rtc_class_ops sun6i_rtc_ops = { | |
671 | .read_time = sun6i_rtc_gettime, | |
672 | .set_time = sun6i_rtc_settime, | |
673 | .read_alarm = sun6i_rtc_getalarm, | |
674 | .set_alarm = sun6i_rtc_setalarm, | |
675 | .alarm_irq_enable = sun6i_rtc_alarm_irq_enable | |
676 | }; | |
677 | ||
581d6d8f SH |
678 | static int sun6i_rtc_nvmem_read(void *priv, unsigned int offset, void *_val, size_t bytes) |
679 | { | |
680 | struct sun6i_rtc_dev *chip = priv; | |
681 | u32 *val = _val; | |
682 | int i; | |
683 | ||
684 | for (i = 0; i < bytes / 4; ++i) | |
685 | val[i] = readl(chip->base + SUN6I_GP_DATA + offset + 4 * i); | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
690 | static int sun6i_rtc_nvmem_write(void *priv, unsigned int offset, void *_val, size_t bytes) | |
691 | { | |
692 | struct sun6i_rtc_dev *chip = priv; | |
693 | u32 *val = _val; | |
694 | int i; | |
695 | ||
696 | for (i = 0; i < bytes / 4; ++i) | |
697 | writel(val[i], chip->base + SUN6I_GP_DATA + offset + 4 * i); | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
702 | static struct nvmem_config sun6i_rtc_nvmem_cfg = { | |
703 | .type = NVMEM_TYPE_BATTERY_BACKED, | |
704 | .reg_read = sun6i_rtc_nvmem_read, | |
705 | .reg_write = sun6i_rtc_nvmem_write, | |
706 | .size = SUN6I_GP_DATA_SIZE, | |
707 | .word_size = 4, | |
708 | .stride = 4, | |
709 | }; | |
710 | ||
d76a81d0 AG |
711 | #ifdef CONFIG_PM_SLEEP |
712 | /* Enable IRQ wake on suspend, to wake up from RTC. */ | |
713 | static int sun6i_rtc_suspend(struct device *dev) | |
714 | { | |
715 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
716 | ||
717 | if (device_may_wakeup(dev)) | |
718 | enable_irq_wake(chip->irq); | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | /* Disable IRQ wake on resume. */ | |
724 | static int sun6i_rtc_resume(struct device *dev) | |
725 | { | |
726 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
727 | ||
728 | if (device_may_wakeup(dev)) | |
729 | disable_irq_wake(chip->irq); | |
730 | ||
731 | return 0; | |
732 | } | |
733 | #endif | |
734 | ||
735 | static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, | |
736 | sun6i_rtc_suspend, sun6i_rtc_resume); | |
737 | ||
2ca03e29 SH |
738 | static void sun6i_rtc_bus_clk_cleanup(void *data) |
739 | { | |
740 | struct clk *bus_clk = data; | |
741 | ||
742 | clk_disable_unprepare(bus_clk); | |
743 | } | |
744 | ||
9765d2d9 CYT |
745 | static int sun6i_rtc_probe(struct platform_device *pdev) |
746 | { | |
3855c2c3 | 747 | struct sun6i_rtc_dev *chip = sun6i_rtc; |
2ca03e29 SH |
748 | struct device *dev = &pdev->dev; |
749 | struct clk *bus_clk; | |
9765d2d9 CYT |
750 | int ret; |
751 | ||
2ca03e29 SH |
752 | bus_clk = devm_clk_get_optional(dev, "bus"); |
753 | if (IS_ERR(bus_clk)) | |
754 | return PTR_ERR(bus_clk); | |
755 | ||
756 | if (bus_clk) { | |
757 | ret = clk_prepare_enable(bus_clk); | |
758 | if (ret) | |
759 | return ret; | |
760 | ||
761 | ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup, | |
762 | bus_clk); | |
763 | if (ret) | |
764 | return ret; | |
765 | } | |
766 | ||
814691c7 SH |
767 | if (!chip) { |
768 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); | |
769 | if (!chip) | |
770 | return -ENOMEM; | |
771 | ||
772 | spin_lock_init(&chip->lock); | |
773 | ||
774 | chip->base = devm_platform_ioremap_resource(pdev, 0); | |
775 | if (IS_ERR(chip->base)) | |
776 | return PTR_ERR(chip->base); | |
d91612d7 SH |
777 | |
778 | if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) { | |
779 | ret = sun6i_rtc_ccu_probe(dev, chip->base); | |
780 | if (ret) | |
781 | return ret; | |
782 | } | |
814691c7 | 783 | } |
9765d2d9 CYT |
784 | |
785 | platform_set_drvdata(pdev, chip); | |
9765d2d9 | 786 | |
648c151a AP |
787 | chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); |
788 | ||
9765d2d9 | 789 | chip->irq = platform_get_irq(pdev, 0); |
faac9102 | 790 | if (chip->irq < 0) |
9765d2d9 | 791 | return chip->irq; |
9765d2d9 CYT |
792 | |
793 | ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, | |
794 | 0, dev_name(&pdev->dev), chip); | |
795 | if (ret) { | |
796 | dev_err(&pdev->dev, "Could not request IRQ\n"); | |
797 | return ret; | |
798 | } | |
799 | ||
800 | /* clear the alarm counter value */ | |
801 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
802 | ||
803 | /* disable counter alarm */ | |
804 | writel(0, chip->base + SUN6I_ALRM_EN); | |
805 | ||
806 | /* disable counter alarm interrupt */ | |
807 | writel(0, chip->base + SUN6I_ALRM_IRQ_EN); | |
808 | ||
809 | /* disable week alarm */ | |
810 | writel(0, chip->base + SUN6I_ALRM1_EN); | |
811 | ||
812 | /* disable week alarm interrupt */ | |
813 | writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); | |
814 | ||
815 | /* clear counter alarm pending interrupts */ | |
816 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
817 | chip->base + SUN6I_ALRM_IRQ_STA); | |
818 | ||
819 | /* clear week alarm pending interrupts */ | |
820 | writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, | |
821 | chip->base + SUN6I_ALRM1_IRQ_STA); | |
822 | ||
823 | /* disable alarm wakeup */ | |
824 | writel(0, chip->base + SUN6I_ALARM_CONFIG); | |
825 | ||
3855c2c3 | 826 | clk_prepare_enable(chip->losc); |
fb61bb82 | 827 | |
d76a81d0 AG |
828 | device_init_wakeup(&pdev->dev, 1); |
829 | ||
8ae79be7 AB |
830 | chip->rtc = devm_rtc_allocate_device(&pdev->dev); |
831 | if (IS_ERR(chip->rtc)) | |
9765d2d9 | 832 | return PTR_ERR(chip->rtc); |
8ae79be7 AB |
833 | |
834 | chip->rtc->ops = &sun6i_rtc_ops; | |
648c151a AP |
835 | if (chip->flags & RTC_LINEAR_DAY) |
836 | chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; | |
837 | else | |
838 | chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ | |
8ae79be7 | 839 | |
fdcfd854 | 840 | ret = devm_rtc_register_device(chip->rtc); |
8ae79be7 AB |
841 | if (ret) |
842 | return ret; | |
9765d2d9 | 843 | |
581d6d8f SH |
844 | sun6i_rtc_nvmem_cfg.priv = chip; |
845 | ret = devm_rtc_nvmem_register(chip->rtc, &sun6i_rtc_nvmem_cfg); | |
846 | if (ret) | |
847 | return ret; | |
848 | ||
9765d2d9 CYT |
849 | dev_info(&pdev->dev, "RTC enabled\n"); |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
403a3c3d CYT |
854 | /* |
855 | * As far as RTC functionality goes, all models are the same. The | |
856 | * datasheets claim that different models have different number of | |
857 | * registers available for non-volatile storage, but experiments show | |
858 | * that all SoCs have 16 registers available for this purpose. | |
859 | */ | |
9765d2d9 CYT |
860 | static const struct of_device_id sun6i_rtc_dt_ids[] = { |
861 | { .compatible = "allwinner,sun6i-a31-rtc" }, | |
7cd1acae CYT |
862 | { .compatible = "allwinner,sun8i-a23-rtc" }, |
863 | { .compatible = "allwinner,sun8i-h3-rtc" }, | |
d6624cc7 | 864 | { .compatible = "allwinner,sun8i-r40-rtc" }, |
7cd1acae CYT |
865 | { .compatible = "allwinner,sun8i-v3-rtc" }, |
866 | { .compatible = "allwinner,sun50i-h5-rtc" }, | |
b60ff2cf | 867 | { .compatible = "allwinner,sun50i-h6-rtc" }, |
8a937203 AP |
868 | { .compatible = "allwinner,sun50i-h616-rtc", |
869 | .data = (void *)RTC_LINEAR_DAY }, | |
b9d98238 IZ |
870 | { .compatible = "allwinner,sun50i-r329-rtc", |
871 | .data = (void *)RTC_LINEAR_DAY }, | |
9765d2d9 CYT |
872 | { /* sentinel */ }, |
873 | }; | |
874 | MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); | |
875 | ||
876 | static struct platform_driver sun6i_rtc_driver = { | |
877 | .probe = sun6i_rtc_probe, | |
9765d2d9 CYT |
878 | .driver = { |
879 | .name = "sun6i-rtc", | |
880 | .of_match_table = sun6i_rtc_dt_ids, | |
d76a81d0 | 881 | .pm = &sun6i_rtc_pm_ops, |
9765d2d9 CYT |
882 | }, |
883 | }; | |
37539414 | 884 | builtin_platform_driver(sun6i_rtc_driver); |