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9765d2d9 CYT |
1 | /* |
2 | * An RTC driver for Allwinner A31/A23 | |
3 | * | |
4 | * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> | |
5 | * | |
6 | * based on rtc-sunxi.c | |
7 | * | |
8 | * An RTC driver for Allwinner A10/A20 | |
9 | * | |
10 | * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
18 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
19 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
20 | * more details. | |
21 | */ | |
22 | ||
3855c2c3 MR |
23 | #include <linux/clk.h> |
24 | #include <linux/clk-provider.h> | |
9765d2d9 CYT |
25 | #include <linux/delay.h> |
26 | #include <linux/err.h> | |
27 | #include <linux/fs.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/of.h> | |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_device.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/rtc.h> | |
3855c2c3 | 38 | #include <linux/slab.h> |
9765d2d9 CYT |
39 | #include <linux/types.h> |
40 | ||
41 | /* Control register */ | |
42 | #define SUN6I_LOSC_CTRL 0x0000 | |
fb61bb82 | 43 | #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) |
9765d2d9 CYT |
44 | #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) |
45 | #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) | |
46 | #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) | |
fb61bb82 | 47 | #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) |
9765d2d9 CYT |
48 | #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) |
49 | ||
3855c2c3 MR |
50 | #define SUN6I_LOSC_CLK_PRESCAL 0x0008 |
51 | ||
9765d2d9 CYT |
52 | /* RTC */ |
53 | #define SUN6I_RTC_YMD 0x0010 | |
54 | #define SUN6I_RTC_HMS 0x0014 | |
55 | ||
56 | /* Alarm 0 (counter) */ | |
57 | #define SUN6I_ALRM_COUNTER 0x0020 | |
58 | #define SUN6I_ALRM_CUR_VAL 0x0024 | |
59 | #define SUN6I_ALRM_EN 0x0028 | |
60 | #define SUN6I_ALRM_EN_CNT_EN BIT(0) | |
61 | #define SUN6I_ALRM_IRQ_EN 0x002c | |
62 | #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) | |
63 | #define SUN6I_ALRM_IRQ_STA 0x0030 | |
64 | #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) | |
65 | ||
66 | /* Alarm 1 (wall clock) */ | |
67 | #define SUN6I_ALRM1_EN 0x0044 | |
68 | #define SUN6I_ALRM1_IRQ_EN 0x0048 | |
69 | #define SUN6I_ALRM1_IRQ_STA 0x004c | |
70 | #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) | |
71 | ||
72 | /* Alarm config */ | |
73 | #define SUN6I_ALARM_CONFIG 0x0050 | |
74 | #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) | |
75 | ||
76 | /* | |
77 | * Get date values | |
78 | */ | |
79 | #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) | |
80 | #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) | |
81 | #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) | |
82 | #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) | |
83 | ||
84 | /* | |
85 | * Get time values | |
86 | */ | |
87 | #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) | |
88 | #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) | |
89 | #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) | |
90 | ||
91 | /* | |
92 | * Set date values | |
93 | */ | |
94 | #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) | |
95 | #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) | |
96 | #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) | |
97 | #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) | |
98 | ||
99 | /* | |
100 | * Set time values | |
101 | */ | |
102 | #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) | |
103 | #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) | |
104 | #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) | |
105 | ||
106 | /* | |
107 | * The year parameter passed to the driver is usually an offset relative to | |
108 | * the year 1900. This macro is used to convert this offset to another one | |
109 | * relative to the minimum year allowed by the hardware. | |
110 | * | |
111 | * The year range is 1970 - 2033. This range is selected to match Allwinner's | |
112 | * driver, even though it is somewhat limited. | |
113 | */ | |
114 | #define SUN6I_YEAR_MIN 1970 | |
115 | #define SUN6I_YEAR_MAX 2033 | |
116 | #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) | |
117 | ||
118 | struct sun6i_rtc_dev { | |
119 | struct rtc_device *rtc; | |
120 | struct device *dev; | |
121 | void __iomem *base; | |
122 | int irq; | |
123 | unsigned long alarm; | |
a9422a19 | 124 | |
3855c2c3 MR |
125 | struct clk_hw hw; |
126 | struct clk_hw *int_osc; | |
127 | struct clk *losc; | |
128 | ||
a9422a19 | 129 | spinlock_t lock; |
9765d2d9 CYT |
130 | }; |
131 | ||
3855c2c3 MR |
132 | static struct sun6i_rtc_dev *sun6i_rtc; |
133 | ||
134 | static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, | |
135 | unsigned long parent_rate) | |
136 | { | |
137 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
138 | u32 val; | |
139 | ||
140 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
141 | if (val & SUN6I_LOSC_CTRL_EXT_OSC) | |
142 | return parent_rate; | |
143 | ||
144 | val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); | |
145 | val &= GENMASK(4, 0); | |
146 | ||
147 | return parent_rate / (val + 1); | |
148 | } | |
149 | ||
150 | static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) | |
151 | { | |
152 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
153 | ||
154 | return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; | |
155 | } | |
156 | ||
157 | static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) | |
158 | { | |
159 | struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); | |
160 | unsigned long flags; | |
161 | u32 val; | |
162 | ||
163 | if (index > 1) | |
164 | return -EINVAL; | |
165 | ||
166 | spin_lock_irqsave(&rtc->lock, flags); | |
167 | val = readl(rtc->base + SUN6I_LOSC_CTRL); | |
168 | val &= ~SUN6I_LOSC_CTRL_EXT_OSC; | |
169 | val |= SUN6I_LOSC_CTRL_KEY; | |
170 | val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; | |
171 | writel(val, rtc->base + SUN6I_LOSC_CTRL); | |
172 | spin_unlock_irqrestore(&rtc->lock, flags); | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | static const struct clk_ops sun6i_rtc_osc_ops = { | |
178 | .recalc_rate = sun6i_rtc_osc_recalc_rate, | |
179 | ||
180 | .get_parent = sun6i_rtc_osc_get_parent, | |
181 | .set_parent = sun6i_rtc_osc_set_parent, | |
182 | }; | |
183 | ||
184 | static void __init sun6i_rtc_clk_init(struct device_node *node) | |
185 | { | |
186 | struct clk_hw_onecell_data *clk_data; | |
187 | struct sun6i_rtc_dev *rtc; | |
188 | struct clk_init_data init = { | |
189 | .ops = &sun6i_rtc_osc_ops, | |
190 | }; | |
191 | const char *parents[2]; | |
192 | ||
193 | rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); | |
194 | if (!rtc) | |
195 | return; | |
196 | spin_lock_init(&rtc->lock); | |
197 | ||
198 | clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws), | |
199 | GFP_KERNEL); | |
200 | if (!clk_data) | |
201 | return; | |
202 | spin_lock_init(&rtc->lock); | |
203 | ||
204 | rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); | |
aaa65a9c | 205 | if (IS_ERR(rtc->base)) { |
3855c2c3 MR |
206 | pr_crit("Can't map RTC registers"); |
207 | return; | |
208 | } | |
209 | ||
210 | /* Switch to the external, more precise, oscillator */ | |
211 | writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC, | |
212 | rtc->base + SUN6I_LOSC_CTRL); | |
213 | ||
15829cf4 CYT |
214 | /* Yes, I know, this is ugly. */ |
215 | sun6i_rtc = rtc; | |
216 | ||
3855c2c3 MR |
217 | /* Deal with old DTs */ |
218 | if (!of_get_property(node, "clocks", NULL)) | |
219 | return; | |
220 | ||
221 | rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, | |
222 | "rtc-int-osc", | |
223 | NULL, 0, | |
224 | 667000, | |
225 | 300000000); | |
226 | if (IS_ERR(rtc->int_osc)) { | |
227 | pr_crit("Couldn't register the internal oscillator\n"); | |
228 | return; | |
229 | } | |
230 | ||
231 | parents[0] = clk_hw_get_name(rtc->int_osc); | |
232 | parents[1] = of_clk_get_parent_name(node, 0); | |
233 | ||
234 | rtc->hw.init = &init; | |
235 | ||
236 | init.parent_names = parents; | |
237 | init.num_parents = of_clk_get_parent_count(node) + 1; | |
238 | of_property_read_string(node, "clock-output-names", &init.name); | |
239 | ||
240 | rtc->losc = clk_register(NULL, &rtc->hw); | |
241 | if (IS_ERR(rtc->losc)) { | |
242 | pr_crit("Couldn't register the LOSC clock\n"); | |
243 | return; | |
244 | } | |
245 | ||
246 | clk_data->num = 1; | |
247 | clk_data->hws[0] = &rtc->hw; | |
248 | of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); | |
3855c2c3 MR |
249 | } |
250 | CLK_OF_DECLARE_DRIVER(sun6i_rtc_clk, "allwinner,sun6i-a31-rtc", | |
251 | sun6i_rtc_clk_init); | |
252 | ||
9765d2d9 CYT |
253 | static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) |
254 | { | |
255 | struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; | |
a9422a19 | 256 | irqreturn_t ret = IRQ_NONE; |
9765d2d9 CYT |
257 | u32 val; |
258 | ||
a9422a19 | 259 | spin_lock(&chip->lock); |
9765d2d9 CYT |
260 | val = readl(chip->base + SUN6I_ALRM_IRQ_STA); |
261 | ||
262 | if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { | |
263 | val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; | |
264 | writel(val, chip->base + SUN6I_ALRM_IRQ_STA); | |
265 | ||
266 | rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); | |
267 | ||
a9422a19 | 268 | ret = IRQ_HANDLED; |
9765d2d9 | 269 | } |
a9422a19 | 270 | spin_unlock(&chip->lock); |
9765d2d9 | 271 | |
a9422a19 | 272 | return ret; |
9765d2d9 CYT |
273 | } |
274 | ||
275 | static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) | |
276 | { | |
277 | u32 alrm_val = 0; | |
278 | u32 alrm_irq_val = 0; | |
279 | u32 alrm_wake_val = 0; | |
a9422a19 | 280 | unsigned long flags; |
9765d2d9 CYT |
281 | |
282 | if (to) { | |
283 | alrm_val = SUN6I_ALRM_EN_CNT_EN; | |
284 | alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; | |
285 | alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; | |
286 | } else { | |
287 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
288 | chip->base + SUN6I_ALRM_IRQ_STA); | |
289 | } | |
290 | ||
a9422a19 | 291 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
292 | writel(alrm_val, chip->base + SUN6I_ALRM_EN); |
293 | writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); | |
294 | writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); | |
a9422a19 | 295 | spin_unlock_irqrestore(&chip->lock, flags); |
9765d2d9 CYT |
296 | } |
297 | ||
298 | static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
299 | { | |
300 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
301 | u32 date, time; | |
302 | ||
303 | /* | |
304 | * read again in case it changes | |
305 | */ | |
306 | do { | |
307 | date = readl(chip->base + SUN6I_RTC_YMD); | |
308 | time = readl(chip->base + SUN6I_RTC_HMS); | |
309 | } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || | |
310 | (time != readl(chip->base + SUN6I_RTC_HMS))); | |
311 | ||
312 | rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); | |
313 | rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); | |
314 | rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); | |
315 | ||
316 | rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); | |
317 | rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date); | |
318 | rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); | |
319 | ||
320 | rtc_tm->tm_mon -= 1; | |
321 | ||
322 | /* | |
323 | * switch from (data_year->min)-relative offset to | |
324 | * a (1900)-relative one | |
325 | */ | |
326 | rtc_tm->tm_year += SUN6I_YEAR_OFF; | |
327 | ||
328 | return rtc_valid_tm(rtc_tm); | |
329 | } | |
330 | ||
331 | static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
332 | { | |
333 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
a9422a19 | 334 | unsigned long flags; |
9765d2d9 CYT |
335 | u32 alrm_st; |
336 | u32 alrm_en; | |
337 | ||
a9422a19 | 338 | spin_lock_irqsave(&chip->lock, flags); |
9765d2d9 CYT |
339 | alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); |
340 | alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); | |
a9422a19 MR |
341 | spin_unlock_irqrestore(&chip->lock, flags); |
342 | ||
9765d2d9 CYT |
343 | wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); |
344 | wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); | |
345 | rtc_time_to_tm(chip->alarm, &wkalrm->time); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
351 | { | |
352 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
353 | struct rtc_time *alrm_tm = &wkalrm->time; | |
354 | struct rtc_time tm_now; | |
355 | unsigned long time_now = 0; | |
356 | unsigned long time_set = 0; | |
357 | unsigned long time_gap = 0; | |
358 | int ret = 0; | |
359 | ||
360 | ret = sun6i_rtc_gettime(dev, &tm_now); | |
361 | if (ret < 0) { | |
362 | dev_err(dev, "Error in getting time\n"); | |
363 | return -EINVAL; | |
364 | } | |
365 | ||
366 | rtc_tm_to_time(alrm_tm, &time_set); | |
367 | rtc_tm_to_time(&tm_now, &time_now); | |
368 | if (time_set <= time_now) { | |
369 | dev_err(dev, "Date to set in the past\n"); | |
370 | return -EINVAL; | |
371 | } | |
372 | ||
373 | time_gap = time_set - time_now; | |
374 | ||
375 | if (time_gap > U32_MAX) { | |
376 | dev_err(dev, "Date too far in the future\n"); | |
377 | return -EINVAL; | |
378 | } | |
379 | ||
380 | sun6i_rtc_setaie(0, chip); | |
381 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
382 | usleep_range(100, 300); | |
383 | ||
384 | writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); | |
385 | chip->alarm = time_set; | |
386 | ||
387 | sun6i_rtc_setaie(wkalrm->enabled, chip); | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, | |
393 | unsigned int mask, unsigned int ms_timeout) | |
394 | { | |
395 | const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); | |
396 | u32 reg; | |
397 | ||
398 | do { | |
399 | reg = readl(chip->base + offset); | |
400 | reg &= mask; | |
401 | ||
402 | if (!reg) | |
403 | return 0; | |
404 | ||
405 | } while (time_before(jiffies, timeout)); | |
406 | ||
407 | return -ETIMEDOUT; | |
408 | } | |
409 | ||
410 | static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) | |
411 | { | |
412 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
413 | u32 date = 0; | |
414 | u32 time = 0; | |
415 | int year; | |
416 | ||
417 | year = rtc_tm->tm_year + 1900; | |
418 | if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) { | |
419 | dev_err(dev, "rtc only supports year in range %d - %d\n", | |
420 | SUN6I_YEAR_MIN, SUN6I_YEAR_MAX); | |
421 | return -EINVAL; | |
422 | } | |
423 | ||
424 | rtc_tm->tm_year -= SUN6I_YEAR_OFF; | |
425 | rtc_tm->tm_mon += 1; | |
426 | ||
427 | date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | | |
428 | SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | | |
429 | SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); | |
430 | ||
431 | if (is_leap_year(year)) | |
432 | date |= SUN6I_LEAP_SET_VALUE(1); | |
433 | ||
434 | time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | | |
435 | SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | | |
436 | SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); | |
437 | ||
438 | /* Check whether registers are writable */ | |
439 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
440 | SUN6I_LOSC_CTRL_ACC_MASK, 50)) { | |
441 | dev_err(dev, "rtc is still busy.\n"); | |
442 | return -EBUSY; | |
443 | } | |
444 | ||
445 | writel(time, chip->base + SUN6I_RTC_HMS); | |
446 | ||
447 | /* | |
448 | * After writing the RTC HH-MM-SS register, the | |
449 | * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not | |
450 | * be cleared until the real writing operation is finished | |
451 | */ | |
452 | ||
453 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
454 | SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { | |
455 | dev_err(dev, "Failed to set rtc time.\n"); | |
456 | return -ETIMEDOUT; | |
457 | } | |
458 | ||
459 | writel(date, chip->base + SUN6I_RTC_YMD); | |
460 | ||
461 | /* | |
462 | * After writing the RTC YY-MM-DD register, the | |
463 | * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not | |
464 | * be cleared until the real writing operation is finished | |
465 | */ | |
466 | ||
467 | if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, | |
468 | SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { | |
469 | dev_err(dev, "Failed to set rtc time.\n"); | |
470 | return -ETIMEDOUT; | |
471 | } | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
477 | { | |
478 | struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); | |
479 | ||
480 | if (!enabled) | |
481 | sun6i_rtc_setaie(enabled, chip); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static const struct rtc_class_ops sun6i_rtc_ops = { | |
487 | .read_time = sun6i_rtc_gettime, | |
488 | .set_time = sun6i_rtc_settime, | |
489 | .read_alarm = sun6i_rtc_getalarm, | |
490 | .set_alarm = sun6i_rtc_setalarm, | |
491 | .alarm_irq_enable = sun6i_rtc_alarm_irq_enable | |
492 | }; | |
493 | ||
494 | static int sun6i_rtc_probe(struct platform_device *pdev) | |
495 | { | |
3855c2c3 | 496 | struct sun6i_rtc_dev *chip = sun6i_rtc; |
9765d2d9 CYT |
497 | int ret; |
498 | ||
9765d2d9 | 499 | if (!chip) |
3855c2c3 | 500 | return -ENODEV; |
9765d2d9 CYT |
501 | |
502 | platform_set_drvdata(pdev, chip); | |
503 | chip->dev = &pdev->dev; | |
504 | ||
9765d2d9 CYT |
505 | chip->irq = platform_get_irq(pdev, 0); |
506 | if (chip->irq < 0) { | |
507 | dev_err(&pdev->dev, "No IRQ resource\n"); | |
508 | return chip->irq; | |
509 | } | |
510 | ||
511 | ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, | |
512 | 0, dev_name(&pdev->dev), chip); | |
513 | if (ret) { | |
514 | dev_err(&pdev->dev, "Could not request IRQ\n"); | |
515 | return ret; | |
516 | } | |
517 | ||
518 | /* clear the alarm counter value */ | |
519 | writel(0, chip->base + SUN6I_ALRM_COUNTER); | |
520 | ||
521 | /* disable counter alarm */ | |
522 | writel(0, chip->base + SUN6I_ALRM_EN); | |
523 | ||
524 | /* disable counter alarm interrupt */ | |
525 | writel(0, chip->base + SUN6I_ALRM_IRQ_EN); | |
526 | ||
527 | /* disable week alarm */ | |
528 | writel(0, chip->base + SUN6I_ALRM1_EN); | |
529 | ||
530 | /* disable week alarm interrupt */ | |
531 | writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); | |
532 | ||
533 | /* clear counter alarm pending interrupts */ | |
534 | writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, | |
535 | chip->base + SUN6I_ALRM_IRQ_STA); | |
536 | ||
537 | /* clear week alarm pending interrupts */ | |
538 | writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, | |
539 | chip->base + SUN6I_ALRM1_IRQ_STA); | |
540 | ||
541 | /* disable alarm wakeup */ | |
542 | writel(0, chip->base + SUN6I_ALARM_CONFIG); | |
543 | ||
3855c2c3 | 544 | clk_prepare_enable(chip->losc); |
fb61bb82 | 545 | |
5dff3a31 MR |
546 | chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i", |
547 | &sun6i_rtc_ops, THIS_MODULE); | |
9765d2d9 CYT |
548 | if (IS_ERR(chip->rtc)) { |
549 | dev_err(&pdev->dev, "unable to register device\n"); | |
550 | return PTR_ERR(chip->rtc); | |
551 | } | |
552 | ||
553 | dev_info(&pdev->dev, "RTC enabled\n"); | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
9765d2d9 CYT |
558 | static const struct of_device_id sun6i_rtc_dt_ids[] = { |
559 | { .compatible = "allwinner,sun6i-a31-rtc" }, | |
560 | { /* sentinel */ }, | |
561 | }; | |
562 | MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); | |
563 | ||
564 | static struct platform_driver sun6i_rtc_driver = { | |
565 | .probe = sun6i_rtc_probe, | |
9765d2d9 CYT |
566 | .driver = { |
567 | .name = "sun6i-rtc", | |
568 | .of_match_table = sun6i_rtc_dt_ids, | |
569 | }, | |
570 | }; | |
37539414 | 571 | builtin_platform_driver(sun6i_rtc_driver); |