[linux-block.git] / drivers / rtc / rtc-stmp3xxx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale STMP37XX/STMP378X Real Time Clock driver
 *
 * Copyright (c) 2007 Sigmatel, Inc.
 * Peter Hartley, <peter.hartley@sigmatel.com>
 *
 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/stmp_device.h>
#include <linux/stmp3xxx_rtc_wdt.h>

#define STMP3XXX_RTC_CTRL			0x0
#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN		0x00000001
#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN	0x00000002
#define STMP3XXX_RTC_CTRL_ALARM_IRQ		0x00000004
#define STMP3XXX_RTC_CTRL_WATCHDOGEN		0x00000010

#define STMP3XXX_RTC_STAT			0x10
#define STMP3XXX_RTC_STAT_STALE_SHIFT		16
#define STMP3XXX_RTC_STAT_RTC_PRESENT		0x80000000
#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT	0x10000000
#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT	0x08000000

#define STMP3XXX_RTC_SECONDS			0x30

#define STMP3XXX_RTC_ALARM			0x40

#define STMP3XXX_RTC_WATCHDOG			0x50

#define STMP3XXX_RTC_PERSISTENT0		0x60
#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE		(1 << 0)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN		(1 << 1)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN		(1 << 2)
#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP	(1 << 4)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP	(1 << 5)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ		(1 << 6)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE		(1 << 7)

#define STMP3XXX_RTC_PERSISTENT1		0x70
/* missing bitmask in headers */
#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER	0x80000000

struct stmp3xxx_rtc_data {
	struct rtc_device *rtc;
	void __iomem *io;
	int irq_alarm;
};

#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
/**
 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
 * @dev: the parent device of the watchdog (= the RTC)
 * @timeout: the desired value for the timeout register of the watchdog.
 *           0 disables the watchdog
 *
 * The watchdog needs one register and two bits which are in the RTC domain.
 * To handle the resource conflict, the RTC driver will create another
 * platform_device for the watchdog driver as a child of the RTC device.
 * The watchdog driver is passed the below accessor function via platform_data
 * to configure the watchdog. Locking is not needed because accessing SET/CLR
 * registers is atomic.
 */

static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (timeout) {
		writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	} else {
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	}
}

static struct stmp3xxx_wdt_pdata wdt_pdata = {
	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
};

static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
	int rc = -1;
	struct platform_device *wdt_pdev =
		platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);

	if (wdt_pdev) {
		wdt_pdev->dev.parent = &rtc_pdev->dev;
		wdt_pdev->dev.platform_data = &wdt_pdata;
		rc = platform_device_add(wdt_pdev);
		if (rc)
			platform_device_put(wdt_pdev);
	}

	if (rc)
		dev_err(&rtc_pdev->dev,
			"failed to register stmp3xxx_rtc_wdt\n");
}
#else
static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
}
#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */

static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
{
	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
	/*
	 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	 * states:
	 * | The order in which registers are updated is
	 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	 * | (This list is in bitfield order, from LSB to MSB, as they would
	 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	 * | register. For example, the Seconds register corresponds to
	 * | STALE_REGS or NEW_REGS containing 0x80.)
	 */
	do {
		if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
				(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
			return 0;
		udelay(1);
	} while (--timeout > 0);
	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
		(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
}

/* Time read/write */
static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
{
	int ret;
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	ret = stmp3xxx_wait_time(rtc_data);
	if (ret)
		return ret;

	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
	return 0;
}

static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
	return stmp3xxx_wait_time(rtc_data);
}

/* interrupt(s) handler */
static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);

	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
		rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (enabled) {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
				STMP_OFFSET_REG_SET);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
	} else {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
				STMP_OFFSET_REG_CLR);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
	}
	return 0;
}

static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
	return 0;
}

static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);

	stmp3xxx_alarm_irq_enable(dev, alm->enabled);

	return 0;
}

static const struct rtc_class_ops stmp3xxx_rtc_ops = {
	.alarm_irq_enable =
			  stmp3xxx_alarm_irq_enable,
	.read_time	= stmp3xxx_rtc_gettime,
	.set_time	= stmp3xxx_rtc_settime,
	.read_alarm	= stmp3xxx_rtc_read_alarm,
	.set_alarm	= stmp3xxx_rtc_set_alarm,
};

static int stmp3xxx_rtc_remove(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);

	if (!rtc_data)
		return 0;

	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
		rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);

	return 0;
}

static int stmp3xxx_rtc_probe(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data;
	struct resource *r;
	u32 rtc_stat;
	u32 pers0_set, pers0_clr;
	u32 crystalfreq = 0;
	int err;

	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
	if (!rtc_data)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "failed to get resource\n");
		return -ENXIO;
	}

	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!rtc_data->io) {
		dev_err(&pdev->dev, "ioremap failed\n");
		return -EIO;
	}

	rtc_data->irq_alarm = platform_get_irq(pdev, 0);

	rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
	if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
		dev_err(&pdev->dev, "no device onboard\n");
		return -ENODEV;
	}

	platform_set_drvdata(pdev, rtc_data);

	/*
	 * Resetting the rtc stops the watchdog timer that is potentially
	 * running. So (assuming it is running on purpose) don't reset if the
	 * watchdog is enabled.
	 */
	if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
	    STMP3XXX_RTC_CTRL_WATCHDOGEN) {
		dev_info(&pdev->dev,
			 "Watchdog is running, skip resetting rtc\n");
	} else {
		err = stmp_reset_block(rtc_data->io);
		if (err) {
			dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
				err);
			return err;
		}
	}

	/*
	 * Obviously the rtc needs a clock input to be able to run.
	 * This clock can be provided by an external 32k crystal. If that one is
	 * missing XTAL must not be disabled in suspend which consumes a
	 * lot of power. Normally the presence and exact frequency (supported
	 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
	 * proves these fuses are not blown correctly on all machines, so the
	 * frequency can be overridden in the device tree.
	 */
	if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
		crystalfreq = 32000;
	else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
		crystalfreq = 32768;

	of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
			     &crystalfreq);

	switch (crystalfreq) {
	case 32000:
		/* keep 32kHz crystal running in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
			STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
		break;
	case 32768:
		/* keep 32.768kHz crystal running in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
		break;
	default:
		dev_warn(&pdev->dev,
			 "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
		fallthrough;
	case 0:
		/* keep XTAL on in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	}

	writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
			STMP_OFFSET_REG_SET);

	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);

	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
			STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
		rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);

	rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc_data->rtc))
		return PTR_ERR(rtc_data->rtc);

	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
			stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
	if (err) {
		dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
			rtc_data->irq_alarm);
		return err;
	}

	rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
	rtc_data->rtc->range_max = U32_MAX;

	err = devm_rtc_register_device(rtc_data->rtc);
	if (err)
		return err;

	stmp3xxx_wdt_register(pdev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int stmp3xxx_rtc_suspend(struct device *dev)
{
	return 0;
}

static int stmp3xxx_rtc_resume(struct device *dev)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	stmp_reset_block(rtc_data->io);
	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
			stmp3xxx_rtc_resume);

static const struct of_device_id rtc_dt_ids[] = {
	{ .compatible = "fsl,stmp3xxx-rtc", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rtc_dt_ids);

static struct platform_driver stmp3xxx_rtcdrv = {
	.probe		= stmp3xxx_rtc_probe,
	.remove		= stmp3xxx_rtc_remove,
	.driver		= {
		.name	= "stmp3xxx-rtc",
		.pm	= &stmp3xxx_rtc_pm_ops,
		.of_match_table = rtc_dt_ids,
	},
};

module_platform_driver(stmp3xxx_rtcdrv);

MODULE_DESCRIPTION("STMP3xxx RTC Driver");
MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
		"Wolfram Sang <kernel@pengutronix.de>");
MODULE_LICENSE("GPL");
Commit	Line	Data
838d2d91	1	// SPDX-License-Identifier: GPL-2.0+
df17f631	2	/*
	3	* Freescale STMP37XX/STMP378X Real Time Clock driver
	4	*
	5	* Copyright (c) 2007 Sigmatel, Inc.
	6	* Peter Hartley, <peter.hartley@sigmatel.com>
	7	*
	8	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	9	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7e794cb7	10	* Copyright 2011 Wolfram Sang, Pengutronix e.K.
df17f631	11	*/
df17f631	12	#include <linux/kernel.h>
df17f631	13	#include <linux/module.h>
b5167159	14	#include <linux/io.h>
df17f631	15	#include <linux/init.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/interrupt.h>
28a0c883	18	#include <linux/delay.h>
df17f631	19	#include <linux/rtc.h>
5a0e3ad6	20	#include <linux/slab.h>
dd8d20a3	21	#include <linux/of_device.h>
c8a6046e	22	#include <linux/of.h>
1a71fb84 WS	23	#include <linux/stmp_device.h>
1a71fb84 WS	24	#include <linux/stmp3xxx_rtc_wdt.h>
df17f631	25
47eac337 WS	26	#define STMP3XXX_RTC_CTRL 0x0
	27	#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
	28	#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
	29	#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
1a71fb84	30	#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
47eac337 WS	31
	32	#define STMP3XXX_RTC_STAT 0x10
	33	#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
	34	#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
7f48b21b UKK	35	#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
7f48b21b UKK	36	#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
47eac337 WS	37
	38	#define STMP3XXX_RTC_SECONDS 0x30
	39
	40	#define STMP3XXX_RTC_ALARM 0x40
	41
1a71fb84 WS	42	#define STMP3XXX_RTC_WATCHDOG 0x50
1a71fb84 WS	43
47eac337	44	#define STMP3XXX_RTC_PERSISTENT0 0x60
7f48b21b UKK	45	#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
	46	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
	47	#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
	48	#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
	49	#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
	50	#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
	51	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
df17f631	52
1a71fb84 WS	53	#define STMP3XXX_RTC_PERSISTENT1 0x70
	54	/* missing bitmask in headers */
	55	#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
	56
df17f631	57	struct stmp3xxx_rtc_data {
df17f631	58	struct rtc_device *rtc;
df17f631	59	void __iomem *io;
7e794cb7	60	int irq_alarm;
df17f631	61	};
df17f631	62
1a71fb84 WS	63	#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
	64	/**
	65	* stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
	66	* @dev: the parent device of the watchdog (= the RTC)
	67	* @timeout: the desired value for the timeout register of the watchdog.
	68	* 0 disables the watchdog
	69	*
	70	* The watchdog needs one register and two bits which are in the RTC domain.
	71	* To handle the resource conflict, the RTC driver will create another
	72	* platform_device for the watchdog driver as a child of the RTC device.
	73	* The watchdog driver is passed the below accessor function via platform_data
	74	* to configure the watchdog. Locking is not needed because accessing SET/CLR
	75	* registers is atomic.
	76	*/
	77
	78	static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
	79	{
	80	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	81
	82	if (timeout) {
	83	writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
	84	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	85	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
	86	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	87	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	88	} else {
	89	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	90	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
	91	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	92	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	93	}
	94	}
	95
	96	static struct stmp3xxx_wdt_pdata wdt_pdata = {
	97	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
	98	};
	99
	100	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	101	{
3497610a	102	int rc = -1;
1a71fb84 WS	103	struct platform_device *wdt_pdev =
	104	platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
	105
	106	if (wdt_pdev) {
	107	wdt_pdev->dev.parent = &rtc_pdev->dev;
	108	wdt_pdev->dev.platform_data = &wdt_pdata;
3497610a	109	rc = platform_device_add(wdt_pdev);
07590111 LY	110	if (rc)
07590111 LY	111	platform_device_put(wdt_pdev);
1a71fb84	112	}
3497610a SM	113
	114	if (rc)
	115	dev_err(&rtc_pdev->dev,
	116	"failed to register stmp3xxx_rtc_wdt\n");
1a71fb84 WS	117	}
	118	#else
	119	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	120	{
	121	}
	122	#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
	123
28a0c883	124	static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
df17f631	125	{
28a0c883	126	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
df17f631	127	/*
28a0c883 LW	128	* The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	129	* states:
	130	* \| The order in which registers are updated is
	131	* \| Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	132	* \| (This list is in bitfield order, from LSB to MSB, as they would
	133	* \| appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	134	* \| register. For example, the Seconds register corresponds to
	135	* \| STALE_REGS or NEW_REGS containing 0x80.)
df17f631	136	*/
28a0c883 LW	137	do {
	138	if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	139	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
	140	return 0;
	141	udelay(1);
	142	} while (--timeout > 0);
	143	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	144	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
df17f631	145	}
	146
	147	/* Time read/write */
	148	static int stmp3xxx_rtc_gettime(struct device dev, struct rtc_time rtc_tm)
	149	{
28a0c883	150	int ret;
df17f631	151	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	152
28a0c883 LW	153	ret = stmp3xxx_wait_time(rtc_data);
	154	if (ret)
	155	return ret;
	156
a659a081	157	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
df17f631	158	return 0;
	159	}
	160
622eb9b4	161	static int stmp3xxx_rtc_settime(struct device dev, struct rtc_time rtc_tm)
df17f631	162	{
	163	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	164
622eb9b4	165	writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
28a0c883	166	return stmp3xxx_wait_time(rtc_data);
df17f631	167	}
	168
	169	/* interrupt(s) handler */
	170	static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
	171	{
	172	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
7e794cb7	173	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
df17f631	174
47eac337	175	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
b5167159	176	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
24417829	177	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
7e794cb7 WS	178	rtc_update_irq(rtc_data->rtc, 1, RTC_AF \| RTC_IRQF);
7e794cb7 WS	179	return IRQ_HANDLED;
df17f631	180	}
df17f631	181
7e794cb7	182	return IRQ_NONE;
df17f631	183	}
	184
	185	static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
	186	{
	187	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	188
df17f631	189	if (enabled) {
b5167159 WS	190	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
b5167159 WS	191	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
24417829 HG	192	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	193	STMP_OFFSET_REG_SET);
b5167159	194	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	195	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
df17f631	196	} else {
b5167159 WS	197	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
b5167159 WS	198	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
24417829 HG	199	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	200	STMP_OFFSET_REG_CLR);
b5167159	201	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	202	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
df17f631	203	}
	204	return 0;
	205	}
	206
df17f631	207	static int stmp3xxx_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
	208	{
	209	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	210
a659a081	211	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
df17f631	212	return 0;
	213	}
	214
	215	static int stmp3xxx_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
	216	{
df17f631	217	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	218
a659a081	219	writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
7e794cb7 WS	220
	221	stmp3xxx_alarm_irq_enable(dev, alm->enabled);
	222
df17f631	223	return 0;
	224	}
	225
34c7b3ac	226	static const struct rtc_class_ops stmp3xxx_rtc_ops = {
df17f631	227	.alarm_irq_enable =
df17f631	228	stmp3xxx_alarm_irq_enable,
df17f631	229	.read_time = stmp3xxx_rtc_gettime,
622eb9b4	230	.set_time = stmp3xxx_rtc_settime,
df17f631	231	.read_alarm = stmp3xxx_rtc_read_alarm,
	232	.set_alarm = stmp3xxx_rtc_set_alarm,
	233	};
	234
	235	static int stmp3xxx_rtc_remove(struct platform_device *pdev)
	236	{
	237	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
	238
	239	if (!rtc_data)
	240	return 0;
	241
7e794cb7	242	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	243	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
df17f631	244
	245	return 0;
	246	}
	247
	248	static int stmp3xxx_rtc_probe(struct platform_device *pdev)
	249	{
	250	struct stmp3xxx_rtc_data *rtc_data;
	251	struct resource *r;
7f48b21b UKK	252	u32 rtc_stat;
	253	u32 pers0_set, pers0_clr;
	254	u32 crystalfreq = 0;
df17f631	255	int err;
df17f631	256
87a81420	257	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
df17f631	258	if (!rtc_data)
	259	return -ENOMEM;
	260
	261	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	262	if (!r) {
	263	dev_err(&pdev->dev, "failed to get resource\n");
87a81420	264	return -ENXIO;
df17f631	265	}
df17f631	266
87a81420	267	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
df17f631	268	if (!rtc_data->io) {
df17f631	269	dev_err(&pdev->dev, "ioremap failed\n");
87a81420	270	return -EIO;
df17f631	271	}
	272
	273	rtc_data->irq_alarm = platform_get_irq(pdev, 0);
df17f631	274
7f48b21b UKK	275	rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
7f48b21b UKK	276	if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
df17f631	277	dev_err(&pdev->dev, "no device onboard\n");
87a81420	278	return -ENODEV;
df17f631	279	}
df17f631	280
a91d2bab WS	281	platform_set_drvdata(pdev, rtc_data);
a91d2bab WS	282
dff700fa UKK	283	/*
	284	* Resetting the rtc stops the watchdog timer that is potentially
	285	* running. So (assuming it is running on purpose) don't reset if the
	286	* watchdog is enabled.
	287	*/
	288	if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
	289	STMP3XXX_RTC_CTRL_WATCHDOGEN) {
	290	dev_info(&pdev->dev,
	291	"Watchdog is running, skip resetting rtc\n");
	292	} else {
	293	err = stmp_reset_block(rtc_data->io);
	294	if (err) {
	295	dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
	296	err);
	297	return err;
	298	}
4e80b188 FE	299	}
4e80b188 FE	300
7f48b21b UKK	301	/*
	302	* Obviously the rtc needs a clock input to be able to run.
	303	* This clock can be provided by an external 32k crystal. If that one is
	304	* missing XTAL must not be disabled in suspend which consumes a
	305	* lot of power. Normally the presence and exact frequency (supported
	306	* are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
	307	* proves these fuses are not blown correctly on all machines, so the
	308	* frequency can be overridden in the device tree.
	309	*/
	310	if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
	311	crystalfreq = 32000;
	312	else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
	313	crystalfreq = 32768;
	314
	315	of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
	316	&crystalfreq);
	317
	318	switch (crystalfreq) {
	319	case 32000:
	320	/* keep 32kHz crystal running in low-power mode */
	321	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ \|
	322	STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	323	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	324	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
	325	break;
	326	case 32768:
	327	/* keep 32.768kHz crystal running in low-power mode */
	328	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	329	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	330	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP \|
	331	STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
	332	break;
	333	default:
	334	dev_warn(&pdev->dev,
	335	"invalid crystal-freq specified in device-tree. Assuming no crystal\n");
df561f66	336	fallthrough;
7f48b21b UKK	337	case 0:
	338	/* keep XTAL on in low-power mode */
	339	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
	340	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	341	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	342	}
	343
24417829 HG	344	writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	345	STMP_OFFSET_REG_SET);
7f48b21b	346
b5167159	347	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337	348	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
7f48b21b	349	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE \| pers0_clr,
24417829	350	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
a91d2bab	351
7e794cb7 WS	352	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN \|
7e794cb7 WS	353	STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	354	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
7e794cb7	355
0d823abd	356	rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
dfd2a178 JH	357	if (IS_ERR(rtc_data->rtc))
dfd2a178 JH	358	return PTR_ERR(rtc_data->rtc);
df17f631	359
87a81420 JH	360	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
87a81420 JH	361	stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
df17f631	362	if (err) {
	363	dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
	364	rtc_data->irq_alarm);
dfd2a178	365	return err;
df17f631	366	}
df17f631	367
0d823abd AB	368	rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
	369	rtc_data->rtc->range_max = U32_MAX;
	370
fdcfd854	371	err = devm_rtc_register_device(rtc_data->rtc);
0d823abd AB	372	if (err)
	373	return err;
	374
1a71fb84	375	stmp3xxx_wdt_register(pdev);
df17f631	376	return 0;
df17f631	377	}
df17f631	378
ef69a7f0 JH	379	#ifdef CONFIG_PM_SLEEP
ef69a7f0 JH	380	static int stmp3xxx_rtc_suspend(struct device *dev)
df17f631	381	{
	382	return 0;
	383	}
	384
ef69a7f0	385	static int stmp3xxx_rtc_resume(struct device *dev)
df17f631	386	{
ef69a7f0	387	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	388
36d1da1d	389	stmp_reset_block(rtc_data->io);
b5167159	390	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337 WS	391	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
47eac337 WS	392	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
24417829	393	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
df17f631	394	return 0;
df17f631	395	}
df17f631	396	#endif
df17f631	397
ef69a7f0 JH	398	static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
	399	stmp3xxx_rtc_resume);
	400
dd8d20a3 MV	401	static const struct of_device_id rtc_dt_ids[] = {
	402	{ .compatible = "fsl,stmp3xxx-rtc", },
	403	{ /* sentinel */ }
	404	};
	405	MODULE_DEVICE_TABLE(of, rtc_dt_ids);
	406
df17f631	407	static struct platform_driver stmp3xxx_rtcdrv = {
	408	.probe = stmp3xxx_rtc_probe,
	409	.remove = stmp3xxx_rtc_remove,
df17f631	410	.driver = {
df17f631	411	.name = "stmp3xxx-rtc",
ef69a7f0	412	.pm = &stmp3xxx_rtc_pm_ops,
462a465b	413	.of_match_table = rtc_dt_ids,
df17f631	414	},
	415	};
	416
0c4eae66	417	module_platform_driver(stmp3xxx_rtcdrv);
df17f631	418
df17f631	419	MODULE_DESCRIPTION("STMP3xxx RTC Driver");
7e794cb7	420	MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
32271efd	421	"Wolfram Sang <kernel@pengutronix.de>");
df17f631	422	MODULE_LICENSE("GPL");