Commit | Line | Data |
---|---|---|
24805645 | 1 | // SPDX-License-Identifier: GPL-2.0 |
4e64350f | 2 | /* |
24805645 AD |
3 | * Copyright (C) STMicroelectronics 2017 |
4 | * Author: Amelie Delaunay <amelie.delaunay@st.com> | |
4e64350f AD |
5 | */ |
6 | ||
7 | #include <linux/bcd.h> | |
8 | #include <linux/clk.h> | |
9 | #include <linux/iopoll.h> | |
10 | #include <linux/ioport.h> | |
11 | #include <linux/mfd/syscon.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of_device.h> | |
b72252b6 | 14 | #include <linux/pm_wakeirq.h> |
4e64350f AD |
15 | #include <linux/regmap.h> |
16 | #include <linux/rtc.h> | |
17 | ||
18 | #define DRIVER_NAME "stm32_rtc" | |
19 | ||
4e64350f AD |
20 | /* STM32_RTC_TR bit fields */ |
21 | #define STM32_RTC_TR_SEC_SHIFT 0 | |
22 | #define STM32_RTC_TR_SEC GENMASK(6, 0) | |
23 | #define STM32_RTC_TR_MIN_SHIFT 8 | |
24 | #define STM32_RTC_TR_MIN GENMASK(14, 8) | |
25 | #define STM32_RTC_TR_HOUR_SHIFT 16 | |
26 | #define STM32_RTC_TR_HOUR GENMASK(21, 16) | |
27 | ||
28 | /* STM32_RTC_DR bit fields */ | |
29 | #define STM32_RTC_DR_DATE_SHIFT 0 | |
30 | #define STM32_RTC_DR_DATE GENMASK(5, 0) | |
31 | #define STM32_RTC_DR_MONTH_SHIFT 8 | |
32 | #define STM32_RTC_DR_MONTH GENMASK(12, 8) | |
33 | #define STM32_RTC_DR_WDAY_SHIFT 13 | |
34 | #define STM32_RTC_DR_WDAY GENMASK(15, 13) | |
35 | #define STM32_RTC_DR_YEAR_SHIFT 16 | |
36 | #define STM32_RTC_DR_YEAR GENMASK(23, 16) | |
37 | ||
38 | /* STM32_RTC_CR bit fields */ | |
39 | #define STM32_RTC_CR_FMT BIT(6) | |
40 | #define STM32_RTC_CR_ALRAE BIT(8) | |
41 | #define STM32_RTC_CR_ALRAIE BIT(12) | |
42 | ||
b72252b6 | 43 | /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ |
4e64350f AD |
44 | #define STM32_RTC_ISR_ALRAWF BIT(0) |
45 | #define STM32_RTC_ISR_INITS BIT(4) | |
46 | #define STM32_RTC_ISR_RSF BIT(5) | |
47 | #define STM32_RTC_ISR_INITF BIT(6) | |
48 | #define STM32_RTC_ISR_INIT BIT(7) | |
49 | #define STM32_RTC_ISR_ALRAF BIT(8) | |
50 | ||
51 | /* STM32_RTC_PRER bit fields */ | |
52 | #define STM32_RTC_PRER_PRED_S_SHIFT 0 | |
53 | #define STM32_RTC_PRER_PRED_S GENMASK(14, 0) | |
54 | #define STM32_RTC_PRER_PRED_A_SHIFT 16 | |
55 | #define STM32_RTC_PRER_PRED_A GENMASK(22, 16) | |
56 | ||
57 | /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */ | |
58 | #define STM32_RTC_ALRMXR_SEC_SHIFT 0 | |
59 | #define STM32_RTC_ALRMXR_SEC GENMASK(6, 0) | |
60 | #define STM32_RTC_ALRMXR_SEC_MASK BIT(7) | |
61 | #define STM32_RTC_ALRMXR_MIN_SHIFT 8 | |
62 | #define STM32_RTC_ALRMXR_MIN GENMASK(14, 8) | |
63 | #define STM32_RTC_ALRMXR_MIN_MASK BIT(15) | |
64 | #define STM32_RTC_ALRMXR_HOUR_SHIFT 16 | |
65 | #define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16) | |
66 | #define STM32_RTC_ALRMXR_PM BIT(22) | |
67 | #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23) | |
68 | #define STM32_RTC_ALRMXR_DATE_SHIFT 24 | |
69 | #define STM32_RTC_ALRMXR_DATE GENMASK(29, 24) | |
70 | #define STM32_RTC_ALRMXR_WDSEL BIT(30) | |
71 | #define STM32_RTC_ALRMXR_WDAY_SHIFT 24 | |
72 | #define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24) | |
73 | #define STM32_RTC_ALRMXR_DATE_MASK BIT(31) | |
74 | ||
b72252b6 AD |
75 | /* STM32_RTC_SR/_SCR bit fields */ |
76 | #define STM32_RTC_SR_ALRA BIT(0) | |
77 | ||
78 | /* STM32_RTC_VERR bit fields */ | |
79 | #define STM32_RTC_VERR_MINREV_SHIFT 0 | |
80 | #define STM32_RTC_VERR_MINREV GENMASK(3, 0) | |
81 | #define STM32_RTC_VERR_MAJREV_SHIFT 4 | |
82 | #define STM32_RTC_VERR_MAJREV GENMASK(7, 4) | |
83 | ||
4e64350f AD |
84 | /* STM32_RTC_WPR key constants */ |
85 | #define RTC_WPR_1ST_KEY 0xCA | |
86 | #define RTC_WPR_2ND_KEY 0x53 | |
87 | #define RTC_WPR_WRONG_KEY 0xFF | |
88 | ||
b72252b6 AD |
89 | /* Max STM32 RTC register offset is 0x3FC */ |
90 | #define UNDEF_REG 0xFFFF | |
91 | ||
02b0cc34 AD |
92 | struct stm32_rtc; |
93 | ||
94 | struct stm32_rtc_registers { | |
b72252b6 AD |
95 | u16 tr; |
96 | u16 dr; | |
97 | u16 cr; | |
98 | u16 isr; | |
99 | u16 prer; | |
100 | u16 alrmar; | |
101 | u16 wpr; | |
102 | u16 sr; | |
103 | u16 scr; | |
104 | u16 verr; | |
02b0cc34 AD |
105 | }; |
106 | ||
107 | struct stm32_rtc_events { | |
108 | u32 alra; | |
109 | }; | |
110 | ||
9a6757ea | 111 | struct stm32_rtc_data { |
02b0cc34 AD |
112 | const struct stm32_rtc_registers regs; |
113 | const struct stm32_rtc_events events; | |
114 | void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags); | |
9a6757ea | 115 | bool has_pclk; |
22cb47c1 | 116 | bool need_dbp; |
b72252b6 | 117 | bool has_wakeirq; |
9a6757ea AD |
118 | }; |
119 | ||
4e64350f AD |
120 | struct stm32_rtc { |
121 | struct rtc_device *rtc_dev; | |
122 | void __iomem *base; | |
123 | struct regmap *dbp; | |
22cb47c1 AD |
124 | unsigned int dbp_reg; |
125 | unsigned int dbp_mask; | |
9a6757ea AD |
126 | struct clk *pclk; |
127 | struct clk *rtc_ck; | |
02b0cc34 | 128 | const struct stm32_rtc_data *data; |
4e64350f | 129 | int irq_alarm; |
b72252b6 | 130 | int wakeirq_alarm; |
4e64350f AD |
131 | }; |
132 | ||
133 | static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) | |
134 | { | |
02b0cc34 AD |
135 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
136 | ||
137 | writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); | |
138 | writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); | |
4e64350f AD |
139 | } |
140 | ||
141 | static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc) | |
142 | { | |
02b0cc34 AD |
143 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
144 | ||
145 | writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); | |
4e64350f AD |
146 | } |
147 | ||
148 | static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) | |
149 | { | |
02b0cc34 AD |
150 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
151 | unsigned int isr = readl_relaxed(rtc->base + regs->isr); | |
4e64350f AD |
152 | |
153 | if (!(isr & STM32_RTC_ISR_INITF)) { | |
154 | isr |= STM32_RTC_ISR_INIT; | |
02b0cc34 | 155 | writel_relaxed(isr, rtc->base + regs->isr); |
4e64350f AD |
156 | |
157 | /* | |
9a6757ea | 158 | * It takes around 2 rtc_ck clock cycles to enter in |
4e64350f | 159 | * initialization phase mode (and have INITF flag set). As |
9a6757ea | 160 | * slowest rtc_ck frequency may be 32kHz and highest should be |
4e64350f AD |
161 | * 1MHz, we poll every 10 us with a timeout of 100ms. |
162 | */ | |
163 | return readl_relaxed_poll_timeout_atomic( | |
02b0cc34 | 164 | rtc->base + regs->isr, |
4e64350f AD |
165 | isr, (isr & STM32_RTC_ISR_INITF), |
166 | 10, 100000); | |
167 | } | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc) | |
173 | { | |
02b0cc34 AD |
174 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
175 | unsigned int isr = readl_relaxed(rtc->base + regs->isr); | |
4e64350f AD |
176 | |
177 | isr &= ~STM32_RTC_ISR_INIT; | |
02b0cc34 | 178 | writel_relaxed(isr, rtc->base + regs->isr); |
4e64350f AD |
179 | } |
180 | ||
181 | static int stm32_rtc_wait_sync(struct stm32_rtc *rtc) | |
182 | { | |
02b0cc34 AD |
183 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
184 | unsigned int isr = readl_relaxed(rtc->base + regs->isr); | |
4e64350f AD |
185 | |
186 | isr &= ~STM32_RTC_ISR_RSF; | |
02b0cc34 | 187 | writel_relaxed(isr, rtc->base + regs->isr); |
4e64350f AD |
188 | |
189 | /* | |
190 | * Wait for RSF to be set to ensure the calendar registers are | |
9a6757ea | 191 | * synchronised, it takes around 2 rtc_ck clock cycles |
4e64350f | 192 | */ |
02b0cc34 | 193 | return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, |
4e64350f AD |
194 | isr, |
195 | (isr & STM32_RTC_ISR_RSF), | |
196 | 10, 100000); | |
197 | } | |
198 | ||
02b0cc34 AD |
199 | static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc, |
200 | unsigned int flags) | |
201 | { | |
202 | rtc->data->clear_events(rtc, flags); | |
203 | } | |
204 | ||
4e64350f AD |
205 | static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id) |
206 | { | |
207 | struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id; | |
02b0cc34 AD |
208 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
209 | const struct stm32_rtc_events *evts = &rtc->data->events; | |
210 | unsigned int status, cr; | |
4e64350f | 211 | |
f66e7f2d | 212 | rtc_lock(rtc->rtc_dev); |
4e64350f | 213 | |
b72252b6 | 214 | status = readl_relaxed(rtc->base + regs->sr); |
02b0cc34 | 215 | cr = readl_relaxed(rtc->base + regs->cr); |
4e64350f | 216 | |
02b0cc34 | 217 | if ((status & evts->alra) && |
4e64350f AD |
218 | (cr & STM32_RTC_CR_ALRAIE)) { |
219 | /* Alarm A flag - Alarm interrupt */ | |
220 | dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n"); | |
221 | ||
222 | /* Pass event to the kernel */ | |
223 | rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); | |
224 | ||
02b0cc34 AD |
225 | /* Clear event flags, otherwise new events won't be received */ |
226 | stm32_rtc_clear_event_flags(rtc, evts->alra); | |
4e64350f AD |
227 | } |
228 | ||
f66e7f2d | 229 | rtc_unlock(rtc->rtc_dev); |
4e64350f AD |
230 | |
231 | return IRQ_HANDLED; | |
232 | } | |
233 | ||
234 | /* Convert rtc_time structure from bin to bcd format */ | |
235 | static void tm2bcd(struct rtc_time *tm) | |
236 | { | |
237 | tm->tm_sec = bin2bcd(tm->tm_sec); | |
238 | tm->tm_min = bin2bcd(tm->tm_min); | |
239 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
240 | ||
241 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
242 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); | |
243 | tm->tm_year = bin2bcd(tm->tm_year - 100); | |
244 | /* | |
245 | * Number of days since Sunday | |
246 | * - on kernel side, 0=Sunday...6=Saturday | |
247 | * - on rtc side, 0=invalid,1=Monday...7=Sunday | |
248 | */ | |
249 | tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday; | |
250 | } | |
251 | ||
252 | /* Convert rtc_time structure from bcd to bin format */ | |
253 | static void bcd2tm(struct rtc_time *tm) | |
254 | { | |
255 | tm->tm_sec = bcd2bin(tm->tm_sec); | |
256 | tm->tm_min = bcd2bin(tm->tm_min); | |
257 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
258 | ||
259 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
260 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
261 | tm->tm_year = bcd2bin(tm->tm_year) + 100; | |
262 | /* | |
263 | * Number of days since Sunday | |
264 | * - on kernel side, 0=Sunday...6=Saturday | |
265 | * - on rtc side, 0=invalid,1=Monday...7=Sunday | |
266 | */ | |
267 | tm->tm_wday %= 7; | |
268 | } | |
269 | ||
270 | static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
271 | { | |
272 | struct stm32_rtc *rtc = dev_get_drvdata(dev); | |
02b0cc34 | 273 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
4e64350f AD |
274 | unsigned int tr, dr; |
275 | ||
276 | /* Time and Date in BCD format */ | |
02b0cc34 AD |
277 | tr = readl_relaxed(rtc->base + regs->tr); |
278 | dr = readl_relaxed(rtc->base + regs->dr); | |
4e64350f AD |
279 | |
280 | tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT; | |
281 | tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT; | |
282 | tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT; | |
283 | ||
284 | tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT; | |
285 | tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT; | |
286 | tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT; | |
287 | tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT; | |
288 | ||
289 | /* We don't report tm_yday and tm_isdst */ | |
290 | ||
291 | bcd2tm(tm); | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
297 | { | |
298 | struct stm32_rtc *rtc = dev_get_drvdata(dev); | |
02b0cc34 | 299 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
4e64350f AD |
300 | unsigned int tr, dr; |
301 | int ret = 0; | |
302 | ||
303 | tm2bcd(tm); | |
304 | ||
305 | /* Time in BCD format */ | |
306 | tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) | | |
307 | ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) | | |
308 | ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR); | |
309 | ||
310 | /* Date in BCD format */ | |
311 | dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) | | |
312 | ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) | | |
313 | ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) | | |
314 | ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY); | |
315 | ||
316 | stm32_rtc_wpr_unlock(rtc); | |
317 | ||
318 | ret = stm32_rtc_enter_init_mode(rtc); | |
319 | if (ret) { | |
320 | dev_err(dev, "Can't enter in init mode. Set time aborted.\n"); | |
321 | goto end; | |
322 | } | |
323 | ||
02b0cc34 AD |
324 | writel_relaxed(tr, rtc->base + regs->tr); |
325 | writel_relaxed(dr, rtc->base + regs->dr); | |
4e64350f AD |
326 | |
327 | stm32_rtc_exit_init_mode(rtc); | |
328 | ||
329 | ret = stm32_rtc_wait_sync(rtc); | |
330 | end: | |
331 | stm32_rtc_wpr_lock(rtc); | |
332 | ||
333 | return ret; | |
334 | } | |
335 | ||
336 | static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
337 | { | |
338 | struct stm32_rtc *rtc = dev_get_drvdata(dev); | |
02b0cc34 AD |
339 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
340 | const struct stm32_rtc_events *evts = &rtc->data->events; | |
4e64350f | 341 | struct rtc_time *tm = &alrm->time; |
02b0cc34 | 342 | unsigned int alrmar, cr, status; |
4e64350f | 343 | |
02b0cc34 AD |
344 | alrmar = readl_relaxed(rtc->base + regs->alrmar); |
345 | cr = readl_relaxed(rtc->base + regs->cr); | |
b72252b6 | 346 | status = readl_relaxed(rtc->base + regs->sr); |
4e64350f AD |
347 | |
348 | if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) { | |
349 | /* | |
350 | * Date/day doesn't matter in Alarm comparison so alarm | |
351 | * triggers every day | |
352 | */ | |
353 | tm->tm_mday = -1; | |
354 | tm->tm_wday = -1; | |
355 | } else { | |
356 | if (alrmar & STM32_RTC_ALRMXR_WDSEL) { | |
357 | /* Alarm is set to a day of week */ | |
358 | tm->tm_mday = -1; | |
359 | tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >> | |
360 | STM32_RTC_ALRMXR_WDAY_SHIFT; | |
361 | tm->tm_wday %= 7; | |
362 | } else { | |
363 | /* Alarm is set to a day of month */ | |
364 | tm->tm_wday = -1; | |
365 | tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >> | |
366 | STM32_RTC_ALRMXR_DATE_SHIFT; | |
367 | } | |
368 | } | |
369 | ||
370 | if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) { | |
371 | /* Hours don't matter in Alarm comparison */ | |
372 | tm->tm_hour = -1; | |
373 | } else { | |
374 | tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >> | |
375 | STM32_RTC_ALRMXR_HOUR_SHIFT; | |
376 | if (alrmar & STM32_RTC_ALRMXR_PM) | |
377 | tm->tm_hour += 12; | |
378 | } | |
379 | ||
380 | if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) { | |
381 | /* Minutes don't matter in Alarm comparison */ | |
382 | tm->tm_min = -1; | |
383 | } else { | |
384 | tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >> | |
385 | STM32_RTC_ALRMXR_MIN_SHIFT; | |
386 | } | |
387 | ||
388 | if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) { | |
389 | /* Seconds don't matter in Alarm comparison */ | |
390 | tm->tm_sec = -1; | |
391 | } else { | |
392 | tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >> | |
393 | STM32_RTC_ALRMXR_SEC_SHIFT; | |
394 | } | |
395 | ||
396 | bcd2tm(tm); | |
397 | ||
398 | alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0; | |
02b0cc34 | 399 | alrm->pending = (status & evts->alra) ? 1 : 0; |
4e64350f AD |
400 | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
405 | { | |
406 | struct stm32_rtc *rtc = dev_get_drvdata(dev); | |
02b0cc34 AD |
407 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
408 | const struct stm32_rtc_events *evts = &rtc->data->events; | |
409 | unsigned int cr; | |
4e64350f | 410 | |
02b0cc34 | 411 | cr = readl_relaxed(rtc->base + regs->cr); |
4e64350f AD |
412 | |
413 | stm32_rtc_wpr_unlock(rtc); | |
414 | ||
415 | /* We expose Alarm A to the kernel */ | |
416 | if (enabled) | |
417 | cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); | |
418 | else | |
419 | cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); | |
02b0cc34 | 420 | writel_relaxed(cr, rtc->base + regs->cr); |
4e64350f | 421 | |
02b0cc34 AD |
422 | /* Clear event flags, otherwise new events won't be received */ |
423 | stm32_rtc_clear_event_flags(rtc, evts->alra); | |
4e64350f AD |
424 | |
425 | stm32_rtc_wpr_lock(rtc); | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm) | |
431 | { | |
02b0cc34 | 432 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
1d70ba3b | 433 | int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec; |
02b0cc34 AD |
434 | unsigned int dr = readl_relaxed(rtc->base + regs->dr); |
435 | unsigned int tr = readl_relaxed(rtc->base + regs->tr); | |
4e64350f AD |
436 | |
437 | cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT; | |
438 | cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT; | |
439 | cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT; | |
440 | cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT; | |
441 | cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT; | |
442 | cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT; | |
443 | ||
444 | /* | |
445 | * Assuming current date is M-D-Y H:M:S. | |
446 | * RTC alarm can't be set on a specific month and year. | |
447 | * So the valid alarm range is: | |
448 | * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S | |
449 | * with a specific case for December... | |
450 | */ | |
451 | if ((((tm->tm_year > cur_year) && | |
452 | (tm->tm_mon == 0x1) && (cur_mon == 0x12)) || | |
453 | ((tm->tm_year == cur_year) && | |
454 | (tm->tm_mon <= cur_mon + 1))) && | |
455 | ((tm->tm_mday > cur_day) || | |
456 | ((tm->tm_mday == cur_day) && | |
457 | ((tm->tm_hour > cur_hour) || | |
458 | ((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) || | |
459 | ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) && | |
460 | (tm->tm_sec >= cur_sec)))))) | |
461 | return 0; | |
462 | ||
463 | return -EINVAL; | |
464 | } | |
465 | ||
466 | static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
467 | { | |
468 | struct stm32_rtc *rtc = dev_get_drvdata(dev); | |
02b0cc34 | 469 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
4e64350f AD |
470 | struct rtc_time *tm = &alrm->time; |
471 | unsigned int cr, isr, alrmar; | |
472 | int ret = 0; | |
473 | ||
474 | tm2bcd(tm); | |
475 | ||
476 | /* | |
477 | * RTC alarm can't be set on a specific date, unless this date is | |
478 | * up to the same day of month next month. | |
479 | */ | |
480 | if (stm32_rtc_valid_alrm(rtc, tm) < 0) { | |
481 | dev_err(dev, "Alarm can be set only on upcoming month.\n"); | |
482 | return -EINVAL; | |
483 | } | |
484 | ||
485 | alrmar = 0; | |
486 | /* tm_year and tm_mon are not used because not supported by RTC */ | |
487 | alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) & | |
488 | STM32_RTC_ALRMXR_DATE; | |
489 | /* 24-hour format */ | |
490 | alrmar &= ~STM32_RTC_ALRMXR_PM; | |
491 | alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) & | |
492 | STM32_RTC_ALRMXR_HOUR; | |
493 | alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) & | |
494 | STM32_RTC_ALRMXR_MIN; | |
495 | alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) & | |
496 | STM32_RTC_ALRMXR_SEC; | |
497 | ||
498 | stm32_rtc_wpr_unlock(rtc); | |
499 | ||
500 | /* Disable Alarm */ | |
02b0cc34 | 501 | cr = readl_relaxed(rtc->base + regs->cr); |
4e64350f | 502 | cr &= ~STM32_RTC_CR_ALRAE; |
02b0cc34 | 503 | writel_relaxed(cr, rtc->base + regs->cr); |
4e64350f AD |
504 | |
505 | /* | |
506 | * Poll Alarm write flag to be sure that Alarm update is allowed: it | |
9a6757ea | 507 | * takes around 2 rtc_ck clock cycles |
4e64350f | 508 | */ |
02b0cc34 | 509 | ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, |
4e64350f AD |
510 | isr, |
511 | (isr & STM32_RTC_ISR_ALRAWF), | |
512 | 10, 100000); | |
513 | ||
514 | if (ret) { | |
515 | dev_err(dev, "Alarm update not allowed\n"); | |
516 | goto end; | |
517 | } | |
518 | ||
519 | /* Write to Alarm register */ | |
02b0cc34 | 520 | writel_relaxed(alrmar, rtc->base + regs->alrmar); |
4e64350f | 521 | |
fe63604c | 522 | stm32_rtc_alarm_irq_enable(dev, alrm->enabled); |
4e64350f AD |
523 | end: |
524 | stm32_rtc_wpr_lock(rtc); | |
525 | ||
526 | return ret; | |
527 | } | |
528 | ||
529 | static const struct rtc_class_ops stm32_rtc_ops = { | |
530 | .read_time = stm32_rtc_read_time, | |
531 | .set_time = stm32_rtc_set_time, | |
532 | .read_alarm = stm32_rtc_read_alarm, | |
533 | .set_alarm = stm32_rtc_set_alarm, | |
534 | .alarm_irq_enable = stm32_rtc_alarm_irq_enable, | |
535 | }; | |
536 | ||
02b0cc34 AD |
537 | static void stm32_rtc_clear_events(struct stm32_rtc *rtc, |
538 | unsigned int flags) | |
539 | { | |
540 | const struct stm32_rtc_registers *regs = &rtc->data->regs; | |
541 | ||
542 | /* Flags are cleared by writing 0 in RTC_ISR */ | |
543 | writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags, | |
544 | rtc->base + regs->isr); | |
545 | } | |
546 | ||
9a6757ea AD |
547 | static const struct stm32_rtc_data stm32_rtc_data = { |
548 | .has_pclk = false, | |
22cb47c1 | 549 | .need_dbp = true, |
b72252b6 | 550 | .has_wakeirq = false, |
02b0cc34 AD |
551 | .regs = { |
552 | .tr = 0x00, | |
553 | .dr = 0x04, | |
554 | .cr = 0x08, | |
555 | .isr = 0x0C, | |
556 | .prer = 0x10, | |
557 | .alrmar = 0x1C, | |
558 | .wpr = 0x24, | |
b72252b6 AD |
559 | .sr = 0x0C, /* set to ISR offset to ease alarm management */ |
560 | .scr = UNDEF_REG, | |
561 | .verr = UNDEF_REG, | |
02b0cc34 AD |
562 | }, |
563 | .events = { | |
564 | .alra = STM32_RTC_ISR_ALRAF, | |
565 | }, | |
566 | .clear_events = stm32_rtc_clear_events, | |
9a6757ea AD |
567 | }; |
568 | ||
569 | static const struct stm32_rtc_data stm32h7_rtc_data = { | |
570 | .has_pclk = true, | |
22cb47c1 | 571 | .need_dbp = true, |
b72252b6 | 572 | .has_wakeirq = false, |
02b0cc34 AD |
573 | .regs = { |
574 | .tr = 0x00, | |
575 | .dr = 0x04, | |
576 | .cr = 0x08, | |
577 | .isr = 0x0C, | |
578 | .prer = 0x10, | |
579 | .alrmar = 0x1C, | |
580 | .wpr = 0x24, | |
b72252b6 AD |
581 | .sr = 0x0C, /* set to ISR offset to ease alarm management */ |
582 | .scr = UNDEF_REG, | |
583 | .verr = UNDEF_REG, | |
02b0cc34 AD |
584 | }, |
585 | .events = { | |
586 | .alra = STM32_RTC_ISR_ALRAF, | |
587 | }, | |
588 | .clear_events = stm32_rtc_clear_events, | |
9a6757ea AD |
589 | }; |
590 | ||
b72252b6 AD |
591 | static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc, |
592 | unsigned int flags) | |
593 | { | |
594 | struct stm32_rtc_registers regs = rtc->data->regs; | |
595 | ||
596 | /* Flags are cleared by writing 1 in RTC_SCR */ | |
597 | writel_relaxed(flags, rtc->base + regs.scr); | |
598 | } | |
599 | ||
600 | static const struct stm32_rtc_data stm32mp1_data = { | |
601 | .has_pclk = true, | |
602 | .need_dbp = false, | |
603 | .has_wakeirq = true, | |
604 | .regs = { | |
605 | .tr = 0x00, | |
606 | .dr = 0x04, | |
607 | .cr = 0x18, | |
608 | .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */ | |
609 | .prer = 0x10, | |
610 | .alrmar = 0x40, | |
611 | .wpr = 0x24, | |
612 | .sr = 0x50, | |
613 | .scr = 0x5C, | |
614 | .verr = 0x3F4, | |
615 | }, | |
616 | .events = { | |
617 | .alra = STM32_RTC_SR_ALRA, | |
618 | }, | |
619 | .clear_events = stm32mp1_rtc_clear_events, | |
620 | }; | |
621 | ||
4e64350f | 622 | static const struct of_device_id stm32_rtc_of_match[] = { |
9a6757ea AD |
623 | { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data }, |
624 | { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data }, | |
b72252b6 | 625 | { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data }, |
4e64350f AD |
626 | {} |
627 | }; | |
628 | MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); | |
4e64350f AD |
629 | |
630 | static int stm32_rtc_init(struct platform_device *pdev, | |
631 | struct stm32_rtc *rtc) | |
632 | { | |
02b0cc34 | 633 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
4e64350f AD |
634 | unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr; |
635 | unsigned int rate; | |
636 | int ret = 0; | |
637 | ||
9a6757ea | 638 | rate = clk_get_rate(rtc->rtc_ck); |
4e64350f AD |
639 | |
640 | /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */ | |
641 | pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT; | |
642 | pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT; | |
643 | ||
1d70ba3b | 644 | for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) { |
4e64350f AD |
645 | pred_s = (rate / (pred_a + 1)) - 1; |
646 | ||
647 | if (((pred_s + 1) * (pred_a + 1)) == rate) | |
648 | break; | |
649 | } | |
650 | ||
651 | /* | |
652 | * Can't find a 1Hz, so give priority to RTC power consumption | |
653 | * by choosing the higher possible value for prediv_a | |
654 | */ | |
655 | if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) { | |
656 | pred_a = pred_a_max; | |
657 | pred_s = (rate / (pred_a + 1)) - 1; | |
658 | ||
9a6757ea | 659 | dev_warn(&pdev->dev, "rtc_ck is %s\n", |
1d70ba3b | 660 | (rate < ((pred_a + 1) * (pred_s + 1))) ? |
4e64350f AD |
661 | "fast" : "slow"); |
662 | } | |
663 | ||
664 | stm32_rtc_wpr_unlock(rtc); | |
665 | ||
666 | ret = stm32_rtc_enter_init_mode(rtc); | |
667 | if (ret) { | |
668 | dev_err(&pdev->dev, | |
669 | "Can't enter in init mode. Prescaler config failed.\n"); | |
670 | goto end; | |
671 | } | |
672 | ||
673 | prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S; | |
02b0cc34 | 674 | writel_relaxed(prer, rtc->base + regs->prer); |
4e64350f | 675 | prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A; |
02b0cc34 | 676 | writel_relaxed(prer, rtc->base + regs->prer); |
4e64350f AD |
677 | |
678 | /* Force 24h time format */ | |
02b0cc34 | 679 | cr = readl_relaxed(rtc->base + regs->cr); |
4e64350f | 680 | cr &= ~STM32_RTC_CR_FMT; |
02b0cc34 | 681 | writel_relaxed(cr, rtc->base + regs->cr); |
4e64350f AD |
682 | |
683 | stm32_rtc_exit_init_mode(rtc); | |
684 | ||
685 | ret = stm32_rtc_wait_sync(rtc); | |
686 | end: | |
687 | stm32_rtc_wpr_lock(rtc); | |
688 | ||
689 | return ret; | |
690 | } | |
691 | ||
692 | static int stm32_rtc_probe(struct platform_device *pdev) | |
693 | { | |
694 | struct stm32_rtc *rtc; | |
02b0cc34 | 695 | const struct stm32_rtc_registers *regs; |
4e64350f AD |
696 | int ret; |
697 | ||
698 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); | |
699 | if (!rtc) | |
700 | return -ENOMEM; | |
701 | ||
09ef18bc | 702 | rtc->base = devm_platform_ioremap_resource(pdev, 0); |
4e64350f AD |
703 | if (IS_ERR(rtc->base)) |
704 | return PTR_ERR(rtc->base); | |
705 | ||
22cb47c1 AD |
706 | rtc->data = (struct stm32_rtc_data *) |
707 | of_device_get_match_data(&pdev->dev); | |
02b0cc34 | 708 | regs = &rtc->data->regs; |
22cb47c1 AD |
709 | |
710 | if (rtc->data->need_dbp) { | |
711 | rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
712 | "st,syscfg"); | |
713 | if (IS_ERR(rtc->dbp)) { | |
714 | dev_err(&pdev->dev, "no st,syscfg\n"); | |
715 | return PTR_ERR(rtc->dbp); | |
716 | } | |
4e64350f | 717 | |
22cb47c1 AD |
718 | ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", |
719 | 1, &rtc->dbp_reg); | |
720 | if (ret) { | |
721 | dev_err(&pdev->dev, "can't read DBP register offset\n"); | |
722 | return ret; | |
723 | } | |
724 | ||
725 | ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", | |
726 | 2, &rtc->dbp_mask); | |
727 | if (ret) { | |
728 | dev_err(&pdev->dev, "can't read DBP register mask\n"); | |
729 | return ret; | |
730 | } | |
731 | } | |
9a6757ea AD |
732 | |
733 | if (!rtc->data->has_pclk) { | |
734 | rtc->pclk = NULL; | |
735 | rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL); | |
736 | } else { | |
737 | rtc->pclk = devm_clk_get(&pdev->dev, "pclk"); | |
738 | if (IS_ERR(rtc->pclk)) { | |
739 | dev_err(&pdev->dev, "no pclk clock"); | |
740 | return PTR_ERR(rtc->pclk); | |
741 | } | |
742 | rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck"); | |
743 | } | |
744 | if (IS_ERR(rtc->rtc_ck)) { | |
745 | dev_err(&pdev->dev, "no rtc_ck clock"); | |
746 | return PTR_ERR(rtc->rtc_ck); | |
747 | } | |
748 | ||
749 | if (rtc->data->has_pclk) { | |
750 | ret = clk_prepare_enable(rtc->pclk); | |
751 | if (ret) | |
752 | return ret; | |
4e64350f AD |
753 | } |
754 | ||
9a6757ea | 755 | ret = clk_prepare_enable(rtc->rtc_ck); |
4e64350f | 756 | if (ret) |
950ac33d | 757 | goto err_no_rtc_ck; |
4e64350f | 758 | |
22cb47c1 AD |
759 | if (rtc->data->need_dbp) |
760 | regmap_update_bits(rtc->dbp, rtc->dbp_reg, | |
761 | rtc->dbp_mask, rtc->dbp_mask); | |
4e64350f AD |
762 | |
763 | /* | |
764 | * After a system reset, RTC_ISR.INITS flag can be read to check if | |
819cbde5 | 765 | * the calendar has been initialized or not. INITS flag is reset by a |
4e64350f | 766 | * power-on reset (no vbat, no power-supply). It is not reset if |
9a6757ea | 767 | * rtc_ck parent clock has changed (so RTC prescalers need to be |
4e64350f AD |
768 | * changed). That's why we cannot rely on this flag to know if RTC |
769 | * init has to be done. | |
770 | */ | |
771 | ret = stm32_rtc_init(pdev, rtc); | |
772 | if (ret) | |
773 | goto err; | |
774 | ||
775 | rtc->irq_alarm = platform_get_irq(pdev, 0); | |
776 | if (rtc->irq_alarm <= 0) { | |
4e64350f AD |
777 | ret = rtc->irq_alarm; |
778 | goto err; | |
779 | } | |
780 | ||
4e64350f | 781 | ret = device_init_wakeup(&pdev->dev, true); |
b72252b6 AD |
782 | if (rtc->data->has_wakeirq) { |
783 | rtc->wakeirq_alarm = platform_get_irq(pdev, 1); | |
cf612c59 | 784 | if (rtc->wakeirq_alarm > 0) { |
b72252b6 AD |
785 | ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, |
786 | rtc->wakeirq_alarm); | |
cf612c59 FD |
787 | } else { |
788 | ret = rtc->wakeirq_alarm; | |
789 | if (rtc->wakeirq_alarm == -EPROBE_DEFER) | |
790 | goto err; | |
791 | } | |
b72252b6 | 792 | } |
4e64350f | 793 | if (ret) |
b72252b6 AD |
794 | dev_warn(&pdev->dev, "alarm can't wake up the system: %d", ret); |
795 | ||
796 | platform_set_drvdata(pdev, rtc); | |
4e64350f AD |
797 | |
798 | rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name, | |
819cbde5 | 799 | &stm32_rtc_ops, THIS_MODULE); |
4e64350f AD |
800 | if (IS_ERR(rtc->rtc_dev)) { |
801 | ret = PTR_ERR(rtc->rtc_dev); | |
802 | dev_err(&pdev->dev, "rtc device registration failed, err=%d\n", | |
803 | ret); | |
804 | goto err; | |
805 | } | |
806 | ||
807 | /* Handle RTC alarm interrupts */ | |
808 | ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL, | |
d213217d | 809 | stm32_rtc_alarm_irq, IRQF_ONESHOT, |
4e64350f AD |
810 | pdev->name, rtc); |
811 | if (ret) { | |
812 | dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n", | |
813 | rtc->irq_alarm); | |
814 | goto err; | |
815 | } | |
816 | ||
817 | /* | |
818 | * If INITS flag is reset (calendar year field set to 0x00), calendar | |
819 | * must be initialized | |
820 | */ | |
02b0cc34 | 821 | if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS)) |
4e64350f AD |
822 | dev_warn(&pdev->dev, "Date/Time must be initialized\n"); |
823 | ||
b72252b6 AD |
824 | if (regs->verr != UNDEF_REG) { |
825 | u32 ver = readl_relaxed(rtc->base + regs->verr); | |
826 | ||
827 | dev_info(&pdev->dev, "registered rev:%d.%d\n", | |
828 | (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF, | |
829 | (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF); | |
830 | } | |
831 | ||
4e64350f | 832 | return 0; |
950ac33d | 833 | |
4e64350f | 834 | err: |
950ac33d MF |
835 | clk_disable_unprepare(rtc->rtc_ck); |
836 | err_no_rtc_ck: | |
9a6757ea AD |
837 | if (rtc->data->has_pclk) |
838 | clk_disable_unprepare(rtc->pclk); | |
4e64350f | 839 | |
22cb47c1 AD |
840 | if (rtc->data->need_dbp) |
841 | regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); | |
4e64350f | 842 | |
b72252b6 | 843 | dev_pm_clear_wake_irq(&pdev->dev); |
4e64350f AD |
844 | device_init_wakeup(&pdev->dev, false); |
845 | ||
846 | return ret; | |
847 | } | |
848 | ||
54c2cb27 | 849 | static void stm32_rtc_remove(struct platform_device *pdev) |
4e64350f AD |
850 | { |
851 | struct stm32_rtc *rtc = platform_get_drvdata(pdev); | |
02b0cc34 | 852 | const struct stm32_rtc_registers *regs = &rtc->data->regs; |
4e64350f AD |
853 | unsigned int cr; |
854 | ||
855 | /* Disable interrupts */ | |
856 | stm32_rtc_wpr_unlock(rtc); | |
02b0cc34 | 857 | cr = readl_relaxed(rtc->base + regs->cr); |
4e64350f | 858 | cr &= ~STM32_RTC_CR_ALRAIE; |
02b0cc34 | 859 | writel_relaxed(cr, rtc->base + regs->cr); |
4e64350f AD |
860 | stm32_rtc_wpr_lock(rtc); |
861 | ||
9a6757ea AD |
862 | clk_disable_unprepare(rtc->rtc_ck); |
863 | if (rtc->data->has_pclk) | |
864 | clk_disable_unprepare(rtc->pclk); | |
4e64350f | 865 | |
22cb47c1 AD |
866 | /* Enable backup domain write protection if needed */ |
867 | if (rtc->data->need_dbp) | |
868 | regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); | |
4e64350f | 869 | |
b72252b6 | 870 | dev_pm_clear_wake_irq(&pdev->dev); |
4e64350f | 871 | device_init_wakeup(&pdev->dev, false); |
4e64350f AD |
872 | } |
873 | ||
874 | #ifdef CONFIG_PM_SLEEP | |
875 | static int stm32_rtc_suspend(struct device *dev) | |
876 | { | |
877 | struct stm32_rtc *rtc = dev_get_drvdata(dev); | |
878 | ||
9a6757ea AD |
879 | if (rtc->data->has_pclk) |
880 | clk_disable_unprepare(rtc->pclk); | |
881 | ||
4e64350f AD |
882 | if (device_may_wakeup(dev)) |
883 | return enable_irq_wake(rtc->irq_alarm); | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | static int stm32_rtc_resume(struct device *dev) | |
889 | { | |
890 | struct stm32_rtc *rtc = dev_get_drvdata(dev); | |
891 | int ret = 0; | |
892 | ||
9a6757ea AD |
893 | if (rtc->data->has_pclk) { |
894 | ret = clk_prepare_enable(rtc->pclk); | |
895 | if (ret) | |
896 | return ret; | |
897 | } | |
898 | ||
4e64350f | 899 | ret = stm32_rtc_wait_sync(rtc); |
cf33e911 CY |
900 | if (ret < 0) { |
901 | if (rtc->data->has_pclk) | |
902 | clk_disable_unprepare(rtc->pclk); | |
4e64350f | 903 | return ret; |
cf33e911 | 904 | } |
4e64350f AD |
905 | |
906 | if (device_may_wakeup(dev)) | |
907 | return disable_irq_wake(rtc->irq_alarm); | |
908 | ||
909 | return ret; | |
910 | } | |
911 | #endif | |
912 | ||
913 | static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops, | |
914 | stm32_rtc_suspend, stm32_rtc_resume); | |
915 | ||
916 | static struct platform_driver stm32_rtc_driver = { | |
917 | .probe = stm32_rtc_probe, | |
54c2cb27 | 918 | .remove_new = stm32_rtc_remove, |
4e64350f AD |
919 | .driver = { |
920 | .name = DRIVER_NAME, | |
921 | .pm = &stm32_rtc_pm_ops, | |
922 | .of_match_table = stm32_rtc_of_match, | |
923 | }, | |
924 | }; | |
925 | ||
926 | module_platform_driver(stm32_rtc_driver); | |
927 | ||
928 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
929 | MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); | |
930 | MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver"); | |
931 | MODULE_LICENSE("GPL v2"); |