Commit | Line | Data |
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179a502f SG |
1 | /* |
2 | * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_device.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/rtc.h> | |
7f899399 | 20 | #include <linux/clk.h> |
d482893b FL |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/regmap.h> | |
23 | ||
24 | #define SNVS_LPREGISTER_OFFSET 0x34 | |
179a502f SG |
25 | |
26 | /* These register offsets are relative to LP (Low Power) range */ | |
27 | #define SNVS_LPCR 0x04 | |
28 | #define SNVS_LPSR 0x18 | |
29 | #define SNVS_LPSRTCMR 0x1c | |
30 | #define SNVS_LPSRTCLR 0x20 | |
31 | #define SNVS_LPTAR 0x24 | |
32 | #define SNVS_LPPGDR 0x30 | |
33 | ||
34 | #define SNVS_LPCR_SRTC_ENV (1 << 0) | |
35 | #define SNVS_LPCR_LPTA_EN (1 << 1) | |
36 | #define SNVS_LPCR_LPWUI_EN (1 << 3) | |
37 | #define SNVS_LPSR_LPTA (1 << 0) | |
38 | ||
39 | #define SNVS_LPPGDR_INIT 0x41736166 | |
40 | #define CNTR_TO_SECS_SH 15 | |
41 | ||
42 | struct snvs_rtc_data { | |
43 | struct rtc_device *rtc; | |
d482893b FL |
44 | struct regmap *regmap; |
45 | int offset; | |
179a502f | 46 | int irq; |
7f899399 | 47 | struct clk *clk; |
179a502f SG |
48 | }; |
49 | ||
d482893b | 50 | static u32 rtc_read_lp_counter(struct snvs_rtc_data *data) |
179a502f SG |
51 | { |
52 | u64 read1, read2; | |
d482893b | 53 | u32 val; |
179a502f SG |
54 | |
55 | do { | |
d482893b FL |
56 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val); |
57 | read1 = val; | |
179a502f | 58 | read1 <<= 32; |
d482893b FL |
59 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val); |
60 | read1 |= val; | |
179a502f | 61 | |
d482893b FL |
62 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val); |
63 | read2 = val; | |
179a502f | 64 | read2 <<= 32; |
d482893b FL |
65 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val); |
66 | read2 |= val; | |
179a502f SG |
67 | } while (read1 != read2); |
68 | ||
69 | /* Convert 47-bit counter to 32-bit raw second count */ | |
70 | return (u32) (read1 >> CNTR_TO_SECS_SH); | |
71 | } | |
72 | ||
d482893b | 73 | static void rtc_write_sync_lp(struct snvs_rtc_data *data) |
179a502f SG |
74 | { |
75 | u32 count1, count2, count3; | |
76 | int i; | |
77 | ||
78 | /* Wait for 3 CKIL cycles */ | |
79 | for (i = 0; i < 3; i++) { | |
80 | do { | |
d482893b FL |
81 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); |
82 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2); | |
179a502f SG |
83 | } while (count1 != count2); |
84 | ||
85 | /* Now wait until counter value changes */ | |
86 | do { | |
87 | do { | |
d482893b FL |
88 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2); |
89 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3); | |
179a502f SG |
90 | } while (count2 != count3); |
91 | } while (count3 == count1); | |
92 | } | |
93 | } | |
94 | ||
95 | static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable) | |
96 | { | |
179a502f SG |
97 | int timeout = 1000; |
98 | u32 lpcr; | |
99 | ||
d482893b FL |
100 | regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV, |
101 | enable ? SNVS_LPCR_SRTC_ENV : 0); | |
179a502f SG |
102 | |
103 | while (--timeout) { | |
d482893b | 104 | regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); |
179a502f SG |
105 | |
106 | if (enable) { | |
107 | if (lpcr & SNVS_LPCR_SRTC_ENV) | |
108 | break; | |
109 | } else { | |
110 | if (!(lpcr & SNVS_LPCR_SRTC_ENV)) | |
111 | break; | |
112 | } | |
113 | } | |
114 | ||
115 | if (!timeout) | |
116 | return -ETIMEDOUT; | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
122 | { | |
123 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
d482893b | 124 | unsigned long time = rtc_read_lp_counter(data); |
179a502f SG |
125 | |
126 | rtc_time_to_tm(time, tm); | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
131 | static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
132 | { | |
133 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
134 | unsigned long time; | |
135 | ||
136 | rtc_tm_to_time(tm, &time); | |
137 | ||
138 | /* Disable RTC first */ | |
139 | snvs_rtc_enable(data, false); | |
140 | ||
141 | /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */ | |
d482893b FL |
142 | regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH); |
143 | regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH)); | |
179a502f SG |
144 | |
145 | /* Enable RTC again */ | |
146 | snvs_rtc_enable(data, true); | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
152 | { | |
153 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
154 | u32 lptar, lpsr; | |
155 | ||
d482893b | 156 | regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar); |
179a502f SG |
157 | rtc_time_to_tm(lptar, &alrm->time); |
158 | ||
d482893b | 159 | regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); |
179a502f SG |
160 | alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0; |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) | |
166 | { | |
167 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
179a502f | 168 | |
d482893b FL |
169 | regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, |
170 | (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN), | |
171 | enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0); | |
179a502f | 172 | |
d482893b | 173 | rtc_write_sync_lp(data); |
179a502f SG |
174 | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
179 | { | |
180 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
181 | struct rtc_time *alrm_tm = &alrm->time; | |
182 | unsigned long time; | |
179a502f SG |
183 | |
184 | rtc_tm_to_time(alrm_tm, &time); | |
185 | ||
d482893b | 186 | regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0); |
7bb633b1 | 187 | rtc_write_sync_lp(data); |
d482893b | 188 | regmap_write(data->regmap, data->offset + SNVS_LPTAR, time); |
179a502f SG |
189 | |
190 | /* Clear alarm interrupt status bit */ | |
d482893b | 191 | regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA); |
179a502f SG |
192 | |
193 | return snvs_rtc_alarm_irq_enable(dev, alrm->enabled); | |
194 | } | |
195 | ||
196 | static const struct rtc_class_ops snvs_rtc_ops = { | |
197 | .read_time = snvs_rtc_read_time, | |
198 | .set_time = snvs_rtc_set_time, | |
199 | .read_alarm = snvs_rtc_read_alarm, | |
200 | .set_alarm = snvs_rtc_set_alarm, | |
201 | .alarm_irq_enable = snvs_rtc_alarm_irq_enable, | |
202 | }; | |
203 | ||
204 | static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id) | |
205 | { | |
206 | struct device *dev = dev_id; | |
207 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
208 | u32 lpsr; | |
209 | u32 events = 0; | |
210 | ||
d482893b | 211 | regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); |
179a502f SG |
212 | |
213 | if (lpsr & SNVS_LPSR_LPTA) { | |
214 | events |= (RTC_AF | RTC_IRQF); | |
215 | ||
216 | /* RTC alarm should be one-shot */ | |
217 | snvs_rtc_alarm_irq_enable(dev, 0); | |
218 | ||
219 | rtc_update_irq(data->rtc, 1, events); | |
220 | } | |
221 | ||
222 | /* clear interrupt status */ | |
d482893b | 223 | regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr); |
179a502f SG |
224 | |
225 | return events ? IRQ_HANDLED : IRQ_NONE; | |
226 | } | |
227 | ||
d482893b FL |
228 | static const struct regmap_config snvs_rtc_config = { |
229 | .reg_bits = 32, | |
230 | .val_bits = 32, | |
231 | .reg_stride = 4, | |
232 | }; | |
233 | ||
5a167f45 | 234 | static int snvs_rtc_probe(struct platform_device *pdev) |
179a502f SG |
235 | { |
236 | struct snvs_rtc_data *data; | |
237 | struct resource *res; | |
238 | int ret; | |
d482893b | 239 | void __iomem *mmio; |
179a502f SG |
240 | |
241 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); | |
242 | if (!data) | |
243 | return -ENOMEM; | |
244 | ||
d482893b FL |
245 | data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap"); |
246 | ||
247 | if (IS_ERR(data->regmap)) { | |
248 | dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n"); | |
249 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
250 | ||
251 | mmio = devm_ioremap_resource(&pdev->dev, res); | |
252 | if (IS_ERR(mmio)) | |
253 | return PTR_ERR(mmio); | |
254 | ||
255 | data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config); | |
256 | } else { | |
257 | data->offset = SNVS_LPREGISTER_OFFSET; | |
258 | of_property_read_u32(pdev->dev.of_node, "offset", &data->offset); | |
259 | } | |
260 | ||
75892900 | 261 | if (IS_ERR(data->regmap)) { |
d482893b FL |
262 | dev_err(&pdev->dev, "Can't find snvs syscon\n"); |
263 | return -ENODEV; | |
264 | } | |
179a502f SG |
265 | |
266 | data->irq = platform_get_irq(pdev, 0); | |
267 | if (data->irq < 0) | |
268 | return data->irq; | |
269 | ||
7f899399 SM |
270 | data->clk = devm_clk_get(&pdev->dev, "snvs-rtc"); |
271 | if (IS_ERR(data->clk)) { | |
272 | data->clk = NULL; | |
273 | } else { | |
274 | ret = clk_prepare_enable(data->clk); | |
275 | if (ret) { | |
276 | dev_err(&pdev->dev, | |
277 | "Could not prepare or enable the snvs clock\n"); | |
278 | return ret; | |
279 | } | |
280 | } | |
281 | ||
179a502f SG |
282 | platform_set_drvdata(pdev, data); |
283 | ||
179a502f | 284 | /* Initialize glitch detect */ |
d482893b | 285 | regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT); |
179a502f SG |
286 | |
287 | /* Clear interrupt status */ | |
d482893b | 288 | regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff); |
179a502f SG |
289 | |
290 | /* Enable RTC */ | |
291 | snvs_rtc_enable(data, true); | |
292 | ||
293 | device_init_wakeup(&pdev->dev, true); | |
294 | ||
295 | ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler, | |
296 | IRQF_SHARED, "rtc alarm", &pdev->dev); | |
297 | if (ret) { | |
298 | dev_err(&pdev->dev, "failed to request irq %d: %d\n", | |
299 | data->irq, ret); | |
7f899399 | 300 | goto error_rtc_device_register; |
179a502f SG |
301 | } |
302 | ||
904784c1 | 303 | data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
179a502f SG |
304 | &snvs_rtc_ops, THIS_MODULE); |
305 | if (IS_ERR(data->rtc)) { | |
306 | ret = PTR_ERR(data->rtc); | |
307 | dev_err(&pdev->dev, "failed to register rtc: %d\n", ret); | |
7f899399 | 308 | goto error_rtc_device_register; |
179a502f SG |
309 | } |
310 | ||
311 | return 0; | |
7f899399 SM |
312 | |
313 | error_rtc_device_register: | |
314 | if (data->clk) | |
315 | clk_disable_unprepare(data->clk); | |
316 | ||
317 | return ret; | |
179a502f SG |
318 | } |
319 | ||
179a502f SG |
320 | #ifdef CONFIG_PM_SLEEP |
321 | static int snvs_rtc_suspend(struct device *dev) | |
322 | { | |
323 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
324 | ||
325 | if (device_may_wakeup(dev)) | |
a350259d | 326 | return enable_irq_wake(data->irq); |
179a502f | 327 | |
119434f4 SA |
328 | return 0; |
329 | } | |
330 | ||
331 | static int snvs_rtc_suspend_noirq(struct device *dev) | |
332 | { | |
333 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
334 | ||
7f899399 SM |
335 | if (data->clk) |
336 | clk_disable_unprepare(data->clk); | |
337 | ||
179a502f SG |
338 | return 0; |
339 | } | |
340 | ||
341 | static int snvs_rtc_resume(struct device *dev) | |
342 | { | |
343 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
344 | ||
345 | if (device_may_wakeup(dev)) | |
119434f4 | 346 | return disable_irq_wake(data->irq); |
179a502f | 347 | |
119434f4 SA |
348 | return 0; |
349 | } | |
350 | ||
351 | static int snvs_rtc_resume_noirq(struct device *dev) | |
352 | { | |
353 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
354 | ||
355 | if (data->clk) | |
356 | return clk_prepare_enable(data->clk); | |
7f899399 | 357 | |
179a502f SG |
358 | return 0; |
359 | } | |
179a502f | 360 | |
7654e9d4 | 361 | static const struct dev_pm_ops snvs_rtc_pm_ops = { |
119434f4 SA |
362 | .suspend = snvs_rtc_suspend, |
363 | .suspend_noirq = snvs_rtc_suspend_noirq, | |
364 | .resume = snvs_rtc_resume, | |
365 | .resume_noirq = snvs_rtc_resume_noirq, | |
7654e9d4 | 366 | }; |
179a502f | 367 | |
88221c32 GR |
368 | #define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops) |
369 | ||
370 | #else | |
371 | ||
372 | #define SNVS_RTC_PM_OPS NULL | |
373 | ||
374 | #endif | |
375 | ||
5a167f45 | 376 | static const struct of_device_id snvs_dt_ids[] = { |
179a502f SG |
377 | { .compatible = "fsl,sec-v4.0-mon-rtc-lp", }, |
378 | { /* sentinel */ } | |
379 | }; | |
380 | MODULE_DEVICE_TABLE(of, snvs_dt_ids); | |
381 | ||
382 | static struct platform_driver snvs_rtc_driver = { | |
383 | .driver = { | |
384 | .name = "snvs_rtc", | |
88221c32 | 385 | .pm = SNVS_RTC_PM_OPS, |
c39b3717 | 386 | .of_match_table = snvs_dt_ids, |
179a502f SG |
387 | }, |
388 | .probe = snvs_rtc_probe, | |
179a502f SG |
389 | }; |
390 | module_platform_driver(snvs_rtc_driver); | |
391 | ||
392 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
393 | MODULE_DESCRIPTION("Freescale SNVS RTC Driver"); | |
394 | MODULE_LICENSE("GPL"); |