[linux-block.git] / drivers / rtc / rtc-snvs.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/rtc.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#define SNVS_LPREGISTER_OFFSET	0x34

/* These register offsets are relative to LP (Low Power) range */
#define SNVS_LPCR		0x04
#define SNVS_LPSR		0x18
#define SNVS_LPSRTCMR		0x1c
#define SNVS_LPSRTCLR		0x20
#define SNVS_LPTAR		0x24
#define SNVS_LPPGDR		0x30

#define SNVS_LPCR_SRTC_ENV	(1 << 0)
#define SNVS_LPCR_LPTA_EN	(1 << 1)
#define SNVS_LPCR_LPWUI_EN	(1 << 3)
#define SNVS_LPSR_LPTA		(1 << 0)

#define SNVS_LPPGDR_INIT	0x41736166
#define CNTR_TO_SECS_SH		15

/* The maximum RTC clock cycles that are allowed to pass between two
 * consecutive clock counter register reads. If the values are corrupted a
 * bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
 * we end at 10ms which should be enough for most cases. If it once takes
 * longer than expected we do a retry.
 */
#define MAX_RTC_READ_DIFF_CYCLES	320

struct snvs_rtc_data {
	struct rtc_device *rtc;
	struct regmap *regmap;
	int offset;
	int irq;
	struct clk *clk;
};

/* Read 64 bit timer register, which could be in inconsistent state */
static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
{
	u32 msb, lsb;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	return (u64)msb << 32 | lsb;
}

/* Read the secure real time counter, taking care to deal with the cases of the
 * counter updating while being read.
 */
static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
{
	u64 read1, read2;
	s64 diff;
	unsigned int timeout = 100;

	/* As expected, the registers might update between the read of the LSB
	 * reg and the MSB reg.  It's also possible that one register might be
	 * in partially modified state as well.
	 */
	read1 = rtc_read_lpsrt(data);
	do {
		read2 = read1;
		read1 = rtc_read_lpsrt(data);
		diff = read1 - read2;
	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
	if (!timeout)
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");

	/* Convert 47-bit counter to 32-bit raw second count */
	return (u32) (read1 >> CNTR_TO_SECS_SH);
}

/* Just read the lsb from the counter, dealing with inconsistent state */
static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
{
	u32 count1, count2;
	s32 diff;
	unsigned int timeout = 100;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	do {
		count2 = count1;
		regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
		diff = count1 - count2;
	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
		return -ETIMEDOUT;
	}

	*lsb = count1;
	return 0;
}

static int rtc_write_sync_lp(struct snvs_rtc_data *data)
{
	u32 count1, count2;
	u32 elapsed;
	unsigned int timeout = 1000;
	int ret;

	ret = rtc_read_lp_counter_lsb(data, &count1);
	if (ret)
		return ret;

	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	do {
		ret = rtc_read_lp_counter_lsb(data, &count2);
		if (ret)
			return ret;
		elapsed = count2 - count1; /* wrap around _is_ handled! */
	} while (elapsed < 3 && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
		return -ETIMEDOUT;
	}
	return 0;
}

static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
{
	int timeout = 1000;
	u32 lpcr;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
			   enable ? SNVS_LPCR_SRTC_ENV : 0);

	while (--timeout) {
		regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);

		if (enable) {
			if (lpcr & SNVS_LPCR_SRTC_ENV)
				break;
		} else {
			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
				break;
		}
	}

	if (!timeout)
		return -ETIMEDOUT;

	return 0;
}

static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time;
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	time = rtc_read_lp_counter(data);
	rtc_time64_to_tm(time, tm);

	clk_disable(data->clk);

	return 0;
}

static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time = rtc_tm_to_time64(tm);
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	/* Disable RTC first */
	ret = snvs_rtc_enable(data, false);
	if (ret)
		return ret;

	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));

	/* Enable RTC again */
	ret = snvs_rtc_enable(data, true);

	clk_disable(data->clk);

	return ret;
}

static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lptar, lpsr;
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
	rtc_time64_to_tm(lptar, &alrm->time);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;

	clk_disable(data->clk);

	return 0;
}

static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
			   (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
			   enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);

	ret = rtc_write_sync_lp(data);

	clk_disable(data->clk);

	return ret;
}

static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time = rtc_tm_to_time64(&alrm->time);
	int ret;

	ret = clk_enable(data->clk);
	if (ret)
		return ret;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
	ret = rtc_write_sync_lp(data);
	if (ret)
		return ret;
	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);

	/* Clear alarm interrupt status bit */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);

	clk_disable(data->clk);

	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
}

static const struct rtc_class_ops snvs_rtc_ops = {
	.read_time = snvs_rtc_read_time,
	.set_time = snvs_rtc_set_time,
	.read_alarm = snvs_rtc_read_alarm,
	.set_alarm = snvs_rtc_set_alarm,
	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
};

static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lpsr;
	u32 events = 0;

	clk_enable(data->clk);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);

	if (lpsr & SNVS_LPSR_LPTA) {
		events |= (RTC_AF | RTC_IRQF);

		/* RTC alarm should be one-shot */
		snvs_rtc_alarm_irq_enable(dev, 0);

		rtc_update_irq(data->rtc, 1, events);
	}

	/* clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);

	clk_disable(data->clk);

	return events ? IRQ_HANDLED : IRQ_NONE;
}

static const struct regmap_config snvs_rtc_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static void snvs_rtc_action(void *data)
{
	clk_disable_unprepare(data);
}

static int snvs_rtc_probe(struct platform_device *pdev)
{
	struct snvs_rtc_data *data;
	int ret;
	void __iomem *mmio;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(data->rtc))
		return PTR_ERR(data->rtc);

	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");

	if (IS_ERR(data->regmap)) {
		dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");

		mmio = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(mmio))
			return PTR_ERR(mmio);

		data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	} else {
		data->offset = SNVS_LPREGISTER_OFFSET;
		of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	}

	if (IS_ERR(data->regmap)) {
		dev_err(&pdev->dev, "Can't find snvs syscon\n");
		return -ENODEV;
	}

	data->irq = platform_get_irq(pdev, 0);
	if (data->irq < 0)
		return data->irq;

	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	if (IS_ERR(data->clk)) {
		data->clk = NULL;
	} else {
		ret = clk_prepare_enable(data->clk);
		if (ret) {
			dev_err(&pdev->dev,
				"Could not prepare or enable the snvs clock\n");
			return ret;
		}
	}

	ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, data);

	/* Initialize glitch detect */
	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);

	/* Clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);

	/* Enable RTC */
	ret = snvs_rtc_enable(data, true);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
		return ret;
	}

	device_init_wakeup(&pdev->dev, true);
	ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
	if (ret)
		dev_err(&pdev->dev, "failed to enable irq wake\n");

	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
			       IRQF_SHARED, "rtc alarm", &pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to request irq %d: %d\n",
			data->irq, ret);
		return ret;
	}

	data->rtc->ops = &snvs_rtc_ops;
	data->rtc->range_max = U32_MAX;

	return devm_rtc_register_device(data->rtc);
}

static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	clk_disable(data->clk);

	return 0;
}

static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (data->clk)
		return clk_enable(data->clk);

	return 0;
}

static const struct dev_pm_ops snvs_rtc_pm_ops = {
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
};

static const struct of_device_id snvs_dt_ids[] = {
	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, snvs_dt_ids);

static struct platform_driver snvs_rtc_driver = {
	.driver = {
		.name	= "snvs_rtc",
		.pm	= &snvs_rtc_pm_ops,
		.of_match_table = snvs_dt_ids,
	},
	.probe		= snvs_rtc_probe,
};
module_platform_driver(snvs_rtc_driver);

MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5874c7f1 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
179a502f SG	4
	5	#include <linux/init.h>
	6	#include <linux/io.h>
	7	#include <linux/kernel.h>
	8	#include <linux/module.h>
	9	#include <linux/of.h>
179a502f	10	#include <linux/platform_device.h>
e7afddb2	11	#include <linux/pm_wakeirq.h>
179a502f	12	#include <linux/rtc.h>
7f899399	13	#include <linux/clk.h>
d482893b FL	14	#include <linux/mfd/syscon.h>
	15	#include <linux/regmap.h>
	16
	17	#define SNVS_LPREGISTER_OFFSET 0x34
179a502f SG	18
	19	/* These register offsets are relative to LP (Low Power) range */
	20	#define SNVS_LPCR 0x04
	21	#define SNVS_LPSR 0x18
	22	#define SNVS_LPSRTCMR 0x1c
	23	#define SNVS_LPSRTCLR 0x20
	24	#define SNVS_LPTAR 0x24
	25	#define SNVS_LPPGDR 0x30
	26
	27	#define SNVS_LPCR_SRTC_ENV (1 << 0)
	28	#define SNVS_LPCR_LPTA_EN (1 << 1)
	29	#define SNVS_LPCR_LPWUI_EN (1 << 3)
	30	#define SNVS_LPSR_LPTA (1 << 0)
	31
	32	#define SNVS_LPPGDR_INIT 0x41736166
	33	#define CNTR_TO_SECS_SH 15
	34
0462681e SE	35	/* The maximum RTC clock cycles that are allowed to pass between two
	36	* consecutive clock counter register reads. If the values are corrupted a
	37	* bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
	38	* we end at 10ms which should be enough for most cases. If it once takes
	39	* longer than expected we do a retry.
	40	*/
	41	#define MAX_RTC_READ_DIFF_CYCLES 320
	42
179a502f SG	43	struct snvs_rtc_data {
179a502f SG	44	struct rtc_device *rtc;
d482893b FL	45	struct regmap *regmap;
d482893b FL	46	int offset;
179a502f	47	int irq;
7f899399	48	struct clk *clk;
179a502f SG	49	};
179a502f SG	50
cd7f3a24 TP	51	/* Read 64 bit timer register, which could be in inconsistent state */
	52	static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
	53	{
	54	u32 msb, lsb;
	55
	56	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	57	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	58	return (u64)msb << 32 \| lsb;
	59	}
	60
	61	/* Read the secure real time counter, taking care to deal with the cases of the
	62	* counter updating while being read.
	63	*/
d482893b	64	static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
179a502f SG	65	{
179a502f SG	66	u64 read1, read2;
0462681e	67	s64 diff;
cd7f3a24	68	unsigned int timeout = 100;
179a502f	69
cd7f3a24 TP	70	/* As expected, the registers might update between the read of the LSB
	71	* reg and the MSB reg. It's also possible that one register might be
	72	* in partially modified state as well.
	73	*/
	74	read1 = rtc_read_lpsrt(data);
179a502f	75	do {
cd7f3a24 TP	76	read2 = read1;
cd7f3a24 TP	77	read1 = rtc_read_lpsrt(data);
0462681e SE	78	diff = read1 - read2;
0462681e SE	79	} while (((diff < 0) \|\| (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
cd7f3a24 TP	80	if (!timeout)
cd7f3a24 TP	81	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
179a502f SG	82
	83	/* Convert 47-bit counter to 32-bit raw second count */
	84	return (u32) (read1 >> CNTR_TO_SECS_SH);
	85	}
	86
cd7f3a24 TP	87	/* Just read the lsb from the counter, dealing with inconsistent state */
cd7f3a24 TP	88	static int rtc_read_lp_counter_lsb(struct snvs_rtc_data data, u32 lsb)
179a502f	89	{
cd7f3a24	90	u32 count1, count2;
0462681e	91	s32 diff;
cd7f3a24 TP	92	unsigned int timeout = 100;
	93
	94	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	95	do {
	96	count2 = count1;
	97	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
0462681e SE	98	diff = count1 - count2;
0462681e SE	99	} while (((diff < 0) \|\| (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
cd7f3a24 TP	100	if (!timeout) {
	101	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
	102	return -ETIMEDOUT;
179a502f	103	}
cd7f3a24 TP	104
	105	*lsb = count1;
	106	return 0;
	107	}
	108
	109	static int rtc_write_sync_lp(struct snvs_rtc_data *data)
	110	{
	111	u32 count1, count2;
	112	u32 elapsed;
	113	unsigned int timeout = 1000;
	114	int ret;
	115
	116	ret = rtc_read_lp_counter_lsb(data, &count1);
	117	if (ret)
	118	return ret;
	119
	120	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	121	do {
	122	ret = rtc_read_lp_counter_lsb(data, &count2);
	123	if (ret)
	124	return ret;
	125	elapsed = count2 - count1; /* wrap around _is_ handled! */
	126	} while (elapsed < 3 && --timeout);
	127	if (!timeout) {
	128	dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
	129	return -ETIMEDOUT;
	130	}
	131	return 0;
179a502f SG	132	}
	133
	134	static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
	135	{
179a502f SG	136	int timeout = 1000;
	137	u32 lpcr;
	138
d482893b FL	139	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
d482893b FL	140	enable ? SNVS_LPCR_SRTC_ENV : 0);
179a502f SG	141
179a502f SG	142	while (--timeout) {
d482893b	143	regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
179a502f SG	144
	145	if (enable) {
	146	if (lpcr & SNVS_LPCR_SRTC_ENV)
	147	break;
	148	} else {
	149	if (!(lpcr & SNVS_LPCR_SRTC_ENV))
	150	break;
	151	}
	152	}
	153
	154	if (!timeout)
	155	return -ETIMEDOUT;
	156
	157	return 0;
	158	}
	159
	160	static int snvs_rtc_read_time(struct device dev, struct rtc_time tm)
	161	{
	162	struct snvs_rtc_data *data = dev_get_drvdata(dev);
4b957bde AH	163	unsigned long time;
	164	int ret;
	165
081e2500 XW	166	ret = clk_enable(data->clk);
	167	if (ret)
	168	return ret;
179a502f	169
4b957bde	170	time = rtc_read_lp_counter(data);
c59a9fc7	171	rtc_time64_to_tm(time, tm);
179a502f	172
081e2500	173	clk_disable(data->clk);
4b957bde	174
179a502f SG	175	return 0;
	176	}
	177
	178	static int snvs_rtc_set_time(struct device dev, struct rtc_time tm)
	179	{
	180	struct snvs_rtc_data *data = dev_get_drvdata(dev);
c59a9fc7	181	unsigned long time = rtc_tm_to_time64(tm);
1485991c	182	int ret;
179a502f	183
081e2500 XW	184	ret = clk_enable(data->clk);
	185	if (ret)
	186	return ret;
4b957bde	187
179a502f	188	/* Disable RTC first */
1485991c BD	189	ret = snvs_rtc_enable(data, false);
	190	if (ret)
	191	return ret;
179a502f SG	192
179a502f SG	193	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
d482893b FL	194	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
d482893b FL	195	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
179a502f SG	196
179a502f SG	197	/* Enable RTC again */
1485991c	198	ret = snvs_rtc_enable(data, true);
179a502f	199
081e2500	200	clk_disable(data->clk);
4b957bde	201
1485991c	202	return ret;
179a502f SG	203	}
	204
	205	static int snvs_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	206	{
	207	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	208	u32 lptar, lpsr;
4b957bde AH	209	int ret;
4b957bde AH	210
081e2500 XW	211	ret = clk_enable(data->clk);
	212	if (ret)
	213	return ret;
179a502f	214
d482893b	215	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
c59a9fc7	216	rtc_time64_to_tm(lptar, &alrm->time);
179a502f	217
d482893b	218	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	219	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
179a502f SG	220
081e2500	221	clk_disable(data->clk);
4b957bde	222
179a502f SG	223	return 0;
	224	}
	225
	226	static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	227	{
	228	struct snvs_rtc_data *data = dev_get_drvdata(dev);
4b957bde AH	229	int ret;
4b957bde AH	230
081e2500 XW	231	ret = clk_enable(data->clk);
	232	if (ret)
	233	return ret;
179a502f	234
d482893b FL	235	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
	236	(SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN),
	237	enable ? (SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN) : 0);
179a502f	238
4b957bde AH	239	ret = rtc_write_sync_lp(data);
4b957bde AH	240
081e2500	241	clk_disable(data->clk);
4b957bde AH	242
4b957bde AH	243	return ret;
179a502f SG	244	}
	245
	246	static int snvs_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	247	{
	248	struct snvs_rtc_data *data = dev_get_drvdata(dev);
c59a9fc7	249	unsigned long time = rtc_tm_to_time64(&alrm->time);
cd7f3a24	250	int ret;
179a502f	251
081e2500 XW	252	ret = clk_enable(data->clk);
	253	if (ret)
	254	return ret;
4b957bde	255
d482893b	256	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
cd7f3a24 TP	257	ret = rtc_write_sync_lp(data);
	258	if (ret)
	259	return ret;
d482893b	260	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
179a502f SG	261
179a502f SG	262	/* Clear alarm interrupt status bit */
d482893b	263	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
179a502f	264
081e2500	265	clk_disable(data->clk);
4b957bde	266
179a502f SG	267	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
	268	}
	269
	270	static const struct rtc_class_ops snvs_rtc_ops = {
	271	.read_time = snvs_rtc_read_time,
	272	.set_time = snvs_rtc_set_time,
	273	.read_alarm = snvs_rtc_read_alarm,
	274	.set_alarm = snvs_rtc_set_alarm,
	275	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
	276	};
	277
	278	static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
	279	{
	280	struct device *dev = dev_id;
	281	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	282	u32 lpsr;
	283	u32 events = 0;
	284
081e2500	285	clk_enable(data->clk);
edb190cb	286
d482893b	287	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	288
	289	if (lpsr & SNVS_LPSR_LPTA) {
	290	events \|= (RTC_AF \| RTC_IRQF);
	291
	292	/* RTC alarm should be one-shot */
	293	snvs_rtc_alarm_irq_enable(dev, 0);
	294
	295	rtc_update_irq(data->rtc, 1, events);
	296	}
	297
	298	/* clear interrupt status */
d482893b	299	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
179a502f	300
081e2500	301	clk_disable(data->clk);
edb190cb	302
179a502f SG	303	return events ? IRQ_HANDLED : IRQ_NONE;
	304	}
	305
d482893b FL	306	static const struct regmap_config snvs_rtc_config = {
	307	.reg_bits = 32,
	308	.val_bits = 32,
	309	.reg_stride = 4,
	310	};
	311
7863bd07 AH	312	static void snvs_rtc_action(void *data)
7863bd07 AH	313	{
081e2500	314	clk_disable_unprepare(data);
7863bd07 AH	315	}
7863bd07 AH	316
5a167f45	317	static int snvs_rtc_probe(struct platform_device *pdev)
179a502f SG	318	{
179a502f SG	319	struct snvs_rtc_data *data;
179a502f	320	int ret;
d482893b	321	void __iomem *mmio;
179a502f SG	322
	323	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	324	if (!data)
	325	return -ENOMEM;
	326
6fd4fe9b AH	327	data->rtc = devm_rtc_allocate_device(&pdev->dev);
	328	if (IS_ERR(data->rtc))
	329	return PTR_ERR(data->rtc);
	330
d482893b FL	331	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
	332
	333	if (IS_ERR(data->regmap)) {
	334	dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
d482893b	335
0c46b07c	336	mmio = devm_platform_ioremap_resource(pdev, 0);
d482893b FL	337	if (IS_ERR(mmio))
	338	return PTR_ERR(mmio);
	339
	340	data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	341	} else {
	342	data->offset = SNVS_LPREGISTER_OFFSET;
	343	of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	344	}
	345
75892900	346	if (IS_ERR(data->regmap)) {
d482893b FL	347	dev_err(&pdev->dev, "Can't find snvs syscon\n");
	348	return -ENODEV;
	349	}
179a502f SG	350
	351	data->irq = platform_get_irq(pdev, 0);
	352	if (data->irq < 0)
	353	return data->irq;
	354
7f899399 SM	355	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	356	if (IS_ERR(data->clk)) {
	357	data->clk = NULL;
	358	} else {
	359	ret = clk_prepare_enable(data->clk);
	360	if (ret) {
	361	dev_err(&pdev->dev,
	362	"Could not prepare or enable the snvs clock\n");
	363	return ret;
	364	}
	365	}
	366
7863bd07 AH	367	ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
	368	if (ret)
	369	return ret;
	370
179a502f SG	371	platform_set_drvdata(pdev, data);
179a502f SG	372
179a502f	373	/* Initialize glitch detect */
d482893b	374	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
179a502f SG	375
179a502f SG	376	/* Clear interrupt status */
d482893b	377	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
179a502f SG	378
179a502f SG	379	/* Enable RTC */
1485991c BD	380	ret = snvs_rtc_enable(data, true);
	381	if (ret) {
	382	dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
7863bd07	383	return ret;
1485991c	384	}
179a502f SG	385
179a502f SG	386	device_init_wakeup(&pdev->dev, true);
e7afddb2 AH	387	ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
	388	if (ret)
	389	dev_err(&pdev->dev, "failed to enable irq wake\n");
179a502f SG	390
	391	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
	392	IRQF_SHARED, "rtc alarm", &pdev->dev);
	393	if (ret) {
	394	dev_err(&pdev->dev, "failed to request irq %d: %d\n",
	395	data->irq, ret);
7863bd07	396	return ret;
179a502f SG	397	}
179a502f SG	398
6fd4fe9b	399	data->rtc->ops = &snvs_rtc_ops;
79610340	400	data->rtc->range_max = U32_MAX;
7f899399	401
fdcfd854	402	return devm_rtc_register_device(data->rtc);
179a502f SG	403	}
179a502f SG	404
dacb6a40	405	static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
119434f4 SA	406	{
	407	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	408
081e2500	409	clk_disable(data->clk);
7f899399	410
179a502f SG	411	return 0;
	412	}
	413
dacb6a40	414	static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
119434f4 SA	415	{
	416	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	417
	418	if (data->clk)
20af6770	419	return clk_enable(data->clk);
7f899399	420
179a502f SG	421	return 0;
179a502f SG	422	}
179a502f	423
7654e9d4	424	static const struct dev_pm_ops snvs_rtc_pm_ops = {
dacb6a40	425	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
7654e9d4	426	};
179a502f	427
5a167f45	428	static const struct of_device_id snvs_dt_ids[] = {
179a502f SG	429	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	430	{ /* sentinel */ }
	431	};
	432	MODULE_DEVICE_TABLE(of, snvs_dt_ids);
	433
	434	static struct platform_driver snvs_rtc_driver = {
	435	.driver = {
	436	.name = "snvs_rtc",
dacb6a40	437	.pm = &snvs_rtc_pm_ops,
c39b3717	438	.of_match_table = snvs_dt_ids,
179a502f SG	439	},
179a502f SG	440	.probe = snvs_rtc_probe,
179a502f SG	441	};
	442	module_platform_driver(snvs_rtc_driver);
	443
	444	MODULE_AUTHOR("Freescale Semiconductor, Inc.");
	445	MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
	446	MODULE_LICENSE("GPL");