Commit | Line | Data |
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179a502f SG |
1 | /* |
2 | * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_device.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/rtc.h> | |
7f899399 | 20 | #include <linux/clk.h> |
d482893b FL |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/regmap.h> | |
23 | ||
24 | #define SNVS_LPREGISTER_OFFSET 0x34 | |
179a502f SG |
25 | |
26 | /* These register offsets are relative to LP (Low Power) range */ | |
27 | #define SNVS_LPCR 0x04 | |
28 | #define SNVS_LPSR 0x18 | |
29 | #define SNVS_LPSRTCMR 0x1c | |
30 | #define SNVS_LPSRTCLR 0x20 | |
31 | #define SNVS_LPTAR 0x24 | |
32 | #define SNVS_LPPGDR 0x30 | |
33 | ||
34 | #define SNVS_LPCR_SRTC_ENV (1 << 0) | |
35 | #define SNVS_LPCR_LPTA_EN (1 << 1) | |
36 | #define SNVS_LPCR_LPWUI_EN (1 << 3) | |
37 | #define SNVS_LPSR_LPTA (1 << 0) | |
38 | ||
39 | #define SNVS_LPPGDR_INIT 0x41736166 | |
40 | #define CNTR_TO_SECS_SH 15 | |
41 | ||
42 | struct snvs_rtc_data { | |
43 | struct rtc_device *rtc; | |
d482893b FL |
44 | struct regmap *regmap; |
45 | int offset; | |
179a502f | 46 | int irq; |
7f899399 | 47 | struct clk *clk; |
179a502f SG |
48 | }; |
49 | ||
d482893b | 50 | static u32 rtc_read_lp_counter(struct snvs_rtc_data *data) |
179a502f SG |
51 | { |
52 | u64 read1, read2; | |
d482893b | 53 | u32 val; |
179a502f SG |
54 | |
55 | do { | |
d482893b FL |
56 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val); |
57 | read1 = val; | |
179a502f | 58 | read1 <<= 32; |
d482893b FL |
59 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val); |
60 | read1 |= val; | |
179a502f | 61 | |
d482893b FL |
62 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &val); |
63 | read2 = val; | |
179a502f | 64 | read2 <<= 32; |
d482893b FL |
65 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &val); |
66 | read2 |= val; | |
179a502f SG |
67 | } while (read1 != read2); |
68 | ||
69 | /* Convert 47-bit counter to 32-bit raw second count */ | |
70 | return (u32) (read1 >> CNTR_TO_SECS_SH); | |
71 | } | |
72 | ||
d482893b | 73 | static void rtc_write_sync_lp(struct snvs_rtc_data *data) |
179a502f SG |
74 | { |
75 | u32 count1, count2, count3; | |
76 | int i; | |
77 | ||
78 | /* Wait for 3 CKIL cycles */ | |
79 | for (i = 0; i < 3; i++) { | |
80 | do { | |
d482893b FL |
81 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); |
82 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2); | |
179a502f SG |
83 | } while (count1 != count2); |
84 | ||
85 | /* Now wait until counter value changes */ | |
86 | do { | |
87 | do { | |
d482893b FL |
88 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count2); |
89 | regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count3); | |
179a502f SG |
90 | } while (count2 != count3); |
91 | } while (count3 == count1); | |
92 | } | |
93 | } | |
94 | ||
95 | static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable) | |
96 | { | |
179a502f SG |
97 | int timeout = 1000; |
98 | u32 lpcr; | |
99 | ||
d482893b FL |
100 | regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV, |
101 | enable ? SNVS_LPCR_SRTC_ENV : 0); | |
179a502f SG |
102 | |
103 | while (--timeout) { | |
d482893b | 104 | regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); |
179a502f SG |
105 | |
106 | if (enable) { | |
107 | if (lpcr & SNVS_LPCR_SRTC_ENV) | |
108 | break; | |
109 | } else { | |
110 | if (!(lpcr & SNVS_LPCR_SRTC_ENV)) | |
111 | break; | |
112 | } | |
113 | } | |
114 | ||
115 | if (!timeout) | |
116 | return -ETIMEDOUT; | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
122 | { | |
123 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
d482893b | 124 | unsigned long time = rtc_read_lp_counter(data); |
179a502f SG |
125 | |
126 | rtc_time_to_tm(time, tm); | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
131 | static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
132 | { | |
133 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
134 | unsigned long time; | |
1485991c | 135 | int ret; |
179a502f SG |
136 | |
137 | rtc_tm_to_time(tm, &time); | |
138 | ||
139 | /* Disable RTC first */ | |
1485991c BD |
140 | ret = snvs_rtc_enable(data, false); |
141 | if (ret) | |
142 | return ret; | |
179a502f SG |
143 | |
144 | /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */ | |
d482893b FL |
145 | regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH); |
146 | regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH)); | |
179a502f SG |
147 | |
148 | /* Enable RTC again */ | |
1485991c | 149 | ret = snvs_rtc_enable(data, true); |
179a502f | 150 | |
1485991c | 151 | return ret; |
179a502f SG |
152 | } |
153 | ||
154 | static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
155 | { | |
156 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
157 | u32 lptar, lpsr; | |
158 | ||
d482893b | 159 | regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar); |
179a502f SG |
160 | rtc_time_to_tm(lptar, &alrm->time); |
161 | ||
d482893b | 162 | regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); |
179a502f SG |
163 | alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0; |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) | |
169 | { | |
170 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
179a502f | 171 | |
d482893b FL |
172 | regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, |
173 | (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN), | |
174 | enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0); | |
179a502f | 175 | |
d482893b | 176 | rtc_write_sync_lp(data); |
179a502f SG |
177 | |
178 | return 0; | |
179 | } | |
180 | ||
181 | static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
182 | { | |
183 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
184 | struct rtc_time *alrm_tm = &alrm->time; | |
185 | unsigned long time; | |
179a502f SG |
186 | |
187 | rtc_tm_to_time(alrm_tm, &time); | |
188 | ||
d482893b | 189 | regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0); |
7bb633b1 | 190 | rtc_write_sync_lp(data); |
d482893b | 191 | regmap_write(data->regmap, data->offset + SNVS_LPTAR, time); |
179a502f SG |
192 | |
193 | /* Clear alarm interrupt status bit */ | |
d482893b | 194 | regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA); |
179a502f SG |
195 | |
196 | return snvs_rtc_alarm_irq_enable(dev, alrm->enabled); | |
197 | } | |
198 | ||
199 | static const struct rtc_class_ops snvs_rtc_ops = { | |
200 | .read_time = snvs_rtc_read_time, | |
201 | .set_time = snvs_rtc_set_time, | |
202 | .read_alarm = snvs_rtc_read_alarm, | |
203 | .set_alarm = snvs_rtc_set_alarm, | |
204 | .alarm_irq_enable = snvs_rtc_alarm_irq_enable, | |
205 | }; | |
206 | ||
207 | static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id) | |
208 | { | |
209 | struct device *dev = dev_id; | |
210 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
211 | u32 lpsr; | |
212 | u32 events = 0; | |
213 | ||
d482893b | 214 | regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); |
179a502f SG |
215 | |
216 | if (lpsr & SNVS_LPSR_LPTA) { | |
217 | events |= (RTC_AF | RTC_IRQF); | |
218 | ||
219 | /* RTC alarm should be one-shot */ | |
220 | snvs_rtc_alarm_irq_enable(dev, 0); | |
221 | ||
222 | rtc_update_irq(data->rtc, 1, events); | |
223 | } | |
224 | ||
225 | /* clear interrupt status */ | |
d482893b | 226 | regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr); |
179a502f SG |
227 | |
228 | return events ? IRQ_HANDLED : IRQ_NONE; | |
229 | } | |
230 | ||
d482893b FL |
231 | static const struct regmap_config snvs_rtc_config = { |
232 | .reg_bits = 32, | |
233 | .val_bits = 32, | |
234 | .reg_stride = 4, | |
235 | }; | |
236 | ||
5a167f45 | 237 | static int snvs_rtc_probe(struct platform_device *pdev) |
179a502f SG |
238 | { |
239 | struct snvs_rtc_data *data; | |
240 | struct resource *res; | |
241 | int ret; | |
d482893b | 242 | void __iomem *mmio; |
179a502f SG |
243 | |
244 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); | |
245 | if (!data) | |
246 | return -ENOMEM; | |
247 | ||
d482893b FL |
248 | data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap"); |
249 | ||
250 | if (IS_ERR(data->regmap)) { | |
251 | dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n"); | |
252 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
253 | ||
254 | mmio = devm_ioremap_resource(&pdev->dev, res); | |
255 | if (IS_ERR(mmio)) | |
256 | return PTR_ERR(mmio); | |
257 | ||
258 | data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config); | |
259 | } else { | |
260 | data->offset = SNVS_LPREGISTER_OFFSET; | |
261 | of_property_read_u32(pdev->dev.of_node, "offset", &data->offset); | |
262 | } | |
263 | ||
75892900 | 264 | if (IS_ERR(data->regmap)) { |
d482893b FL |
265 | dev_err(&pdev->dev, "Can't find snvs syscon\n"); |
266 | return -ENODEV; | |
267 | } | |
179a502f SG |
268 | |
269 | data->irq = platform_get_irq(pdev, 0); | |
270 | if (data->irq < 0) | |
271 | return data->irq; | |
272 | ||
7f899399 SM |
273 | data->clk = devm_clk_get(&pdev->dev, "snvs-rtc"); |
274 | if (IS_ERR(data->clk)) { | |
275 | data->clk = NULL; | |
276 | } else { | |
277 | ret = clk_prepare_enable(data->clk); | |
278 | if (ret) { | |
279 | dev_err(&pdev->dev, | |
280 | "Could not prepare or enable the snvs clock\n"); | |
281 | return ret; | |
282 | } | |
283 | } | |
284 | ||
179a502f SG |
285 | platform_set_drvdata(pdev, data); |
286 | ||
179a502f | 287 | /* Initialize glitch detect */ |
d482893b | 288 | regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT); |
179a502f SG |
289 | |
290 | /* Clear interrupt status */ | |
d482893b | 291 | regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff); |
179a502f SG |
292 | |
293 | /* Enable RTC */ | |
1485991c BD |
294 | ret = snvs_rtc_enable(data, true); |
295 | if (ret) { | |
296 | dev_err(&pdev->dev, "failed to enable rtc %d\n", ret); | |
297 | goto error_rtc_device_register; | |
298 | } | |
179a502f SG |
299 | |
300 | device_init_wakeup(&pdev->dev, true); | |
301 | ||
302 | ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler, | |
303 | IRQF_SHARED, "rtc alarm", &pdev->dev); | |
304 | if (ret) { | |
305 | dev_err(&pdev->dev, "failed to request irq %d: %d\n", | |
306 | data->irq, ret); | |
7f899399 | 307 | goto error_rtc_device_register; |
179a502f SG |
308 | } |
309 | ||
904784c1 | 310 | data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
179a502f SG |
311 | &snvs_rtc_ops, THIS_MODULE); |
312 | if (IS_ERR(data->rtc)) { | |
313 | ret = PTR_ERR(data->rtc); | |
314 | dev_err(&pdev->dev, "failed to register rtc: %d\n", ret); | |
7f899399 | 315 | goto error_rtc_device_register; |
179a502f SG |
316 | } |
317 | ||
318 | return 0; | |
7f899399 SM |
319 | |
320 | error_rtc_device_register: | |
321 | if (data->clk) | |
322 | clk_disable_unprepare(data->clk); | |
323 | ||
324 | return ret; | |
179a502f SG |
325 | } |
326 | ||
179a502f SG |
327 | #ifdef CONFIG_PM_SLEEP |
328 | static int snvs_rtc_suspend(struct device *dev) | |
329 | { | |
330 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
331 | ||
332 | if (device_may_wakeup(dev)) | |
a350259d | 333 | return enable_irq_wake(data->irq); |
179a502f | 334 | |
119434f4 SA |
335 | return 0; |
336 | } | |
337 | ||
338 | static int snvs_rtc_suspend_noirq(struct device *dev) | |
339 | { | |
340 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
341 | ||
7f899399 SM |
342 | if (data->clk) |
343 | clk_disable_unprepare(data->clk); | |
344 | ||
179a502f SG |
345 | return 0; |
346 | } | |
347 | ||
348 | static int snvs_rtc_resume(struct device *dev) | |
349 | { | |
350 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
351 | ||
352 | if (device_may_wakeup(dev)) | |
119434f4 | 353 | return disable_irq_wake(data->irq); |
179a502f | 354 | |
119434f4 SA |
355 | return 0; |
356 | } | |
357 | ||
358 | static int snvs_rtc_resume_noirq(struct device *dev) | |
359 | { | |
360 | struct snvs_rtc_data *data = dev_get_drvdata(dev); | |
361 | ||
362 | if (data->clk) | |
363 | return clk_prepare_enable(data->clk); | |
7f899399 | 364 | |
179a502f SG |
365 | return 0; |
366 | } | |
179a502f | 367 | |
7654e9d4 | 368 | static const struct dev_pm_ops snvs_rtc_pm_ops = { |
119434f4 SA |
369 | .suspend = snvs_rtc_suspend, |
370 | .suspend_noirq = snvs_rtc_suspend_noirq, | |
371 | .resume = snvs_rtc_resume, | |
372 | .resume_noirq = snvs_rtc_resume_noirq, | |
7654e9d4 | 373 | }; |
179a502f | 374 | |
88221c32 GR |
375 | #define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops) |
376 | ||
377 | #else | |
378 | ||
379 | #define SNVS_RTC_PM_OPS NULL | |
380 | ||
381 | #endif | |
382 | ||
5a167f45 | 383 | static const struct of_device_id snvs_dt_ids[] = { |
179a502f SG |
384 | { .compatible = "fsl,sec-v4.0-mon-rtc-lp", }, |
385 | { /* sentinel */ } | |
386 | }; | |
387 | MODULE_DEVICE_TABLE(of, snvs_dt_ids); | |
388 | ||
389 | static struct platform_driver snvs_rtc_driver = { | |
390 | .driver = { | |
391 | .name = "snvs_rtc", | |
88221c32 | 392 | .pm = SNVS_RTC_PM_OPS, |
c39b3717 | 393 | .of_match_table = snvs_dt_ids, |
179a502f SG |
394 | }, |
395 | .probe = snvs_rtc_probe, | |
179a502f SG |
396 | }; |
397 | module_platform_driver(snvs_rtc_driver); | |
398 | ||
399 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
400 | MODULE_DESCRIPTION("Freescale SNVS RTC Driver"); | |
401 | MODULE_LICENSE("GPL"); |