[linux-2.6-block.git] / drivers / rtc / rtc-snvs.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/rtc.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#define SNVS_LPREGISTER_OFFSET	0x34

/* These register offsets are relative to LP (Low Power) range */
#define SNVS_LPCR		0x04
#define SNVS_LPSR		0x18
#define SNVS_LPSRTCMR		0x1c
#define SNVS_LPSRTCLR		0x20
#define SNVS_LPTAR		0x24
#define SNVS_LPPGDR		0x30

#define SNVS_LPCR_SRTC_ENV	(1 << 0)
#define SNVS_LPCR_LPTA_EN	(1 << 1)
#define SNVS_LPCR_LPWUI_EN	(1 << 3)
#define SNVS_LPSR_LPTA		(1 << 0)

#define SNVS_LPPGDR_INIT	0x41736166
#define CNTR_TO_SECS_SH		15

struct snvs_rtc_data {
	struct rtc_device *rtc;
	struct regmap *regmap;
	int offset;
	int irq;
	struct clk *clk;
};

/* Read 64 bit timer register, which could be in inconsistent state */
static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
{
	u32 msb, lsb;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	return (u64)msb << 32 | lsb;
}

/* Read the secure real time counter, taking care to deal with the cases of the
 * counter updating while being read.
 */
static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
{
	u64 read1, read2;
	unsigned int timeout = 100;

	/* As expected, the registers might update between the read of the LSB
	 * reg and the MSB reg.  It's also possible that one register might be
	 * in partially modified state as well.
	 */
	read1 = rtc_read_lpsrt(data);
	do {
		read2 = read1;
		read1 = rtc_read_lpsrt(data);
	} while (read1 != read2 && --timeout);
	if (!timeout)
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");

	/* Convert 47-bit counter to 32-bit raw second count */
	return (u32) (read1 >> CNTR_TO_SECS_SH);
}

/* Just read the lsb from the counter, dealing with inconsistent state */
static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
{
	u32 count1, count2;
	unsigned int timeout = 100;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	do {
		count2 = count1;
		regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	} while (count1 != count2 && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
		return -ETIMEDOUT;
	}

	*lsb = count1;
	return 0;
}

static int rtc_write_sync_lp(struct snvs_rtc_data *data)
{
	u32 count1, count2;
	u32 elapsed;
	unsigned int timeout = 1000;
	int ret;

	ret = rtc_read_lp_counter_lsb(data, &count1);
	if (ret)
		return ret;

	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	do {
		ret = rtc_read_lp_counter_lsb(data, &count2);
		if (ret)
			return ret;
		elapsed = count2 - count1; /* wrap around _is_ handled! */
	} while (elapsed < 3 && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
		return -ETIMEDOUT;
	}
	return 0;
}

static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
{
	int timeout = 1000;
	u32 lpcr;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
			   enable ? SNVS_LPCR_SRTC_ENV : 0);

	while (--timeout) {
		regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);

		if (enable) {
			if (lpcr & SNVS_LPCR_SRTC_ENV)
				break;
		} else {
			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
				break;
		}
	}

	if (!timeout)
		return -ETIMEDOUT;

	return 0;
}

static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time = rtc_read_lp_counter(data);

	rtc_time_to_tm(time, tm);

	return 0;
}

static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time;
	int ret;

	rtc_tm_to_time(tm, &time);

	/* Disable RTC first */
	ret = snvs_rtc_enable(data, false);
	if (ret)
		return ret;

	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));

	/* Enable RTC again */
	ret = snvs_rtc_enable(data, true);

	return ret;
}

static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lptar, lpsr;

	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
	rtc_time_to_tm(lptar, &alrm->time);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;

	return 0;
}

static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
			   (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
			   enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);

	return rtc_write_sync_lp(data);
}

static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	struct rtc_time *alrm_tm = &alrm->time;
	unsigned long time;
	int ret;

	rtc_tm_to_time(alrm_tm, &time);

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
	ret = rtc_write_sync_lp(data);
	if (ret)
		return ret;
	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);

	/* Clear alarm interrupt status bit */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);

	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
}

static const struct rtc_class_ops snvs_rtc_ops = {
	.read_time = snvs_rtc_read_time,
	.set_time = snvs_rtc_set_time,
	.read_alarm = snvs_rtc_read_alarm,
	.set_alarm = snvs_rtc_set_alarm,
	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
};

static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lpsr;
	u32 events = 0;

	if (data->clk)
		clk_enable(data->clk);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);

	if (lpsr & SNVS_LPSR_LPTA) {
		events |= (RTC_AF | RTC_IRQF);

		/* RTC alarm should be one-shot */
		snvs_rtc_alarm_irq_enable(dev, 0);

		rtc_update_irq(data->rtc, 1, events);
	}

	/* clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);

	if (data->clk)
		clk_disable(data->clk);

	return events ? IRQ_HANDLED : IRQ_NONE;
}

static const struct regmap_config snvs_rtc_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static int snvs_rtc_probe(struct platform_device *pdev)
{
	struct snvs_rtc_data *data;
	int ret;
	void __iomem *mmio;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");

	if (IS_ERR(data->regmap)) {
		dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");

		mmio = devm_platform_ioremap_resource(pdev, 0);
		if (IS_ERR(mmio))
			return PTR_ERR(mmio);

		data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	} else {
		data->offset = SNVS_LPREGISTER_OFFSET;
		of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	}

	if (IS_ERR(data->regmap)) {
		dev_err(&pdev->dev, "Can't find snvs syscon\n");
		return -ENODEV;
	}

	data->irq = platform_get_irq(pdev, 0);
	if (data->irq < 0)
		return data->irq;

	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	if (IS_ERR(data->clk)) {
		data->clk = NULL;
	} else {
		ret = clk_prepare_enable(data->clk);
		if (ret) {
			dev_err(&pdev->dev,
				"Could not prepare or enable the snvs clock\n");
			return ret;
		}
	}

	platform_set_drvdata(pdev, data);

	/* Initialize glitch detect */
	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);

	/* Clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);

	/* Enable RTC */
	ret = snvs_rtc_enable(data, true);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
		goto error_rtc_device_register;
	}

	device_init_wakeup(&pdev->dev, true);
	ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
	if (ret)
		dev_err(&pdev->dev, "failed to enable irq wake\n");

	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
			       IRQF_SHARED, "rtc alarm", &pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to request irq %d: %d\n",
			data->irq, ret);
		goto error_rtc_device_register;
	}

	data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
					&snvs_rtc_ops, THIS_MODULE);
	if (IS_ERR(data->rtc)) {
		ret = PTR_ERR(data->rtc);
		dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
		goto error_rtc_device_register;
	}

	return 0;

error_rtc_device_register:
	if (data->clk)
		clk_disable_unprepare(data->clk);

	return ret;
}

static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (data->clk)
		clk_disable_unprepare(data->clk);

	return 0;
}

static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (data->clk)
		return clk_prepare_enable(data->clk);

	return 0;
}

static const struct dev_pm_ops snvs_rtc_pm_ops = {
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
};

static const struct of_device_id snvs_dt_ids[] = {
	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, snvs_dt_ids);

static struct platform_driver snvs_rtc_driver = {
	.driver = {
		.name	= "snvs_rtc",
		.pm	= &snvs_rtc_pm_ops,
		.of_match_table = snvs_dt_ids,
	},
	.probe		= snvs_rtc_probe,
};
module_platform_driver(snvs_rtc_driver);

MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5874c7f1 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
179a502f SG	4
	5	#include <linux/init.h>
	6	#include <linux/io.h>
	7	#include <linux/kernel.h>
	8	#include <linux/module.h>
	9	#include <linux/of.h>
	10	#include <linux/of_device.h>
	11	#include <linux/platform_device.h>
e7afddb2	12	#include <linux/pm_wakeirq.h>
179a502f	13	#include <linux/rtc.h>
7f899399	14	#include <linux/clk.h>
d482893b FL	15	#include <linux/mfd/syscon.h>
	16	#include <linux/regmap.h>
	17
	18	#define SNVS_LPREGISTER_OFFSET 0x34
179a502f SG	19
	20	/* These register offsets are relative to LP (Low Power) range */
	21	#define SNVS_LPCR 0x04
	22	#define SNVS_LPSR 0x18
	23	#define SNVS_LPSRTCMR 0x1c
	24	#define SNVS_LPSRTCLR 0x20
	25	#define SNVS_LPTAR 0x24
	26	#define SNVS_LPPGDR 0x30
	27
	28	#define SNVS_LPCR_SRTC_ENV (1 << 0)
	29	#define SNVS_LPCR_LPTA_EN (1 << 1)
	30	#define SNVS_LPCR_LPWUI_EN (1 << 3)
	31	#define SNVS_LPSR_LPTA (1 << 0)
	32
	33	#define SNVS_LPPGDR_INIT 0x41736166
	34	#define CNTR_TO_SECS_SH 15
	35
	36	struct snvs_rtc_data {
	37	struct rtc_device *rtc;
d482893b FL	38	struct regmap *regmap;
d482893b FL	39	int offset;
179a502f	40	int irq;
7f899399	41	struct clk *clk;
179a502f SG	42	};
179a502f SG	43
cd7f3a24 TP	44	/* Read 64 bit timer register, which could be in inconsistent state */
	45	static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
	46	{
	47	u32 msb, lsb;
	48
	49	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	50	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	51	return (u64)msb << 32 \| lsb;
	52	}
	53
	54	/* Read the secure real time counter, taking care to deal with the cases of the
	55	* counter updating while being read.
	56	*/
d482893b	57	static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
179a502f SG	58	{
179a502f SG	59	u64 read1, read2;
cd7f3a24	60	unsigned int timeout = 100;
179a502f	61
cd7f3a24 TP	62	/* As expected, the registers might update between the read of the LSB
	63	* reg and the MSB reg. It's also possible that one register might be
	64	* in partially modified state as well.
	65	*/
	66	read1 = rtc_read_lpsrt(data);
179a502f	67	do {
cd7f3a24 TP	68	read2 = read1;
	69	read1 = rtc_read_lpsrt(data);
	70	} while (read1 != read2 && --timeout);
	71	if (!timeout)
	72	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
179a502f SG	73
	74	/* Convert 47-bit counter to 32-bit raw second count */
	75	return (u32) (read1 >> CNTR_TO_SECS_SH);
	76	}
	77
cd7f3a24 TP	78	/* Just read the lsb from the counter, dealing with inconsistent state */
cd7f3a24 TP	79	static int rtc_read_lp_counter_lsb(struct snvs_rtc_data data, u32 lsb)
179a502f	80	{
cd7f3a24 TP	81	u32 count1, count2;
	82	unsigned int timeout = 100;
	83
	84	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	85	do {
	86	count2 = count1;
	87	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	88	} while (count1 != count2 && --timeout);
	89	if (!timeout) {
	90	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
	91	return -ETIMEDOUT;
179a502f	92	}
cd7f3a24 TP	93
	94	*lsb = count1;
	95	return 0;
	96	}
	97
	98	static int rtc_write_sync_lp(struct snvs_rtc_data *data)
	99	{
	100	u32 count1, count2;
	101	u32 elapsed;
	102	unsigned int timeout = 1000;
	103	int ret;
	104
	105	ret = rtc_read_lp_counter_lsb(data, &count1);
	106	if (ret)
	107	return ret;
	108
	109	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	110	do {
	111	ret = rtc_read_lp_counter_lsb(data, &count2);
	112	if (ret)
	113	return ret;
	114	elapsed = count2 - count1; /* wrap around _is_ handled! */
	115	} while (elapsed < 3 && --timeout);
	116	if (!timeout) {
	117	dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
	118	return -ETIMEDOUT;
	119	}
	120	return 0;
179a502f SG	121	}
	122
	123	static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
	124	{
179a502f SG	125	int timeout = 1000;
	126	u32 lpcr;
	127
d482893b FL	128	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
d482893b FL	129	enable ? SNVS_LPCR_SRTC_ENV : 0);
179a502f SG	130
179a502f SG	131	while (--timeout) {
d482893b	132	regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
179a502f SG	133
	134	if (enable) {
	135	if (lpcr & SNVS_LPCR_SRTC_ENV)
	136	break;
	137	} else {
	138	if (!(lpcr & SNVS_LPCR_SRTC_ENV))
	139	break;
	140	}
	141	}
	142
	143	if (!timeout)
	144	return -ETIMEDOUT;
	145
	146	return 0;
	147	}
	148
	149	static int snvs_rtc_read_time(struct device dev, struct rtc_time tm)
	150	{
	151	struct snvs_rtc_data *data = dev_get_drvdata(dev);
d482893b	152	unsigned long time = rtc_read_lp_counter(data);
179a502f SG	153
	154	rtc_time_to_tm(time, tm);
	155
	156	return 0;
	157	}
	158
	159	static int snvs_rtc_set_time(struct device dev, struct rtc_time tm)
	160	{
	161	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	162	unsigned long time;
1485991c	163	int ret;
179a502f SG	164
	165	rtc_tm_to_time(tm, &time);
	166
	167	/* Disable RTC first */
1485991c BD	168	ret = snvs_rtc_enable(data, false);
	169	if (ret)
	170	return ret;
179a502f SG	171
179a502f SG	172	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
d482893b FL	173	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
d482893b FL	174	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
179a502f SG	175
179a502f SG	176	/* Enable RTC again */
1485991c	177	ret = snvs_rtc_enable(data, true);
179a502f	178
1485991c	179	return ret;
179a502f SG	180	}
	181
	182	static int snvs_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	183	{
	184	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	185	u32 lptar, lpsr;
	186
d482893b	187	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
179a502f SG	188	rtc_time_to_tm(lptar, &alrm->time);
179a502f SG	189
d482893b	190	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	191	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
	192
	193	return 0;
	194	}
	195
	196	static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	197	{
	198	struct snvs_rtc_data *data = dev_get_drvdata(dev);
179a502f	199
d482893b FL	200	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
	201	(SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN),
	202	enable ? (SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN) : 0);
179a502f	203
cd7f3a24	204	return rtc_write_sync_lp(data);
179a502f SG	205	}
	206
	207	static int snvs_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	208	{
	209	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	210	struct rtc_time *alrm_tm = &alrm->time;
	211	unsigned long time;
cd7f3a24	212	int ret;
179a502f SG	213
	214	rtc_tm_to_time(alrm_tm, &time);
	215
d482893b	216	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
cd7f3a24 TP	217	ret = rtc_write_sync_lp(data);
	218	if (ret)
	219	return ret;
d482893b	220	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
179a502f SG	221
179a502f SG	222	/* Clear alarm interrupt status bit */
d482893b	223	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
179a502f SG	224
	225	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
	226	}
	227
	228	static const struct rtc_class_ops snvs_rtc_ops = {
	229	.read_time = snvs_rtc_read_time,
	230	.set_time = snvs_rtc_set_time,
	231	.read_alarm = snvs_rtc_read_alarm,
	232	.set_alarm = snvs_rtc_set_alarm,
	233	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
	234	};
	235
	236	static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
	237	{
	238	struct device *dev = dev_id;
	239	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	240	u32 lpsr;
	241	u32 events = 0;
	242
edb190cb AH	243	if (data->clk)
	244	clk_enable(data->clk);
	245
d482893b	246	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	247
	248	if (lpsr & SNVS_LPSR_LPTA) {
	249	events \|= (RTC_AF \| RTC_IRQF);
	250
	251	/* RTC alarm should be one-shot */
	252	snvs_rtc_alarm_irq_enable(dev, 0);
	253
	254	rtc_update_irq(data->rtc, 1, events);
	255	}
	256
	257	/* clear interrupt status */
d482893b	258	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
179a502f	259
edb190cb AH	260	if (data->clk)
	261	clk_disable(data->clk);
	262
179a502f SG	263	return events ? IRQ_HANDLED : IRQ_NONE;
	264	}
	265
d482893b FL	266	static const struct regmap_config snvs_rtc_config = {
	267	.reg_bits = 32,
	268	.val_bits = 32,
	269	.reg_stride = 4,
	270	};
	271
5a167f45	272	static int snvs_rtc_probe(struct platform_device *pdev)
179a502f SG	273	{
179a502f SG	274	struct snvs_rtc_data *data;
179a502f	275	int ret;
d482893b	276	void __iomem *mmio;
179a502f SG	277
	278	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	279	if (!data)
	280	return -ENOMEM;
	281
d482893b FL	282	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
	283
	284	if (IS_ERR(data->regmap)) {
	285	dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
d482893b	286
0c46b07c	287	mmio = devm_platform_ioremap_resource(pdev, 0);
d482893b FL	288	if (IS_ERR(mmio))
	289	return PTR_ERR(mmio);
	290
	291	data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	292	} else {
	293	data->offset = SNVS_LPREGISTER_OFFSET;
	294	of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	295	}
	296
75892900	297	if (IS_ERR(data->regmap)) {
d482893b FL	298	dev_err(&pdev->dev, "Can't find snvs syscon\n");
	299	return -ENODEV;
	300	}
179a502f SG	301
	302	data->irq = platform_get_irq(pdev, 0);
	303	if (data->irq < 0)
	304	return data->irq;
	305
7f899399 SM	306	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	307	if (IS_ERR(data->clk)) {
	308	data->clk = NULL;
	309	} else {
	310	ret = clk_prepare_enable(data->clk);
	311	if (ret) {
	312	dev_err(&pdev->dev,
	313	"Could not prepare or enable the snvs clock\n");
	314	return ret;
	315	}
	316	}
	317
179a502f SG	318	platform_set_drvdata(pdev, data);
179a502f SG	319
179a502f	320	/* Initialize glitch detect */
d482893b	321	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
179a502f SG	322
179a502f SG	323	/* Clear interrupt status */
d482893b	324	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
179a502f SG	325
179a502f SG	326	/* Enable RTC */
1485991c BD	327	ret = snvs_rtc_enable(data, true);
	328	if (ret) {
	329	dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
	330	goto error_rtc_device_register;
	331	}
179a502f SG	332
179a502f SG	333	device_init_wakeup(&pdev->dev, true);
e7afddb2 AH	334	ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
	335	if (ret)
	336	dev_err(&pdev->dev, "failed to enable irq wake\n");
179a502f SG	337
	338	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
	339	IRQF_SHARED, "rtc alarm", &pdev->dev);
	340	if (ret) {
	341	dev_err(&pdev->dev, "failed to request irq %d: %d\n",
	342	data->irq, ret);
7f899399	343	goto error_rtc_device_register;
179a502f SG	344	}
179a502f SG	345
904784c1	346	data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
179a502f SG	347	&snvs_rtc_ops, THIS_MODULE);
	348	if (IS_ERR(data->rtc)) {
	349	ret = PTR_ERR(data->rtc);
	350	dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
7f899399	351	goto error_rtc_device_register;
179a502f SG	352	}
	353
	354	return 0;
7f899399 SM	355
	356	error_rtc_device_register:
	357	if (data->clk)
	358	clk_disable_unprepare(data->clk);
	359
	360	return ret;
179a502f SG	361	}
179a502f SG	362
dacb6a40	363	static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
119434f4 SA	364	{
	365	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	366
7f899399 SM	367	if (data->clk)
	368	clk_disable_unprepare(data->clk);
	369
179a502f SG	370	return 0;
	371	}
	372
dacb6a40	373	static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
119434f4 SA	374	{
	375	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	376
	377	if (data->clk)
	378	return clk_prepare_enable(data->clk);
7f899399	379
179a502f SG	380	return 0;
179a502f SG	381	}
179a502f	382
7654e9d4	383	static const struct dev_pm_ops snvs_rtc_pm_ops = {
dacb6a40	384	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
7654e9d4	385	};
179a502f	386
5a167f45	387	static const struct of_device_id snvs_dt_ids[] = {
179a502f SG	388	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	389	{ /* sentinel */ }
	390	};
	391	MODULE_DEVICE_TABLE(of, snvs_dt_ids);
	392
	393	static struct platform_driver snvs_rtc_driver = {
	394	.driver = {
	395	.name = "snvs_rtc",
dacb6a40	396	.pm = &snvs_rtc_pm_ops,
c39b3717	397	.of_match_table = snvs_dt_ids,
179a502f SG	398	},
179a502f SG	399	.probe = snvs_rtc_probe,
179a502f SG	400	};
	401	module_platform_driver(snvs_rtc_driver);
	402
	403	MODULE_AUTHOR("Freescale Semiconductor, Inc.");
	404	MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
	405	MODULE_LICENSE("GPL");