[linux-2.6-block.git] / drivers / rtc / rtc-snvs.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#define SNVS_LPREGISTER_OFFSET	0x34

/* These register offsets are relative to LP (Low Power) range */
#define SNVS_LPCR		0x04
#define SNVS_LPSR		0x18
#define SNVS_LPSRTCMR		0x1c
#define SNVS_LPSRTCLR		0x20
#define SNVS_LPTAR		0x24
#define SNVS_LPPGDR		0x30

#define SNVS_LPCR_SRTC_ENV	(1 << 0)
#define SNVS_LPCR_LPTA_EN	(1 << 1)
#define SNVS_LPCR_LPWUI_EN	(1 << 3)
#define SNVS_LPSR_LPTA		(1 << 0)

#define SNVS_LPPGDR_INIT	0x41736166
#define CNTR_TO_SECS_SH		15

struct snvs_rtc_data {
	struct rtc_device *rtc;
	struct regmap *regmap;
	int offset;
	int irq;
	struct clk *clk;
};

/* Read 64 bit timer register, which could be in inconsistent state */
static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
{
	u32 msb, lsb;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	return (u64)msb << 32 | lsb;
}

/* Read the secure real time counter, taking care to deal with the cases of the
 * counter updating while being read.
 */
static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
{
	u64 read1, read2;
	unsigned int timeout = 100;

	/* As expected, the registers might update between the read of the LSB
	 * reg and the MSB reg.  It's also possible that one register might be
	 * in partially modified state as well.
	 */
	read1 = rtc_read_lpsrt(data);
	do {
		read2 = read1;
		read1 = rtc_read_lpsrt(data);
	} while (read1 != read2 && --timeout);
	if (!timeout)
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");

	/* Convert 47-bit counter to 32-bit raw second count */
	return (u32) (read1 >> CNTR_TO_SECS_SH);
}

/* Just read the lsb from the counter, dealing with inconsistent state */
static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
{
	u32 count1, count2;
	unsigned int timeout = 100;

	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	do {
		count2 = count1;
		regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	} while (count1 != count2 && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
		return -ETIMEDOUT;
	}

	*lsb = count1;
	return 0;
}

static int rtc_write_sync_lp(struct snvs_rtc_data *data)
{
	u32 count1, count2;
	u32 elapsed;
	unsigned int timeout = 1000;
	int ret;

	ret = rtc_read_lp_counter_lsb(data, &count1);
	if (ret)
		return ret;

	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	do {
		ret = rtc_read_lp_counter_lsb(data, &count2);
		if (ret)
			return ret;
		elapsed = count2 - count1; /* wrap around _is_ handled! */
	} while (elapsed < 3 && --timeout);
	if (!timeout) {
		dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
		return -ETIMEDOUT;
	}
	return 0;
}

static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
{
	int timeout = 1000;
	u32 lpcr;

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
			   enable ? SNVS_LPCR_SRTC_ENV : 0);

	while (--timeout) {
		regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);

		if (enable) {
			if (lpcr & SNVS_LPCR_SRTC_ENV)
				break;
		} else {
			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
				break;
		}
	}

	if (!timeout)
		return -ETIMEDOUT;

	return 0;
}

static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time = rtc_read_lp_counter(data);

	rtc_time_to_tm(time, tm);

	return 0;
}

static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	unsigned long time;
	int ret;

	rtc_tm_to_time(tm, &time);

	/* Disable RTC first */
	ret = snvs_rtc_enable(data, false);
	if (ret)
		return ret;

	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));

	/* Enable RTC again */
	ret = snvs_rtc_enable(data, true);

	return ret;
}

static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lptar, lpsr;

	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
	rtc_time_to_tm(lptar, &alrm->time);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;

	return 0;
}

static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
			   (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
			   enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);

	return rtc_write_sync_lp(data);
}

static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	struct rtc_time *alrm_tm = &alrm->time;
	unsigned long time;
	int ret;

	rtc_tm_to_time(alrm_tm, &time);

	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
	ret = rtc_write_sync_lp(data);
	if (ret)
		return ret;
	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);

	/* Clear alarm interrupt status bit */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);

	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
}

static const struct rtc_class_ops snvs_rtc_ops = {
	.read_time = snvs_rtc_read_time,
	.set_time = snvs_rtc_set_time,
	.read_alarm = snvs_rtc_read_alarm,
	.set_alarm = snvs_rtc_set_alarm,
	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
};

static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	u32 lpsr;
	u32 events = 0;

	if (data->clk)
		clk_enable(data->clk);

	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);

	if (lpsr & SNVS_LPSR_LPTA) {
		events |= (RTC_AF | RTC_IRQF);

		/* RTC alarm should be one-shot */
		snvs_rtc_alarm_irq_enable(dev, 0);

		rtc_update_irq(data->rtc, 1, events);
	}

	/* clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);

	if (data->clk)
		clk_disable(data->clk);

	return events ? IRQ_HANDLED : IRQ_NONE;
}

static const struct regmap_config snvs_rtc_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static int snvs_rtc_probe(struct platform_device *pdev)
{
	struct snvs_rtc_data *data;
	struct resource *res;
	int ret;
	void __iomem *mmio;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");

	if (IS_ERR(data->regmap)) {
		dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

		mmio = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(mmio))
			return PTR_ERR(mmio);

		data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	} else {
		data->offset = SNVS_LPREGISTER_OFFSET;
		of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	}

	if (IS_ERR(data->regmap)) {
		dev_err(&pdev->dev, "Can't find snvs syscon\n");
		return -ENODEV;
	}

	data->irq = platform_get_irq(pdev, 0);
	if (data->irq < 0)
		return data->irq;

	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	if (IS_ERR(data->clk)) {
		data->clk = NULL;
	} else {
		ret = clk_prepare_enable(data->clk);
		if (ret) {
			dev_err(&pdev->dev,
				"Could not prepare or enable the snvs clock\n");
			return ret;
		}
	}

	platform_set_drvdata(pdev, data);

	/* Initialize glitch detect */
	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);

	/* Clear interrupt status */
	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);

	/* Enable RTC */
	ret = snvs_rtc_enable(data, true);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
		goto error_rtc_device_register;
	}

	device_init_wakeup(&pdev->dev, true);

	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
			       IRQF_SHARED, "rtc alarm", &pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "failed to request irq %d: %d\n",
			data->irq, ret);
		goto error_rtc_device_register;
	}

	data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
					&snvs_rtc_ops, THIS_MODULE);
	if (IS_ERR(data->rtc)) {
		ret = PTR_ERR(data->rtc);
		dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
		goto error_rtc_device_register;
	}

	return 0;

error_rtc_device_register:
	if (data->clk)
		clk_disable_unprepare(data->clk);

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int snvs_rtc_suspend(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		return enable_irq_wake(data->irq);

	return 0;
}

static int snvs_rtc_suspend_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (data->clk)
		clk_disable_unprepare(data->clk);

	return 0;
}

static int snvs_rtc_resume(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		return disable_irq_wake(data->irq);

	return 0;
}

static int snvs_rtc_resume_noirq(struct device *dev)
{
	struct snvs_rtc_data *data = dev_get_drvdata(dev);

	if (data->clk)
		return clk_prepare_enable(data->clk);

	return 0;
}

static const struct dev_pm_ops snvs_rtc_pm_ops = {
	.suspend = snvs_rtc_suspend,
	.suspend_noirq = snvs_rtc_suspend_noirq,
	.resume = snvs_rtc_resume,
	.resume_noirq = snvs_rtc_resume_noirq,
};

#define SNVS_RTC_PM_OPS	(&snvs_rtc_pm_ops)

#else

#define SNVS_RTC_PM_OPS	NULL

#endif

static const struct of_device_id snvs_dt_ids[] = {
	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, snvs_dt_ids);

static struct platform_driver snvs_rtc_driver = {
	.driver = {
		.name	= "snvs_rtc",
		.pm	= SNVS_RTC_PM_OPS,
		.of_match_table = snvs_dt_ids,
	},
	.probe		= snvs_rtc_probe,
};
module_platform_driver(snvs_rtc_driver);

MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5874c7f1 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
179a502f SG	4
	5	#include <linux/init.h>
	6	#include <linux/io.h>
	7	#include <linux/kernel.h>
	8	#include <linux/module.h>
	9	#include <linux/of.h>
	10	#include <linux/of_device.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/rtc.h>
7f899399	13	#include <linux/clk.h>
d482893b FL	14	#include <linux/mfd/syscon.h>
	15	#include <linux/regmap.h>
	16
	17	#define SNVS_LPREGISTER_OFFSET 0x34
179a502f SG	18
	19	/* These register offsets are relative to LP (Low Power) range */
	20	#define SNVS_LPCR 0x04
	21	#define SNVS_LPSR 0x18
	22	#define SNVS_LPSRTCMR 0x1c
	23	#define SNVS_LPSRTCLR 0x20
	24	#define SNVS_LPTAR 0x24
	25	#define SNVS_LPPGDR 0x30
	26
	27	#define SNVS_LPCR_SRTC_ENV (1 << 0)
	28	#define SNVS_LPCR_LPTA_EN (1 << 1)
	29	#define SNVS_LPCR_LPWUI_EN (1 << 3)
	30	#define SNVS_LPSR_LPTA (1 << 0)
	31
	32	#define SNVS_LPPGDR_INIT 0x41736166
	33	#define CNTR_TO_SECS_SH 15
	34
	35	struct snvs_rtc_data {
	36	struct rtc_device *rtc;
d482893b FL	37	struct regmap *regmap;
d482893b FL	38	int offset;
179a502f	39	int irq;
7f899399	40	struct clk *clk;
179a502f SG	41	};
179a502f SG	42
cd7f3a24 TP	43	/* Read 64 bit timer register, which could be in inconsistent state */
	44	static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
	45	{
	46	u32 msb, lsb;
	47
	48	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
	49	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
	50	return (u64)msb << 32 \| lsb;
	51	}
	52
	53	/* Read the secure real time counter, taking care to deal with the cases of the
	54	* counter updating while being read.
	55	*/
d482893b	56	static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
179a502f SG	57	{
179a502f SG	58	u64 read1, read2;
cd7f3a24	59	unsigned int timeout = 100;
179a502f	60
cd7f3a24 TP	61	/* As expected, the registers might update between the read of the LSB
	62	* reg and the MSB reg. It's also possible that one register might be
	63	* in partially modified state as well.
	64	*/
	65	read1 = rtc_read_lpsrt(data);
179a502f	66	do {
cd7f3a24 TP	67	read2 = read1;
	68	read1 = rtc_read_lpsrt(data);
	69	} while (read1 != read2 && --timeout);
	70	if (!timeout)
	71	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
179a502f SG	72
	73	/* Convert 47-bit counter to 32-bit raw second count */
	74	return (u32) (read1 >> CNTR_TO_SECS_SH);
	75	}
	76
cd7f3a24 TP	77	/* Just read the lsb from the counter, dealing with inconsistent state */
cd7f3a24 TP	78	static int rtc_read_lp_counter_lsb(struct snvs_rtc_data data, u32 lsb)
179a502f	79	{
cd7f3a24 TP	80	u32 count1, count2;
	81	unsigned int timeout = 100;
	82
	83	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	84	do {
	85	count2 = count1;
	86	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
	87	} while (count1 != count2 && --timeout);
	88	if (!timeout) {
	89	dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
	90	return -ETIMEDOUT;
179a502f	91	}
cd7f3a24 TP	92
	93	*lsb = count1;
	94	return 0;
	95	}
	96
	97	static int rtc_write_sync_lp(struct snvs_rtc_data *data)
	98	{
	99	u32 count1, count2;
	100	u32 elapsed;
	101	unsigned int timeout = 1000;
	102	int ret;
	103
	104	ret = rtc_read_lp_counter_lsb(data, &count1);
	105	if (ret)
	106	return ret;
	107
	108	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
	109	do {
	110	ret = rtc_read_lp_counter_lsb(data, &count2);
	111	if (ret)
	112	return ret;
	113	elapsed = count2 - count1; /* wrap around _is_ handled! */
	114	} while (elapsed < 3 && --timeout);
	115	if (!timeout) {
	116	dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
	117	return -ETIMEDOUT;
	118	}
	119	return 0;
179a502f SG	120	}
	121
	122	static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
	123	{
179a502f SG	124	int timeout = 1000;
	125	u32 lpcr;
	126
d482893b FL	127	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
d482893b FL	128	enable ? SNVS_LPCR_SRTC_ENV : 0);
179a502f SG	129
179a502f SG	130	while (--timeout) {
d482893b	131	regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
179a502f SG	132
	133	if (enable) {
	134	if (lpcr & SNVS_LPCR_SRTC_ENV)
	135	break;
	136	} else {
	137	if (!(lpcr & SNVS_LPCR_SRTC_ENV))
	138	break;
	139	}
	140	}
	141
	142	if (!timeout)
	143	return -ETIMEDOUT;
	144
	145	return 0;
	146	}
	147
	148	static int snvs_rtc_read_time(struct device dev, struct rtc_time tm)
	149	{
	150	struct snvs_rtc_data *data = dev_get_drvdata(dev);
d482893b	151	unsigned long time = rtc_read_lp_counter(data);
179a502f SG	152
	153	rtc_time_to_tm(time, tm);
	154
	155	return 0;
	156	}
	157
	158	static int snvs_rtc_set_time(struct device dev, struct rtc_time tm)
	159	{
	160	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	161	unsigned long time;
1485991c	162	int ret;
179a502f SG	163
	164	rtc_tm_to_time(tm, &time);
	165
	166	/* Disable RTC first */
1485991c BD	167	ret = snvs_rtc_enable(data, false);
	168	if (ret)
	169	return ret;
179a502f SG	170
179a502f SG	171	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
d482893b FL	172	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
d482893b FL	173	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
179a502f SG	174
179a502f SG	175	/* Enable RTC again */
1485991c	176	ret = snvs_rtc_enable(data, true);
179a502f	177
1485991c	178	return ret;
179a502f SG	179	}
	180
	181	static int snvs_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	182	{
	183	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	184	u32 lptar, lpsr;
	185
d482893b	186	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
179a502f SG	187	rtc_time_to_tm(lptar, &alrm->time);
179a502f SG	188
d482893b	189	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	190	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
	191
	192	return 0;
	193	}
	194
	195	static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	196	{
	197	struct snvs_rtc_data *data = dev_get_drvdata(dev);
179a502f	198
d482893b FL	199	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
	200	(SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN),
	201	enable ? (SNVS_LPCR_LPTA_EN \| SNVS_LPCR_LPWUI_EN) : 0);
179a502f	202
cd7f3a24	203	return rtc_write_sync_lp(data);
179a502f SG	204	}
	205
	206	static int snvs_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	207	{
	208	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	209	struct rtc_time *alrm_tm = &alrm->time;
	210	unsigned long time;
cd7f3a24	211	int ret;
179a502f SG	212
	213	rtc_tm_to_time(alrm_tm, &time);
	214
d482893b	215	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
cd7f3a24 TP	216	ret = rtc_write_sync_lp(data);
	217	if (ret)
	218	return ret;
d482893b	219	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
179a502f SG	220
179a502f SG	221	/* Clear alarm interrupt status bit */
d482893b	222	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
179a502f SG	223
	224	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
	225	}
	226
	227	static const struct rtc_class_ops snvs_rtc_ops = {
	228	.read_time = snvs_rtc_read_time,
	229	.set_time = snvs_rtc_set_time,
	230	.read_alarm = snvs_rtc_read_alarm,
	231	.set_alarm = snvs_rtc_set_alarm,
	232	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
	233	};
	234
	235	static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
	236	{
	237	struct device *dev = dev_id;
	238	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	239	u32 lpsr;
	240	u32 events = 0;
	241
edb190cb AH	242	if (data->clk)
	243	clk_enable(data->clk);
	244
d482893b	245	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
179a502f SG	246
	247	if (lpsr & SNVS_LPSR_LPTA) {
	248	events \|= (RTC_AF \| RTC_IRQF);
	249
	250	/* RTC alarm should be one-shot */
	251	snvs_rtc_alarm_irq_enable(dev, 0);
	252
	253	rtc_update_irq(data->rtc, 1, events);
	254	}
	255
	256	/* clear interrupt status */
d482893b	257	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
179a502f	258
edb190cb AH	259	if (data->clk)
	260	clk_disable(data->clk);
	261
179a502f SG	262	return events ? IRQ_HANDLED : IRQ_NONE;
	263	}
	264
d482893b FL	265	static const struct regmap_config snvs_rtc_config = {
	266	.reg_bits = 32,
	267	.val_bits = 32,
	268	.reg_stride = 4,
	269	};
	270
5a167f45	271	static int snvs_rtc_probe(struct platform_device *pdev)
179a502f SG	272	{
	273	struct snvs_rtc_data *data;
	274	struct resource *res;
	275	int ret;
d482893b	276	void __iomem *mmio;
179a502f SG	277
	278	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	279	if (!data)
	280	return -ENOMEM;
	281
d482893b FL	282	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
	283
	284	if (IS_ERR(data->regmap)) {
	285	dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
	286	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	287
	288	mmio = devm_ioremap_resource(&pdev->dev, res);
	289	if (IS_ERR(mmio))
	290	return PTR_ERR(mmio);
	291
	292	data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
	293	} else {
	294	data->offset = SNVS_LPREGISTER_OFFSET;
	295	of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
	296	}
	297
75892900	298	if (IS_ERR(data->regmap)) {
d482893b FL	299	dev_err(&pdev->dev, "Can't find snvs syscon\n");
	300	return -ENODEV;
	301	}
179a502f SG	302
	303	data->irq = platform_get_irq(pdev, 0);
	304	if (data->irq < 0)
	305	return data->irq;
	306
7f899399 SM	307	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
	308	if (IS_ERR(data->clk)) {
	309	data->clk = NULL;
	310	} else {
	311	ret = clk_prepare_enable(data->clk);
	312	if (ret) {
	313	dev_err(&pdev->dev,
	314	"Could not prepare or enable the snvs clock\n");
	315	return ret;
	316	}
	317	}
	318
179a502f SG	319	platform_set_drvdata(pdev, data);
179a502f SG	320
179a502f	321	/* Initialize glitch detect */
d482893b	322	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
179a502f SG	323
179a502f SG	324	/* Clear interrupt status */
d482893b	325	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
179a502f SG	326
179a502f SG	327	/* Enable RTC */
1485991c BD	328	ret = snvs_rtc_enable(data, true);
	329	if (ret) {
	330	dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
	331	goto error_rtc_device_register;
	332	}
179a502f SG	333
	334	device_init_wakeup(&pdev->dev, true);
	335
	336	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
	337	IRQF_SHARED, "rtc alarm", &pdev->dev);
	338	if (ret) {
	339	dev_err(&pdev->dev, "failed to request irq %d: %d\n",
	340	data->irq, ret);
7f899399	341	goto error_rtc_device_register;
179a502f SG	342	}
179a502f SG	343
904784c1	344	data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
179a502f SG	345	&snvs_rtc_ops, THIS_MODULE);
	346	if (IS_ERR(data->rtc)) {
	347	ret = PTR_ERR(data->rtc);
	348	dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
7f899399	349	goto error_rtc_device_register;
179a502f SG	350	}
	351
	352	return 0;
7f899399 SM	353
	354	error_rtc_device_register:
	355	if (data->clk)
	356	clk_disable_unprepare(data->clk);
	357
	358	return ret;
179a502f SG	359	}
179a502f SG	360
179a502f SG	361	#ifdef CONFIG_PM_SLEEP
	362	static int snvs_rtc_suspend(struct device *dev)
	363	{
	364	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	365
	366	if (device_may_wakeup(dev))
a350259d	367	return enable_irq_wake(data->irq);
179a502f	368
119434f4 SA	369	return 0;
	370	}
	371
	372	static int snvs_rtc_suspend_noirq(struct device *dev)
	373	{
	374	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	375
7f899399 SM	376	if (data->clk)
	377	clk_disable_unprepare(data->clk);
	378
179a502f SG	379	return 0;
	380	}
	381
	382	static int snvs_rtc_resume(struct device *dev)
	383	{
	384	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	385
	386	if (device_may_wakeup(dev))
119434f4	387	return disable_irq_wake(data->irq);
179a502f	388
119434f4 SA	389	return 0;
	390	}
	391
	392	static int snvs_rtc_resume_noirq(struct device *dev)
	393	{
	394	struct snvs_rtc_data *data = dev_get_drvdata(dev);
	395
	396	if (data->clk)
	397	return clk_prepare_enable(data->clk);
7f899399	398
179a502f SG	399	return 0;
179a502f SG	400	}
179a502f	401
7654e9d4	402	static const struct dev_pm_ops snvs_rtc_pm_ops = {
119434f4 SA	403	.suspend = snvs_rtc_suspend,
	404	.suspend_noirq = snvs_rtc_suspend_noirq,
	405	.resume = snvs_rtc_resume,
	406	.resume_noirq = snvs_rtc_resume_noirq,
7654e9d4	407	};
179a502f	408
88221c32 GR	409	#define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops)
	410
	411	#else
	412
	413	#define SNVS_RTC_PM_OPS NULL
	414
	415	#endif
	416
5a167f45	417	static const struct of_device_id snvs_dt_ids[] = {
179a502f SG	418	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
	419	{ /* sentinel */ }
	420	};
	421	MODULE_DEVICE_TABLE(of, snvs_dt_ids);
	422
	423	static struct platform_driver snvs_rtc_driver = {
	424	.driver = {
	425	.name = "snvs_rtc",
88221c32	426	.pm = SNVS_RTC_PM_OPS,
c39b3717	427	.of_match_table = snvs_dt_ids,
179a502f SG	428	},
179a502f SG	429	.probe = snvs_rtc_probe,
179a502f SG	430	};
	431	module_platform_driver(snvs_rtc_driver);
	432
	433	MODULE_AUTHOR("Freescale Semiconductor, Inc.");
	434	MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
	435	MODULE_LICENSE("GPL");