[linux-2.6-block.git] / drivers / rtc / rtc-sirfsoc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * SiRFSoC Real Time Clock interface for Linux
 *
 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
 */

#include <linux/module.h>
#include <linux/err.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/rtc/sirfsoc_rtciobrg.h>


#define RTC_CN			0x00
#define RTC_ALARM0		0x04
#define RTC_ALARM1		0x18
#define RTC_STATUS		0x08
#define RTC_SW_VALUE            0x40
#define SIRFSOC_RTC_AL1E	(1<<6)
#define SIRFSOC_RTC_AL1		(1<<4)
#define SIRFSOC_RTC_HZE		(1<<3)
#define SIRFSOC_RTC_AL0E	(1<<2)
#define SIRFSOC_RTC_HZ		(1<<1)
#define SIRFSOC_RTC_AL0		(1<<0)
#define RTC_DIV			0x0c
#define RTC_DEEP_CTRL		0x14
#define RTC_CLOCK_SWITCH	0x1c
#define SIRFSOC_RTC_CLK		0x03	/* others are reserved */

/* Refer to RTC DIV switch */
#define RTC_HZ			16

/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
#define RTC_SHIFT		4

#define INTR_SYSRTC_CN		0x48

struct sirfsoc_rtc_drv {
	struct rtc_device	*rtc;
	u32			rtc_base;
	u32			irq;
	unsigned		irq_wake;
	/* Overflow for every 8 years extra time */
	u32			overflow_rtc;
	spinlock_t		lock;
	struct regmap *regmap;
#ifdef CONFIG_PM
	u32		saved_counter;
	u32		saved_overflow_rtc;
#endif
};

static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
{
	u32 val;

	regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
	return val;
}

static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
			       u32 offset, u32 val)
{
	regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
}

static int sirfsoc_rtc_read_alarm(struct device *dev,
		struct rtc_wkalrm *alrm)
{
	unsigned long rtc_alarm, rtc_count;
	struct sirfsoc_rtc_drv *rtcdrv;

	rtcdrv = dev_get_drvdata(dev);

	spin_lock_irq(&rtcdrv->lock);

	rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);

	rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
	memset(alrm, 0, sizeof(struct rtc_wkalrm));

	/*
	 * assume alarm interval not beyond one round counter overflow_rtc:
	 * 0->0xffffffff
	 */
	/* if alarm is in next overflow cycle */
	if (rtc_count > rtc_alarm)
		rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
				<< (BITS_PER_LONG - RTC_SHIFT)
				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	else
		rtc_time_to_tm(rtcdrv->overflow_rtc
				<< (BITS_PER_LONG - RTC_SHIFT)
				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
		alrm->enabled = 1;

	spin_unlock_irq(&rtcdrv->lock);

	return 0;
}

static int sirfsoc_rtc_set_alarm(struct device *dev,
		struct rtc_wkalrm *alrm)
{
	unsigned long rtc_status_reg, rtc_alarm;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);

	if (alrm->enabled) {
		rtc_tm_to_time(&(alrm->time), &rtc_alarm);

		spin_lock_irq(&rtcdrv->lock);

		rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
			/*
			 * An ongoing alarm in progress - ingore it and not
			 * to return EBUSY
			 */
			dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
		}

		sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
		rtc_status_reg &= ~0x07; /* mask out the lower status bits */
		/*
		 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
		 * Writing 1 into this bit will clear it
		 */
		rtc_status_reg |= SIRFSOC_RTC_AL0;
		/* enable the RTC alarm interrupt */
		rtc_status_reg |= SIRFSOC_RTC_AL0E;
		sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);

		spin_unlock_irq(&rtcdrv->lock);
	} else {
		/*
		 * if this function was called with enabled=0
		 * then it could mean that the application is
		 * trying to cancel an ongoing alarm
		 */
		spin_lock_irq(&rtcdrv->lock);

		rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
			/* clear the RTC status register's alarm bit */
			rtc_status_reg &= ~0x07;
			/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
			rtc_status_reg |= (SIRFSOC_RTC_AL0);
			/* Clear the Alarm enable bit */
			rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);

			sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
					   rtc_status_reg);
		}

		spin_unlock_irq(&rtcdrv->lock);
	}

	return 0;
}

static int sirfsoc_rtc_read_time(struct device *dev,
		struct rtc_time *tm)
{
	unsigned long tmp_rtc = 0;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);
	/*
	 * This patch is taken from WinCE - Need to validate this for
	 * correctness. To work around sirfsoc RTC counter double sync logic
	 * fail, read several times to make sure get stable value.
	 */
	do {
		tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
		cpu_relax();
	} while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));

	rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
					tmp_rtc >> RTC_SHIFT, tm);
	return 0;
}

static int sirfsoc_rtc_set_time(struct device *dev,
		struct rtc_time *tm)
{
	unsigned long rtc_time;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);

	rtc_tm_to_time(tm, &rtc_time);

	rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);

	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
	sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);

	return 0;
}

static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
		unsigned int enabled)
{
	unsigned long rtc_status_reg = 0x0;
	struct sirfsoc_rtc_drv *rtcdrv;

	rtcdrv = dev_get_drvdata(dev);

	spin_lock_irq(&rtcdrv->lock);

	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
	if (enabled)
		rtc_status_reg |= SIRFSOC_RTC_AL0E;
	else
		rtc_status_reg &= ~SIRFSOC_RTC_AL0E;

	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);

	spin_unlock_irq(&rtcdrv->lock);

	return 0;

}

static const struct rtc_class_ops sirfsoc_rtc_ops = {
	.read_time = sirfsoc_rtc_read_time,
	.set_time = sirfsoc_rtc_set_time,
	.read_alarm = sirfsoc_rtc_read_alarm,
	.set_alarm = sirfsoc_rtc_set_alarm,
	.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
};

static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
{
	struct sirfsoc_rtc_drv *rtcdrv = pdata;
	unsigned long rtc_status_reg = 0x0;
	unsigned long events = 0x0;

	spin_lock(&rtcdrv->lock);

	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
	/* this bit will be set ONLY if an alarm was active
	 * and it expired NOW
	 * So this is being used as an ASSERT
	 */
	if (rtc_status_reg & SIRFSOC_RTC_AL0) {
		/*
		 * clear the RTC status register's alarm bit
		 * mask out the lower status bits
		 */
		rtc_status_reg &= ~0x07;
		/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
		rtc_status_reg |= (SIRFSOC_RTC_AL0);
		/* Clear the Alarm enable bit */
		rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	}

	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);

	spin_unlock(&rtcdrv->lock);

	/* this should wake up any apps polling/waiting on the read
	 * after setting the alarm
	 */
	events |= RTC_IRQF | RTC_AF;
	rtc_update_irq(rtcdrv->rtc, 1, events);

	return IRQ_HANDLED;
}

static const struct of_device_id sirfsoc_rtc_of_match[] = {
	{ .compatible = "sirf,prima2-sysrtc"},
	{},
};

static const struct regmap_config sysrtc_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.fast_io = true,
};

MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);

static int sirfsoc_rtc_probe(struct platform_device *pdev)
{
	int err;
	unsigned long rtc_div;
	struct sirfsoc_rtc_drv *rtcdrv;
	struct device_node *np = pdev->dev.of_node;

	rtcdrv = devm_kzalloc(&pdev->dev,
		sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
	if (rtcdrv == NULL)
		return -ENOMEM;

	spin_lock_init(&rtcdrv->lock);

	err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
	if (err) {
		dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
		return err;
	}

	platform_set_drvdata(pdev, rtcdrv);

	/* Register rtc alarm as a wakeup source */
	device_init_wakeup(&pdev->dev, 1);

	rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
			&sysrtc_regmap_config);
	if (IS_ERR(rtcdrv->regmap)) {
		err = PTR_ERR(rtcdrv->regmap);
		dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
			err);
		return err;
	}

	/*
	 * Set SYS_RTC counter in RTC_HZ HZ Units
	 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	 * If 16HZ, therefore RTC_DIV = 1023;
	 */
	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
	sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);

	/* 0x3 -> RTC_CLK */
	sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);

	/* reset SYS RTC ALARM0 */
	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);

	/* reset SYS RTC ALARM1 */
	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);

	/* Restore RTC Overflow From Register After Command Reboot */
	rtcdrv->overflow_rtc =
		sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);

	rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
			&sirfsoc_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtcdrv->rtc)) {
		err = PTR_ERR(rtcdrv->rtc);
		dev_err(&pdev->dev, "can't register RTC device\n");
		return err;
	}

	rtcdrv->irq = platform_get_irq(pdev, 0);
	err = devm_request_irq(
			&pdev->dev,
			rtcdrv->irq,
			sirfsoc_rtc_irq_handler,
			IRQF_SHARED,
			pdev->name,
			rtcdrv);
	if (err) {
		dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
		return err;
	}

	return 0;
}

static int sirfsoc_rtc_remove(struct platform_device *pdev)
{
	device_init_wakeup(&pdev->dev, 0);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sirfsoc_rtc_suspend(struct device *dev)
{
	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
	rtcdrv->overflow_rtc =
		sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);

	rtcdrv->saved_counter =
		sirfsoc_rtc_readl(rtcdrv, RTC_CN);
	rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
	if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
		rtcdrv->irq_wake = 1;

	return 0;
}

static int sirfsoc_rtc_resume(struct device *dev)
{
	u32 tmp;
	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);

	/*
	 * if resume from snapshot and the rtc power is lost,
	 * restroe the rtc settings
	 */
	if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
		u32 rtc_div;
		/* 0x3 -> RTC_CLK */
		sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
		/*
		 * Set SYS_RTC counter in RTC_HZ HZ Units
		 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
		 * If 16HZ, therefore RTC_DIV = 1023;
		 */
		rtc_div = ((32768 / RTC_HZ) / 2) - 1;

		sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);

		/* reset SYS RTC ALARM0 */
		sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);

		/* reset SYS RTC ALARM1 */
		sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
	}
	rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;

	/*
	 * if current counter is small than previous,
	 * it means overflow in sleep
	 */
	tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
	if (tmp <= rtcdrv->saved_counter)
		rtcdrv->overflow_rtc++;
	/*
	 *PWRC Value Be Changed When Suspend, Restore Overflow
	 * In Memory To Register
	 */
	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);

	if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
		disable_irq_wake(rtcdrv->irq);
		rtcdrv->irq_wake = 0;
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
		sirfsoc_rtc_suspend, sirfsoc_rtc_resume);

static struct platform_driver sirfsoc_rtc_driver = {
	.driver = {
		.name = "sirfsoc-rtc",
		.pm = &sirfsoc_rtc_pm_ops,
		.of_match_table = sirfsoc_rtc_of_match,
	},
	.probe = sirfsoc_rtc_probe,
	.remove = sirfsoc_rtc_remove,
};
module_platform_driver(sirfsoc_rtc_driver);

MODULE_DESCRIPTION("SiRF SoC rtc driver");
MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:sirfsoc-rtc");
Commit	Line	Data
a636cd6c	1	// SPDX-License-Identifier: GPL-2.0-or-later
e88b815e XD	2	/*
	3	* SiRFSoC Real Time Clock interface for Linux
	4	*
	5	* Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
e88b815e XD	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/err.h>
	10	#include <linux/rtc.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/slab.h>
	13	#include <linux/io.h>
	14	#include <linux/of.h>
dfe6c04a	15	#include <linux/regmap.h>
e88b815e XD	16	#include <linux/rtc/sirfsoc_rtciobrg.h>
	17
	18
	19	#define RTC_CN 0x00
	20	#define RTC_ALARM0 0x04
	21	#define RTC_ALARM1 0x18
	22	#define RTC_STATUS 0x08
	23	#define RTC_SW_VALUE 0x40
	24	#define SIRFSOC_RTC_AL1E (1<<6)
	25	#define SIRFSOC_RTC_AL1 (1<<4)
	26	#define SIRFSOC_RTC_HZE (1<<3)
	27	#define SIRFSOC_RTC_AL0E (1<<2)
	28	#define SIRFSOC_RTC_HZ (1<<1)
	29	#define SIRFSOC_RTC_AL0 (1<<0)
	30	#define RTC_DIV 0x0c
	31	#define RTC_DEEP_CTRL 0x14
	32	#define RTC_CLOCK_SWITCH 0x1c
	33	#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
	34
	35	/* Refer to RTC DIV switch */
	36	#define RTC_HZ 16
	37
	38	/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
	39	#define RTC_SHIFT 4
	40
	41	#define INTR_SYSRTC_CN 0x48
	42
	43	struct sirfsoc_rtc_drv {
	44	struct rtc_device *rtc;
	45	u32 rtc_base;
	46	u32 irq;
28984c7d	47	unsigned irq_wake;
e88b815e XD	48	/* Overflow for every 8 years extra time */
e88b815e XD	49	u32 overflow_rtc;
e9bc7363	50	spinlock_t lock;
dfe6c04a	51	struct regmap *regmap;
e88b815e XD	52	#ifdef CONFIG_PM
	53	u32 saved_counter;
	54	u32 saved_overflow_rtc;
	55	#endif
	56	};
	57
dfe6c04a GZ	58	static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
	59	{
	60	u32 val;
	61
	62	regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
	63	return val;
	64	}
	65
	66	static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
	67	u32 offset, u32 val)
	68	{
	69	regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
	70	}
	71
e88b815e XD	72	static int sirfsoc_rtc_read_alarm(struct device *dev,
	73	struct rtc_wkalrm *alrm)
	74	{
	75	unsigned long rtc_alarm, rtc_count;
	76	struct sirfsoc_rtc_drv *rtcdrv;
	77
b7efdf3b	78	rtcdrv = dev_get_drvdata(dev);
e88b815e	79
e9bc7363	80	spin_lock_irq(&rtcdrv->lock);
e88b815e	81
dfe6c04a	82	rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e	83
dfe6c04a	84	rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
e88b815e XD	85	memset(alrm, 0, sizeof(struct rtc_wkalrm));
	86
	87	/*
	88	* assume alarm interval not beyond one round counter overflow_rtc:
	89	* 0->0xffffffff
	90	*/
	91	/* if alarm is in next overflow cycle */
	92	if (rtc_count > rtc_alarm)
	93	rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
	94	<< (BITS_PER_LONG - RTC_SHIFT)
	95	\| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	96	else
	97	rtc_time_to_tm(rtcdrv->overflow_rtc
	98	<< (BITS_PER_LONG - RTC_SHIFT)
	99	\| rtc_alarm >> RTC_SHIFT, &(alrm->time));
dfe6c04a	100	if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
e88b815e	101	alrm->enabled = 1;
e9bc7363 BS	102
e9bc7363 BS	103	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	104
	105	return 0;
	106	}
	107
	108	static int sirfsoc_rtc_set_alarm(struct device *dev,
	109	struct rtc_wkalrm *alrm)
	110	{
	111	unsigned long rtc_status_reg, rtc_alarm;
	112	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	113	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	114
	115	if (alrm->enabled) {
	116	rtc_tm_to_time(&(alrm->time), &rtc_alarm);
	117
e9bc7363	118	spin_lock_irq(&rtcdrv->lock);
e88b815e	119
dfe6c04a	120	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
e88b815e XD	121	if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
	122	/*
	123	* An ongoing alarm in progress - ingore it and not
	124	* to return EBUSY
	125	*/
	126	dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
	127	}
	128
dfe6c04a	129	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
e88b815e XD	130	rtc_status_reg &= ~0x07; /* mask out the lower status bits */
	131	/*
	132	* This bit RTC_AL sets it as a wake-up source for Sleep Mode
	133	* Writing 1 into this bit will clear it
	134	*/
	135	rtc_status_reg \|= SIRFSOC_RTC_AL0;
	136	/* enable the RTC alarm interrupt */
	137	rtc_status_reg \|= SIRFSOC_RTC_AL0E;
dfe6c04a	138	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
e9bc7363 BS	139
e9bc7363 BS	140	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	141	} else {
	142	/*
	143	* if this function was called with enabled=0
	144	* then it could mean that the application is
	145	* trying to cancel an ongoing alarm
	146	*/
e9bc7363	147	spin_lock_irq(&rtcdrv->lock);
e88b815e	148
dfe6c04a	149	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
e88b815e XD	150	if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
	151	/* clear the RTC status register's alarm bit */
	152	rtc_status_reg &= ~0x07;
	153	/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
	154	rtc_status_reg \|= (SIRFSOC_RTC_AL0);
	155	/* Clear the Alarm enable bit */
	156	rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	157
dfe6c04a GZ	158	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
dfe6c04a GZ	159	rtc_status_reg);
e88b815e XD	160	}
e88b815e XD	161
e9bc7363	162	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	163	}
	164
	165	return 0;
	166	}
	167
	168	static int sirfsoc_rtc_read_time(struct device *dev,
	169	struct rtc_time *tm)
	170	{
	171	unsigned long tmp_rtc = 0;
	172	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	173	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	174	/*
	175	* This patch is taken from WinCE - Need to validate this for
	176	* correctness. To work around sirfsoc RTC counter double sync logic
	177	* fail, read several times to make sure get stable value.
	178	*/
	179	do {
dfe6c04a	180	tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e	181	cpu_relax();
dfe6c04a	182	} while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
e88b815e XD	183
	184	rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) \|
	185	tmp_rtc >> RTC_SHIFT, tm);
	186	return 0;
	187	}
	188
	189	static int sirfsoc_rtc_set_time(struct device *dev,
	190	struct rtc_time *tm)
	191	{
	192	unsigned long rtc_time;
	193	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	194	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	195
	196	rtc_tm_to_time(tm, &rtc_time);
	197
	198	rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
	199
dfe6c04a GZ	200	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
dfe6c04a GZ	201	sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
e88b815e XD	202
	203	return 0;
	204	}
	205
09e427f8	206	static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
	207	unsigned int enabled)
	208	{
	209	unsigned long rtc_status_reg = 0x0;
	210	struct sirfsoc_rtc_drv *rtcdrv;
	211
	212	rtcdrv = dev_get_drvdata(dev);
	213
e9bc7363	214	spin_lock_irq(&rtcdrv->lock);
09e427f8	215
dfe6c04a	216	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
09e427f8	217	if (enabled)
	218	rtc_status_reg \|= SIRFSOC_RTC_AL0E;
	219	else
	220	rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
	221
dfe6c04a	222	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
e9bc7363 BS	223
e9bc7363 BS	224	spin_unlock_irq(&rtcdrv->lock);
09e427f8	225
	226	return 0;
	227
	228	}
	229
e88b815e XD	230	static const struct rtc_class_ops sirfsoc_rtc_ops = {
	231	.read_time = sirfsoc_rtc_read_time,
	232	.set_time = sirfsoc_rtc_set_time,
	233	.read_alarm = sirfsoc_rtc_read_alarm,
	234	.set_alarm = sirfsoc_rtc_set_alarm,
09e427f8	235	.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
e88b815e XD	236	};
	237
	238	static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
	239	{
	240	struct sirfsoc_rtc_drv *rtcdrv = pdata;
	241	unsigned long rtc_status_reg = 0x0;
	242	unsigned long events = 0x0;
	243
e9bc7363 BS	244	spin_lock(&rtcdrv->lock);
e9bc7363 BS	245
dfe6c04a	246	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
e88b815e XD	247	/* this bit will be set ONLY if an alarm was active
	248	* and it expired NOW
	249	* So this is being used as an ASSERT
	250	*/
	251	if (rtc_status_reg & SIRFSOC_RTC_AL0) {
	252	/*
	253	* clear the RTC status register's alarm bit
	254	* mask out the lower status bits
	255	*/
	256	rtc_status_reg &= ~0x07;
	257	/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
	258	rtc_status_reg \|= (SIRFSOC_RTC_AL0);
	259	/* Clear the Alarm enable bit */
	260	rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	261	}
dfe6c04a GZ	262
dfe6c04a GZ	263	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
e9bc7363 BS	264
	265	spin_unlock(&rtcdrv->lock);
	266
e88b815e XD	267	/* this should wake up any apps polling/waiting on the read
	268	* after setting the alarm
	269	*/
	270	events \|= RTC_IRQF \| RTC_AF;
	271	rtc_update_irq(rtcdrv->rtc, 1, events);
	272
	273	return IRQ_HANDLED;
	274	}
	275
	276	static const struct of_device_id sirfsoc_rtc_of_match[] = {
	277	{ .compatible = "sirf,prima2-sysrtc"},
	278	{},
	279	};
dfe6c04a	280
153a9177	281	static const struct regmap_config sysrtc_regmap_config = {
dfe6c04a GZ	282	.reg_bits = 32,
	283	.val_bits = 32,
	284	.fast_io = true,
	285	};
	286
e88b815e XD	287	MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
	288
	289	static int sirfsoc_rtc_probe(struct platform_device *pdev)
	290	{
	291	int err;
	292	unsigned long rtc_div;
	293	struct sirfsoc_rtc_drv *rtcdrv;
	294	struct device_node *np = pdev->dev.of_node;
	295
	296	rtcdrv = devm_kzalloc(&pdev->dev,
	297	sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
98e2d21f	298	if (rtcdrv == NULL)
e88b815e	299	return -ENOMEM;
e88b815e	300
e9bc7363 BS	301	spin_lock_init(&rtcdrv->lock);
e9bc7363 BS	302
e88b815e XD	303	err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
	304	if (err) {
	305	dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
3d09162e	306	return err;
e88b815e XD	307	}
	308
	309	platform_set_drvdata(pdev, rtcdrv);
	310
	311	/* Register rtc alarm as a wakeup source */
	312	device_init_wakeup(&pdev->dev, 1);
	313
dfe6c04a GZ	314	rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
	315	&sysrtc_regmap_config);
	316	if (IS_ERR(rtcdrv->regmap)) {
	317	err = PTR_ERR(rtcdrv->regmap);
	318	dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
	319	err);
	320	return err;
	321	}
	322
e88b815e XD	323	/*
	324	* Set SYS_RTC counter in RTC_HZ HZ Units
	325	* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	326	* If 16HZ, therefore RTC_DIV = 1023;
	327	*/
	328	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
dfe6c04a	329	sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
e88b815e	330
e88b815e	331	/* 0x3 -> RTC_CLK */
dfe6c04a	332	sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
e88b815e XD	333
e88b815e XD	334	/* reset SYS RTC ALARM0 */
dfe6c04a	335	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
e88b815e XD	336
e88b815e XD	337	/* reset SYS RTC ALARM1 */
dfe6c04a	338	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
e88b815e XD	339
	340	/* Restore RTC Overflow From Register After Command Reboot */
	341	rtcdrv->overflow_rtc =
dfe6c04a	342	sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
e88b815e	343
0e953255 GZ	344	rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
	345	&sirfsoc_rtc_ops, THIS_MODULE);
	346	if (IS_ERR(rtcdrv->rtc)) {
	347	err = PTR_ERR(rtcdrv->rtc);
	348	dev_err(&pdev->dev, "can't register RTC device\n");
	349	return err;
	350	}
	351
e88b815e XD	352	rtcdrv->irq = platform_get_irq(pdev, 0);
	353	err = devm_request_irq(
	354	&pdev->dev,
	355	rtcdrv->irq,
	356	sirfsoc_rtc_irq_handler,
	357	IRQF_SHARED,
	358	pdev->name,
	359	rtcdrv);
	360	if (err) {
	361	dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
3d09162e	362	return err;
e88b815e XD	363	}
	364
	365	return 0;
e88b815e XD	366	}
	367
	368	static int sirfsoc_rtc_remove(struct platform_device *pdev)
	369	{
e88b815e	370	device_init_wakeup(&pdev->dev, 0);
e88b815e XD	371
	372	return 0;
	373	}
	374
3916b09e	375	#ifdef CONFIG_PM_SLEEP
e88b815e XD	376	static int sirfsoc_rtc_suspend(struct device *dev)
e88b815e XD	377	{
3916b09e	378	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
e88b815e	379	rtcdrv->overflow_rtc =
dfe6c04a	380	sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
e88b815e XD	381
e88b815e XD	382	rtcdrv->saved_counter =
dfe6c04a	383	sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e	384	rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
3916b09e	385	if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
28984c7d	386	rtcdrv->irq_wake = 1;
e88b815e XD	387
	388	return 0;
	389	}
	390
3916b09e	391	static int sirfsoc_rtc_resume(struct device *dev)
e88b815e XD	392	{
e88b815e XD	393	u32 tmp;
3916b09e	394	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
e88b815e XD	395
e88b815e XD	396	/*
3916b09e	397	* if resume from snapshot and the rtc power is lost,
e88b815e XD	398	* restroe the rtc settings
e88b815e XD	399	*/
dfe6c04a	400	if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
e88b815e XD	401	u32 rtc_div;
e88b815e XD	402	/* 0x3 -> RTC_CLK */
dfe6c04a	403	sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
e88b815e XD	404	/*
	405	* Set SYS_RTC counter in RTC_HZ HZ Units
	406	* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	407	* If 16HZ, therefore RTC_DIV = 1023;
	408	*/
	409	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
	410
dfe6c04a	411	sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
e88b815e XD	412
e88b815e XD	413	/* reset SYS RTC ALARM0 */
dfe6c04a	414	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
e88b815e XD	415
e88b815e XD	416	/* reset SYS RTC ALARM1 */
dfe6c04a	417	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
e88b815e XD	418	}
	419	rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
	420
	421	/*
	422	* if current counter is small than previous,
	423	* it means overflow in sleep
	424	*/
dfe6c04a	425	tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e XD	426	if (tmp <= rtcdrv->saved_counter)
	427	rtcdrv->overflow_rtc++;
	428	/*
	429	*PWRC Value Be Changed When Suspend, Restore Overflow
	430	* In Memory To Register
	431	*/
dfe6c04a	432	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
e88b815e	433
3916b09e	434	if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
e88b815e	435	disable_irq_wake(rtcdrv->irq);
28984c7d XD	436	rtcdrv->irq_wake = 0;
28984c7d XD	437	}
e88b815e XD	438
	439	return 0;
	440	}
e88b815e XD	441	#endif
e88b815e XD	442
3916b09e XD	443	static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
3916b09e XD	444	sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
e88b815e XD	445
	446	static struct platform_driver sirfsoc_rtc_driver = {
	447	.driver = {
	448	.name = "sirfsoc-rtc",
e88b815e	449	.pm = &sirfsoc_rtc_pm_ops,
d149632e	450	.of_match_table = sirfsoc_rtc_of_match,
e88b815e XD	451	},
	452	.probe = sirfsoc_rtc_probe,
	453	.remove = sirfsoc_rtc_remove,
	454	};
	455	module_platform_driver(sirfsoc_rtc_driver);
	456
	457	MODULE_DESCRIPTION("SiRF SoC rtc driver");
	458	MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
	459	MODULE_LICENSE("GPL v2");
	460	MODULE_ALIAS("platform:sirfsoc-rtc");