[linux-2.6-block.git] / drivers / rtc / rtc-sirfsoc.c

/*
 * SiRFSoC Real Time Clock interface for Linux
 *
 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/err.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/rtc/sirfsoc_rtciobrg.h>


#define RTC_CN			0x00
#define RTC_ALARM0		0x04
#define RTC_ALARM1		0x18
#define RTC_STATUS		0x08
#define RTC_SW_VALUE            0x40
#define SIRFSOC_RTC_AL1E	(1<<6)
#define SIRFSOC_RTC_AL1		(1<<4)
#define SIRFSOC_RTC_HZE		(1<<3)
#define SIRFSOC_RTC_AL0E	(1<<2)
#define SIRFSOC_RTC_HZ		(1<<1)
#define SIRFSOC_RTC_AL0		(1<<0)
#define RTC_DIV			0x0c
#define RTC_DEEP_CTRL		0x14
#define RTC_CLOCK_SWITCH	0x1c
#define SIRFSOC_RTC_CLK		0x03	/* others are reserved */

/* Refer to RTC DIV switch */
#define RTC_HZ			16

/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
#define RTC_SHIFT		4

#define INTR_SYSRTC_CN		0x48

struct sirfsoc_rtc_drv {
	struct rtc_device	*rtc;
	u32			rtc_base;
	u32			irq;
	unsigned		irq_wake;
	/* Overflow for every 8 years extra time */
	u32			overflow_rtc;
	spinlock_t		lock;
	struct regmap *regmap;
#ifdef CONFIG_PM
	u32		saved_counter;
	u32		saved_overflow_rtc;
#endif
};

static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
{
	u32 val;

	regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
	return val;
}

static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
			       u32 offset, u32 val)
{
	regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
}

static int sirfsoc_rtc_read_alarm(struct device *dev,
		struct rtc_wkalrm *alrm)
{
	unsigned long rtc_alarm, rtc_count;
	struct sirfsoc_rtc_drv *rtcdrv;

	rtcdrv = dev_get_drvdata(dev);

	spin_lock_irq(&rtcdrv->lock);

	rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);

	rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
	memset(alrm, 0, sizeof(struct rtc_wkalrm));

	/*
	 * assume alarm interval not beyond one round counter overflow_rtc:
	 * 0->0xffffffff
	 */
	/* if alarm is in next overflow cycle */
	if (rtc_count > rtc_alarm)
		rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
				<< (BITS_PER_LONG - RTC_SHIFT)
				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	else
		rtc_time_to_tm(rtcdrv->overflow_rtc
				<< (BITS_PER_LONG - RTC_SHIFT)
				| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
		alrm->enabled = 1;

	spin_unlock_irq(&rtcdrv->lock);

	return 0;
}

static int sirfsoc_rtc_set_alarm(struct device *dev,
		struct rtc_wkalrm *alrm)
{
	unsigned long rtc_status_reg, rtc_alarm;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);

	if (alrm->enabled) {
		rtc_tm_to_time(&(alrm->time), &rtc_alarm);

		spin_lock_irq(&rtcdrv->lock);

		rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
			/*
			 * An ongoing alarm in progress - ingore it and not
			 * to return EBUSY
			 */
			dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
		}

		sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
		rtc_status_reg &= ~0x07; /* mask out the lower status bits */
		/*
		 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
		 * Writing 1 into this bit will clear it
		 */
		rtc_status_reg |= SIRFSOC_RTC_AL0;
		/* enable the RTC alarm interrupt */
		rtc_status_reg |= SIRFSOC_RTC_AL0E;
		sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);

		spin_unlock_irq(&rtcdrv->lock);
	} else {
		/*
		 * if this function was called with enabled=0
		 * then it could mean that the application is
		 * trying to cancel an ongoing alarm
		 */
		spin_lock_irq(&rtcdrv->lock);

		rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
		if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
			/* clear the RTC status register's alarm bit */
			rtc_status_reg &= ~0x07;
			/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
			rtc_status_reg |= (SIRFSOC_RTC_AL0);
			/* Clear the Alarm enable bit */
			rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);

			sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
					   rtc_status_reg);
		}

		spin_unlock_irq(&rtcdrv->lock);
	}

	return 0;
}

static int sirfsoc_rtc_read_time(struct device *dev,
		struct rtc_time *tm)
{
	unsigned long tmp_rtc = 0;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);
	/*
	 * This patch is taken from WinCE - Need to validate this for
	 * correctness. To work around sirfsoc RTC counter double sync logic
	 * fail, read several times to make sure get stable value.
	 */
	do {
		tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
		cpu_relax();
	} while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));

	rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
					tmp_rtc >> RTC_SHIFT, tm);
	return 0;
}

static int sirfsoc_rtc_set_time(struct device *dev,
		struct rtc_time *tm)
{
	unsigned long rtc_time;
	struct sirfsoc_rtc_drv *rtcdrv;
	rtcdrv = dev_get_drvdata(dev);

	rtc_tm_to_time(tm, &rtc_time);

	rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);

	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
	sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);

	return 0;
}

static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
		unsigned int enabled)
{
	unsigned long rtc_status_reg = 0x0;
	struct sirfsoc_rtc_drv *rtcdrv;

	rtcdrv = dev_get_drvdata(dev);

	spin_lock_irq(&rtcdrv->lock);

	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
	if (enabled)
		rtc_status_reg |= SIRFSOC_RTC_AL0E;
	else
		rtc_status_reg &= ~SIRFSOC_RTC_AL0E;

	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);

	spin_unlock_irq(&rtcdrv->lock);

	return 0;

}

static const struct rtc_class_ops sirfsoc_rtc_ops = {
	.read_time = sirfsoc_rtc_read_time,
	.set_time = sirfsoc_rtc_set_time,
	.read_alarm = sirfsoc_rtc_read_alarm,
	.set_alarm = sirfsoc_rtc_set_alarm,
	.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
};

static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
{
	struct sirfsoc_rtc_drv *rtcdrv = pdata;
	unsigned long rtc_status_reg = 0x0;
	unsigned long events = 0x0;

	spin_lock(&rtcdrv->lock);

	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
	/* this bit will be set ONLY if an alarm was active
	 * and it expired NOW
	 * So this is being used as an ASSERT
	 */
	if (rtc_status_reg & SIRFSOC_RTC_AL0) {
		/*
		 * clear the RTC status register's alarm bit
		 * mask out the lower status bits
		 */
		rtc_status_reg &= ~0x07;
		/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
		rtc_status_reg |= (SIRFSOC_RTC_AL0);
		/* Clear the Alarm enable bit */
		rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	}

	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);

	spin_unlock(&rtcdrv->lock);

	/* this should wake up any apps polling/waiting on the read
	 * after setting the alarm
	 */
	events |= RTC_IRQF | RTC_AF;
	rtc_update_irq(rtcdrv->rtc, 1, events);

	return IRQ_HANDLED;
}

static const struct of_device_id sirfsoc_rtc_of_match[] = {
	{ .compatible = "sirf,prima2-sysrtc"},
	{},
};

const struct regmap_config sysrtc_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.fast_io = true,
};

MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);

static int sirfsoc_rtc_probe(struct platform_device *pdev)
{
	int err;
	unsigned long rtc_div;
	struct sirfsoc_rtc_drv *rtcdrv;
	struct device_node *np = pdev->dev.of_node;

	rtcdrv = devm_kzalloc(&pdev->dev,
		sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
	if (rtcdrv == NULL)
		return -ENOMEM;

	spin_lock_init(&rtcdrv->lock);

	err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
	if (err) {
		dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
		return err;
	}

	platform_set_drvdata(pdev, rtcdrv);

	/* Register rtc alarm as a wakeup source */
	device_init_wakeup(&pdev->dev, 1);

	rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
			&sysrtc_regmap_config);
	if (IS_ERR(rtcdrv->regmap)) {
		err = PTR_ERR(rtcdrv->regmap);
		dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
			err);
		return err;
	}

	/*
	 * Set SYS_RTC counter in RTC_HZ HZ Units
	 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	 * If 16HZ, therefore RTC_DIV = 1023;
	 */
	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
	sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);

	/* 0x3 -> RTC_CLK */
	sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);

	/* reset SYS RTC ALARM0 */
	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);

	/* reset SYS RTC ALARM1 */
	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);

	/* Restore RTC Overflow From Register After Command Reboot */
	rtcdrv->overflow_rtc =
		sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);

	rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
			&sirfsoc_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtcdrv->rtc)) {
		err = PTR_ERR(rtcdrv->rtc);
		dev_err(&pdev->dev, "can't register RTC device\n");
		return err;
	}

	rtcdrv->irq = platform_get_irq(pdev, 0);
	err = devm_request_irq(
			&pdev->dev,
			rtcdrv->irq,
			sirfsoc_rtc_irq_handler,
			IRQF_SHARED,
			pdev->name,
			rtcdrv);
	if (err) {
		dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
		return err;
	}

	return 0;
}

static int sirfsoc_rtc_remove(struct platform_device *pdev)
{
	device_init_wakeup(&pdev->dev, 0);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sirfsoc_rtc_suspend(struct device *dev)
{
	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
	rtcdrv->overflow_rtc =
		sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);

	rtcdrv->saved_counter =
		sirfsoc_rtc_readl(rtcdrv, RTC_CN);
	rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
	if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
		rtcdrv->irq_wake = 1;

	return 0;
}

static int sirfsoc_rtc_resume(struct device *dev)
{
	u32 tmp;
	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);

	/*
	 * if resume from snapshot and the rtc power is lost,
	 * restroe the rtc settings
	 */
	if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
		u32 rtc_div;
		/* 0x3 -> RTC_CLK */
		sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
		/*
		 * Set SYS_RTC counter in RTC_HZ HZ Units
		 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
		 * If 16HZ, therefore RTC_DIV = 1023;
		 */
		rtc_div = ((32768 / RTC_HZ) / 2) - 1;

		sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);

		/* reset SYS RTC ALARM0 */
		sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);

		/* reset SYS RTC ALARM1 */
		sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
	}
	rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;

	/*
	 * if current counter is small than previous,
	 * it means overflow in sleep
	 */
	tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
	if (tmp <= rtcdrv->saved_counter)
		rtcdrv->overflow_rtc++;
	/*
	 *PWRC Value Be Changed When Suspend, Restore Overflow
	 * In Memory To Register
	 */
	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);

	if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
		disable_irq_wake(rtcdrv->irq);
		rtcdrv->irq_wake = 0;
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
		sirfsoc_rtc_suspend, sirfsoc_rtc_resume);

static struct platform_driver sirfsoc_rtc_driver = {
	.driver = {
		.name = "sirfsoc-rtc",
		.pm = &sirfsoc_rtc_pm_ops,
		.of_match_table = sirfsoc_rtc_of_match,
	},
	.probe = sirfsoc_rtc_probe,
	.remove = sirfsoc_rtc_remove,
};
module_platform_driver(sirfsoc_rtc_driver);

MODULE_DESCRIPTION("SiRF SoC rtc driver");
MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:sirfsoc-rtc");
Commit	Line	Data
e88b815e XD	1	/*
	2	* SiRFSoC Real Time Clock interface for Linux
	3	*
	4	* Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/err.h>
	11	#include <linux/rtc.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/slab.h>
	14	#include <linux/io.h>
	15	#include <linux/of.h>
dfe6c04a	16	#include <linux/regmap.h>
e88b815e XD	17	#include <linux/rtc/sirfsoc_rtciobrg.h>
	18
	19
	20	#define RTC_CN 0x00
	21	#define RTC_ALARM0 0x04
	22	#define RTC_ALARM1 0x18
	23	#define RTC_STATUS 0x08
	24	#define RTC_SW_VALUE 0x40
	25	#define SIRFSOC_RTC_AL1E (1<<6)
	26	#define SIRFSOC_RTC_AL1 (1<<4)
	27	#define SIRFSOC_RTC_HZE (1<<3)
	28	#define SIRFSOC_RTC_AL0E (1<<2)
	29	#define SIRFSOC_RTC_HZ (1<<1)
	30	#define SIRFSOC_RTC_AL0 (1<<0)
	31	#define RTC_DIV 0x0c
	32	#define RTC_DEEP_CTRL 0x14
	33	#define RTC_CLOCK_SWITCH 0x1c
	34	#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
	35
	36	/* Refer to RTC DIV switch */
	37	#define RTC_HZ 16
	38
	39	/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
	40	#define RTC_SHIFT 4
	41
	42	#define INTR_SYSRTC_CN 0x48
	43
	44	struct sirfsoc_rtc_drv {
	45	struct rtc_device *rtc;
	46	u32 rtc_base;
	47	u32 irq;
28984c7d	48	unsigned irq_wake;
e88b815e XD	49	/* Overflow for every 8 years extra time */
e88b815e XD	50	u32 overflow_rtc;
e9bc7363	51	spinlock_t lock;
dfe6c04a	52	struct regmap *regmap;
e88b815e XD	53	#ifdef CONFIG_PM
	54	u32 saved_counter;
	55	u32 saved_overflow_rtc;
	56	#endif
	57	};
	58
dfe6c04a GZ	59	static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
	60	{
	61	u32 val;
	62
	63	regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
	64	return val;
	65	}
	66
	67	static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
	68	u32 offset, u32 val)
	69	{
	70	regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
	71	}
	72
e88b815e XD	73	static int sirfsoc_rtc_read_alarm(struct device *dev,
	74	struct rtc_wkalrm *alrm)
	75	{
	76	unsigned long rtc_alarm, rtc_count;
	77	struct sirfsoc_rtc_drv *rtcdrv;
	78
b7efdf3b	79	rtcdrv = dev_get_drvdata(dev);
e88b815e	80
e9bc7363	81	spin_lock_irq(&rtcdrv->lock);
e88b815e	82
dfe6c04a	83	rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e	84
dfe6c04a	85	rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
e88b815e XD	86	memset(alrm, 0, sizeof(struct rtc_wkalrm));
	87
	88	/*
	89	* assume alarm interval not beyond one round counter overflow_rtc:
	90	* 0->0xffffffff
	91	*/
	92	/* if alarm is in next overflow cycle */
	93	if (rtc_count > rtc_alarm)
	94	rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
	95	<< (BITS_PER_LONG - RTC_SHIFT)
	96	\| rtc_alarm >> RTC_SHIFT, &(alrm->time));
	97	else
	98	rtc_time_to_tm(rtcdrv->overflow_rtc
	99	<< (BITS_PER_LONG - RTC_SHIFT)
	100	\| rtc_alarm >> RTC_SHIFT, &(alrm->time));
dfe6c04a	101	if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
e88b815e	102	alrm->enabled = 1;
e9bc7363 BS	103
e9bc7363 BS	104	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	105
	106	return 0;
	107	}
	108
	109	static int sirfsoc_rtc_set_alarm(struct device *dev,
	110	struct rtc_wkalrm *alrm)
	111	{
	112	unsigned long rtc_status_reg, rtc_alarm;
	113	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	114	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	115
	116	if (alrm->enabled) {
	117	rtc_tm_to_time(&(alrm->time), &rtc_alarm);
	118
e9bc7363	119	spin_lock_irq(&rtcdrv->lock);
e88b815e	120
dfe6c04a	121	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
e88b815e XD	122	if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
	123	/*
	124	* An ongoing alarm in progress - ingore it and not
	125	* to return EBUSY
	126	*/
	127	dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
	128	}
	129
dfe6c04a	130	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
e88b815e XD	131	rtc_status_reg &= ~0x07; /* mask out the lower status bits */
	132	/*
	133	* This bit RTC_AL sets it as a wake-up source for Sleep Mode
	134	* Writing 1 into this bit will clear it
	135	*/
	136	rtc_status_reg \|= SIRFSOC_RTC_AL0;
	137	/* enable the RTC alarm interrupt */
	138	rtc_status_reg \|= SIRFSOC_RTC_AL0E;
dfe6c04a	139	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
e9bc7363 BS	140
e9bc7363 BS	141	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	142	} else {
	143	/*
	144	* if this function was called with enabled=0
	145	* then it could mean that the application is
	146	* trying to cancel an ongoing alarm
	147	*/
e9bc7363	148	spin_lock_irq(&rtcdrv->lock);
e88b815e	149
dfe6c04a	150	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
e88b815e XD	151	if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
	152	/* clear the RTC status register's alarm bit */
	153	rtc_status_reg &= ~0x07;
	154	/* write 1 into SIRFSOC_RTC_AL0 to force a clear */
	155	rtc_status_reg \|= (SIRFSOC_RTC_AL0);
	156	/* Clear the Alarm enable bit */
	157	rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	158
dfe6c04a GZ	159	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
dfe6c04a GZ	160	rtc_status_reg);
e88b815e XD	161	}
e88b815e XD	162
e9bc7363	163	spin_unlock_irq(&rtcdrv->lock);
e88b815e XD	164	}
	165
	166	return 0;
	167	}
	168
	169	static int sirfsoc_rtc_read_time(struct device *dev,
	170	struct rtc_time *tm)
	171	{
	172	unsigned long tmp_rtc = 0;
	173	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	174	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	175	/*
	176	* This patch is taken from WinCE - Need to validate this for
	177	* correctness. To work around sirfsoc RTC counter double sync logic
	178	* fail, read several times to make sure get stable value.
	179	*/
	180	do {
dfe6c04a	181	tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e	182	cpu_relax();
dfe6c04a	183	} while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
e88b815e XD	184
	185	rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) \|
	186	tmp_rtc >> RTC_SHIFT, tm);
	187	return 0;
	188	}
	189
	190	static int sirfsoc_rtc_set_time(struct device *dev,
	191	struct rtc_time *tm)
	192	{
	193	unsigned long rtc_time;
	194	struct sirfsoc_rtc_drv *rtcdrv;
b7efdf3b	195	rtcdrv = dev_get_drvdata(dev);
e88b815e XD	196
	197	rtc_tm_to_time(tm, &rtc_time);
	198
	199	rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
	200
dfe6c04a GZ	201	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
dfe6c04a GZ	202	sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
e88b815e XD	203
	204	return 0;
	205	}
	206
09e427f8	207	static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
	208	unsigned int enabled)
	209	{
	210	unsigned long rtc_status_reg = 0x0;
	211	struct sirfsoc_rtc_drv *rtcdrv;
	212
	213	rtcdrv = dev_get_drvdata(dev);
	214
e9bc7363	215	spin_lock_irq(&rtcdrv->lock);
09e427f8	216
dfe6c04a	217	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
09e427f8	218	if (enabled)
	219	rtc_status_reg \|= SIRFSOC_RTC_AL0E;
	220	else
	221	rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
	222
dfe6c04a	223	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
e9bc7363 BS	224
e9bc7363 BS	225	spin_unlock_irq(&rtcdrv->lock);
09e427f8	226
	227	return 0;
	228
	229	}
	230
e88b815e XD	231	static const struct rtc_class_ops sirfsoc_rtc_ops = {
	232	.read_time = sirfsoc_rtc_read_time,
	233	.set_time = sirfsoc_rtc_set_time,
	234	.read_alarm = sirfsoc_rtc_read_alarm,
	235	.set_alarm = sirfsoc_rtc_set_alarm,
09e427f8	236	.alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
e88b815e XD	237	};
	238
	239	static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
	240	{
	241	struct sirfsoc_rtc_drv *rtcdrv = pdata;
	242	unsigned long rtc_status_reg = 0x0;
	243	unsigned long events = 0x0;
	244
e9bc7363 BS	245	spin_lock(&rtcdrv->lock);
e9bc7363 BS	246
dfe6c04a	247	rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
e88b815e XD	248	/* this bit will be set ONLY if an alarm was active
	249	* and it expired NOW
	250	* So this is being used as an ASSERT
	251	*/
	252	if (rtc_status_reg & SIRFSOC_RTC_AL0) {
	253	/*
	254	* clear the RTC status register's alarm bit
	255	* mask out the lower status bits
	256	*/
	257	rtc_status_reg &= ~0x07;
	258	/* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
	259	rtc_status_reg \|= (SIRFSOC_RTC_AL0);
	260	/* Clear the Alarm enable bit */
	261	rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
	262	}
dfe6c04a GZ	263
dfe6c04a GZ	264	sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
e9bc7363 BS	265
	266	spin_unlock(&rtcdrv->lock);
	267
e88b815e XD	268	/* this should wake up any apps polling/waiting on the read
	269	* after setting the alarm
	270	*/
	271	events \|= RTC_IRQF \| RTC_AF;
	272	rtc_update_irq(rtcdrv->rtc, 1, events);
	273
	274	return IRQ_HANDLED;
	275	}
	276
	277	static const struct of_device_id sirfsoc_rtc_of_match[] = {
	278	{ .compatible = "sirf,prima2-sysrtc"},
	279	{},
	280	};
dfe6c04a GZ	281
	282	const struct regmap_config sysrtc_regmap_config = {
	283	.reg_bits = 32,
	284	.val_bits = 32,
	285	.fast_io = true,
	286	};
	287
e88b815e XD	288	MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
	289
	290	static int sirfsoc_rtc_probe(struct platform_device *pdev)
	291	{
	292	int err;
	293	unsigned long rtc_div;
	294	struct sirfsoc_rtc_drv *rtcdrv;
	295	struct device_node *np = pdev->dev.of_node;
	296
	297	rtcdrv = devm_kzalloc(&pdev->dev,
	298	sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
98e2d21f	299	if (rtcdrv == NULL)
e88b815e	300	return -ENOMEM;
e88b815e	301
e9bc7363 BS	302	spin_lock_init(&rtcdrv->lock);
e9bc7363 BS	303
e88b815e XD	304	err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
	305	if (err) {
	306	dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
3d09162e	307	return err;
e88b815e XD	308	}
	309
	310	platform_set_drvdata(pdev, rtcdrv);
	311
	312	/* Register rtc alarm as a wakeup source */
	313	device_init_wakeup(&pdev->dev, 1);
	314
dfe6c04a GZ	315	rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
	316	&sysrtc_regmap_config);
	317	if (IS_ERR(rtcdrv->regmap)) {
	318	err = PTR_ERR(rtcdrv->regmap);
	319	dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
	320	err);
	321	return err;
	322	}
	323
e88b815e XD	324	/*
	325	* Set SYS_RTC counter in RTC_HZ HZ Units
	326	* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	327	* If 16HZ, therefore RTC_DIV = 1023;
	328	*/
	329	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
dfe6c04a	330	sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
e88b815e	331
e88b815e	332	/* 0x3 -> RTC_CLK */
dfe6c04a	333	sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
e88b815e XD	334
e88b815e XD	335	/* reset SYS RTC ALARM0 */
dfe6c04a	336	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
e88b815e XD	337
e88b815e XD	338	/* reset SYS RTC ALARM1 */
dfe6c04a	339	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
e88b815e XD	340
	341	/* Restore RTC Overflow From Register After Command Reboot */
	342	rtcdrv->overflow_rtc =
dfe6c04a	343	sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
e88b815e	344
0e953255 GZ	345	rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
	346	&sirfsoc_rtc_ops, THIS_MODULE);
	347	if (IS_ERR(rtcdrv->rtc)) {
	348	err = PTR_ERR(rtcdrv->rtc);
	349	dev_err(&pdev->dev, "can't register RTC device\n");
	350	return err;
	351	}
	352
e88b815e XD	353	rtcdrv->irq = platform_get_irq(pdev, 0);
	354	err = devm_request_irq(
	355	&pdev->dev,
	356	rtcdrv->irq,
	357	sirfsoc_rtc_irq_handler,
	358	IRQF_SHARED,
	359	pdev->name,
	360	rtcdrv);
	361	if (err) {
	362	dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
3d09162e	363	return err;
e88b815e XD	364	}
	365
	366	return 0;
e88b815e XD	367	}
	368
	369	static int sirfsoc_rtc_remove(struct platform_device *pdev)
	370	{
e88b815e	371	device_init_wakeup(&pdev->dev, 0);
e88b815e XD	372
	373	return 0;
	374	}
	375
3916b09e	376	#ifdef CONFIG_PM_SLEEP
e88b815e XD	377	static int sirfsoc_rtc_suspend(struct device *dev)
e88b815e XD	378	{
3916b09e	379	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
e88b815e	380	rtcdrv->overflow_rtc =
dfe6c04a	381	sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
e88b815e XD	382
e88b815e XD	383	rtcdrv->saved_counter =
dfe6c04a	384	sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e	385	rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
3916b09e	386	if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
28984c7d	387	rtcdrv->irq_wake = 1;
e88b815e XD	388
	389	return 0;
	390	}
	391
3916b09e	392	static int sirfsoc_rtc_resume(struct device *dev)
e88b815e XD	393	{
e88b815e XD	394	u32 tmp;
3916b09e	395	struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
e88b815e XD	396
e88b815e XD	397	/*
3916b09e	398	* if resume from snapshot and the rtc power is lost,
e88b815e XD	399	* restroe the rtc settings
e88b815e XD	400	*/
dfe6c04a	401	if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
e88b815e XD	402	u32 rtc_div;
e88b815e XD	403	/* 0x3 -> RTC_CLK */
dfe6c04a	404	sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
e88b815e XD	405	/*
	406	* Set SYS_RTC counter in RTC_HZ HZ Units
	407	* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
	408	* If 16HZ, therefore RTC_DIV = 1023;
	409	*/
	410	rtc_div = ((32768 / RTC_HZ) / 2) - 1;
	411
dfe6c04a	412	sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
e88b815e XD	413
e88b815e XD	414	/* reset SYS RTC ALARM0 */
dfe6c04a	415	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
e88b815e XD	416
e88b815e XD	417	/* reset SYS RTC ALARM1 */
dfe6c04a	418	sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
e88b815e XD	419	}
	420	rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
	421
	422	/*
	423	* if current counter is small than previous,
	424	* it means overflow in sleep
	425	*/
dfe6c04a	426	tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
e88b815e XD	427	if (tmp <= rtcdrv->saved_counter)
	428	rtcdrv->overflow_rtc++;
	429	/*
	430	*PWRC Value Be Changed When Suspend, Restore Overflow
	431	* In Memory To Register
	432	*/
dfe6c04a	433	sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
e88b815e	434
3916b09e	435	if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
e88b815e	436	disable_irq_wake(rtcdrv->irq);
28984c7d XD	437	rtcdrv->irq_wake = 0;
28984c7d XD	438	}
e88b815e XD	439
	440	return 0;
	441	}
e88b815e XD	442	#endif
e88b815e XD	443
3916b09e XD	444	static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
3916b09e XD	445	sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
e88b815e XD	446
	447	static struct platform_driver sirfsoc_rtc_driver = {
	448	.driver = {
	449	.name = "sirfsoc-rtc",
e88b815e	450	.pm = &sirfsoc_rtc_pm_ops,
d149632e	451	.of_match_table = sirfsoc_rtc_of_match,
e88b815e XD	452	},
	453	.probe = sirfsoc_rtc_probe,
	454	.remove = sirfsoc_rtc_remove,
	455	};
	456	module_platform_driver(sirfsoc_rtc_driver);
	457
	458	MODULE_DESCRIPTION("SiRF SoC rtc driver");
	459	MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
	460	MODULE_LICENSE("GPL v2");
	461	MODULE_ALIAS("platform:sirfsoc-rtc");