Commit | Line | Data |
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317a6104 PM |
1 | /* |
2 | * SuperH On-Chip RTC Support | |
3 | * | |
b420b1a7 | 4 | * Copyright (C) 2006, 2007, 2008 Paul Mundt |
1b73e6ae | 5 | * Copyright (C) 2006 Jamie Lenehan |
b420b1a7 | 6 | * Copyright (C) 2008 Angelo Castello |
317a6104 PM |
7 | * |
8 | * Based on the old arch/sh/kernel/cpu/rtc.c by: | |
9 | * | |
10 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> | |
11 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka | |
12 | * | |
13 | * This file is subject to the terms and conditions of the GNU General Public | |
14 | * License. See the file "COPYING" in the main directory of this archive | |
15 | * for more details. | |
16 | */ | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/bcd.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/seq_file.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spinlock.h> | |
31ccb081 | 26 | #include <linux/io.h> |
5d2a5037 | 27 | #include <linux/log2.h> |
ad89f87a | 28 | #include <asm/rtc.h> |
317a6104 | 29 | |
1b73e6ae | 30 | #define DRV_NAME "sh-rtc" |
b420b1a7 | 31 | #define DRV_VERSION "0.2.0" |
317a6104 PM |
32 | |
33 | #define RTC_REG(r) ((r) * rtc_reg_size) | |
34 | ||
31ccb081 | 35 | #define R64CNT RTC_REG(0) |
1b73e6ae JL |
36 | |
37 | #define RSECCNT RTC_REG(1) /* RTC sec */ | |
38 | #define RMINCNT RTC_REG(2) /* RTC min */ | |
39 | #define RHRCNT RTC_REG(3) /* RTC hour */ | |
40 | #define RWKCNT RTC_REG(4) /* RTC week */ | |
41 | #define RDAYCNT RTC_REG(5) /* RTC day */ | |
42 | #define RMONCNT RTC_REG(6) /* RTC month */ | |
43 | #define RYRCNT RTC_REG(7) /* RTC year */ | |
44 | #define RSECAR RTC_REG(8) /* ALARM sec */ | |
45 | #define RMINAR RTC_REG(9) /* ALARM min */ | |
46 | #define RHRAR RTC_REG(10) /* ALARM hour */ | |
47 | #define RWKAR RTC_REG(11) /* ALARM week */ | |
48 | #define RDAYAR RTC_REG(12) /* ALARM day */ | |
49 | #define RMONAR RTC_REG(13) /* ALARM month */ | |
50 | #define RCR1 RTC_REG(14) /* Control */ | |
51 | #define RCR2 RTC_REG(15) /* Control */ | |
52 | ||
ff1b7506 PM |
53 | /* |
54 | * Note on RYRAR and RCR3: Up until this point most of the register | |
55 | * definitions are consistent across all of the available parts. However, | |
56 | * the placement of the optional RYRAR and RCR3 (the RYRAR control | |
57 | * register used to control RYRCNT/RYRAR compare) varies considerably | |
58 | * across various parts, occasionally being mapped in to a completely | |
59 | * unrelated address space. For proper RYRAR support a separate resource | |
60 | * would have to be handed off, but as this is purely optional in | |
61 | * practice, we simply opt not to support it, thereby keeping the code | |
62 | * quite a bit more simplified. | |
63 | */ | |
64 | ||
1b73e6ae JL |
65 | /* ALARM Bits - or with BCD encoded value */ |
66 | #define AR_ENB 0x80 /* Enable for alarm cmp */ | |
317a6104 | 67 | |
b420b1a7 AC |
68 | /* Period Bits */ |
69 | #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ | |
70 | #define PF_COUNT 0x200 /* Half periodic counter */ | |
71 | #define PF_OXS 0x400 /* Periodic One x Second */ | |
72 | #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ | |
73 | #define PF_MASK 0xf00 | |
74 | ||
317a6104 PM |
75 | /* RCR1 Bits */ |
76 | #define RCR1_CF 0x80 /* Carry Flag */ | |
77 | #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ | |
78 | #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ | |
79 | #define RCR1_AF 0x01 /* Alarm Flag */ | |
80 | ||
81 | /* RCR2 Bits */ | |
82 | #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ | |
83 | #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ | |
84 | #define RCR2_RTCEN 0x08 /* ENable RTC */ | |
85 | #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ | |
86 | #define RCR2_RESET 0x02 /* Reset bit */ | |
87 | #define RCR2_START 0x01 /* Start bit */ | |
88 | ||
89 | struct sh_rtc { | |
90 | void __iomem *regbase; | |
91 | unsigned long regsize; | |
92 | struct resource *res; | |
2fac6674 AV |
93 | int alarm_irq; |
94 | int periodic_irq; | |
95 | int carry_irq; | |
317a6104 PM |
96 | struct rtc_device *rtc_dev; |
97 | spinlock_t lock; | |
ad89f87a | 98 | unsigned long capabilities; /* See asm-sh/rtc.h for cap bits */ |
b420b1a7 | 99 | unsigned short periodic_freq; |
317a6104 PM |
100 | }; |
101 | ||
5e084a15 | 102 | static int __sh_rtc_interrupt(struct sh_rtc *rtc) |
317a6104 | 103 | { |
5e084a15 | 104 | unsigned int tmp, pending; |
317a6104 PM |
105 | |
106 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 107 | pending = tmp & RCR1_CF; |
1b73e6ae | 108 | tmp &= ~RCR1_CF; |
317a6104 PM |
109 | writeb(tmp, rtc->regbase + RCR1); |
110 | ||
b420b1a7 | 111 | /* Users have requested One x Second IRQ */ |
5e084a15 | 112 | if (pending && rtc->periodic_freq & PF_OXS) |
b420b1a7 | 113 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); |
317a6104 | 114 | |
5e084a15 | 115 | return pending; |
317a6104 PM |
116 | } |
117 | ||
5e084a15 | 118 | static int __sh_rtc_alarm(struct sh_rtc *rtc) |
1b73e6ae | 119 | { |
5e084a15 | 120 | unsigned int tmp, pending; |
1b73e6ae JL |
121 | |
122 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 123 | pending = tmp & RCR1_AF; |
b420b1a7 | 124 | tmp &= ~(RCR1_AF | RCR1_AIE); |
5e084a15 | 125 | writeb(tmp, rtc->regbase + RCR1); |
1b73e6ae | 126 | |
5e084a15 MD |
127 | if (pending) |
128 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); | |
b420b1a7 | 129 | |
5e084a15 | 130 | return pending; |
1b73e6ae JL |
131 | } |
132 | ||
5e084a15 | 133 | static int __sh_rtc_periodic(struct sh_rtc *rtc) |
317a6104 | 134 | { |
b420b1a7 | 135 | struct rtc_device *rtc_dev = rtc->rtc_dev; |
5e084a15 MD |
136 | struct rtc_task *irq_task; |
137 | unsigned int tmp, pending; | |
317a6104 | 138 | |
b420b1a7 | 139 | tmp = readb(rtc->regbase + RCR2); |
5e084a15 | 140 | pending = tmp & RCR2_PEF; |
b420b1a7 AC |
141 | tmp &= ~RCR2_PEF; |
142 | writeb(tmp, rtc->regbase + RCR2); | |
143 | ||
5e084a15 MD |
144 | if (!pending) |
145 | return 0; | |
146 | ||
b420b1a7 AC |
147 | /* Half period enabled than one skipped and the next notified */ |
148 | if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) | |
149 | rtc->periodic_freq &= ~PF_COUNT; | |
150 | else { | |
151 | if (rtc->periodic_freq & PF_HP) | |
152 | rtc->periodic_freq |= PF_COUNT; | |
153 | if (rtc->periodic_freq & PF_KOU) { | |
154 | spin_lock(&rtc_dev->irq_task_lock); | |
5e084a15 MD |
155 | irq_task = rtc_dev->irq_task; |
156 | if (irq_task) | |
157 | irq_task->func(irq_task->private_data); | |
b420b1a7 AC |
158 | spin_unlock(&rtc_dev->irq_task_lock); |
159 | } else | |
160 | rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); | |
161 | } | |
317a6104 | 162 | |
5e084a15 MD |
163 | return pending; |
164 | } | |
165 | ||
166 | static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) | |
167 | { | |
168 | struct sh_rtc *rtc = dev_id; | |
169 | int ret; | |
170 | ||
171 | spin_lock(&rtc->lock); | |
172 | ret = __sh_rtc_interrupt(rtc); | |
173 | spin_unlock(&rtc->lock); | |
174 | ||
175 | return IRQ_RETVAL(ret); | |
176 | } | |
177 | ||
178 | static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) | |
179 | { | |
180 | struct sh_rtc *rtc = dev_id; | |
181 | int ret; | |
182 | ||
183 | spin_lock(&rtc->lock); | |
184 | ret = __sh_rtc_alarm(rtc); | |
185 | spin_unlock(&rtc->lock); | |
186 | ||
187 | return IRQ_RETVAL(ret); | |
188 | } | |
189 | ||
190 | static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) | |
191 | { | |
192 | struct sh_rtc *rtc = dev_id; | |
193 | int ret; | |
194 | ||
195 | spin_lock(&rtc->lock); | |
196 | ret = __sh_rtc_periodic(rtc); | |
317a6104 PM |
197 | spin_unlock(&rtc->lock); |
198 | ||
5e084a15 MD |
199 | return IRQ_RETVAL(ret); |
200 | } | |
201 | ||
202 | static irqreturn_t sh_rtc_shared(int irq, void *dev_id) | |
203 | { | |
204 | struct sh_rtc *rtc = dev_id; | |
205 | int ret; | |
206 | ||
207 | spin_lock(&rtc->lock); | |
208 | ret = __sh_rtc_interrupt(rtc); | |
209 | ret |= __sh_rtc_alarm(rtc); | |
210 | ret |= __sh_rtc_periodic(rtc); | |
211 | spin_unlock(&rtc->lock); | |
212 | ||
213 | return IRQ_RETVAL(ret); | |
317a6104 PM |
214 | } |
215 | ||
216 | static inline void sh_rtc_setpie(struct device *dev, unsigned int enable) | |
217 | { | |
218 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
219 | unsigned int tmp; | |
220 | ||
221 | spin_lock_irq(&rtc->lock); | |
222 | ||
223 | tmp = readb(rtc->regbase + RCR2); | |
224 | ||
225 | if (enable) { | |
b420b1a7 AC |
226 | tmp &= ~RCR2_PEF; /* Clear PES bit */ |
227 | tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ | |
317a6104 PM |
228 | } else |
229 | tmp &= ~(RCR2_PESMASK | RCR2_PEF); | |
230 | ||
231 | writeb(tmp, rtc->regbase + RCR2); | |
232 | ||
233 | spin_unlock_irq(&rtc->lock); | |
234 | } | |
235 | ||
b420b1a7 | 236 | static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq) |
317a6104 PM |
237 | { |
238 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
b420b1a7 | 239 | int tmp, ret = 0; |
317a6104 PM |
240 | |
241 | spin_lock_irq(&rtc->lock); | |
b420b1a7 | 242 | tmp = rtc->periodic_freq & PF_MASK; |
317a6104 | 243 | |
b420b1a7 AC |
244 | switch (freq) { |
245 | case 0: | |
246 | rtc->periodic_freq = 0x00; | |
247 | break; | |
248 | case 1: | |
249 | rtc->periodic_freq = 0x60; | |
250 | break; | |
251 | case 2: | |
252 | rtc->periodic_freq = 0x50; | |
253 | break; | |
254 | case 4: | |
255 | rtc->periodic_freq = 0x40; | |
256 | break; | |
257 | case 8: | |
258 | rtc->periodic_freq = 0x30 | PF_HP; | |
259 | break; | |
260 | case 16: | |
261 | rtc->periodic_freq = 0x30; | |
262 | break; | |
263 | case 32: | |
264 | rtc->periodic_freq = 0x20 | PF_HP; | |
265 | break; | |
266 | case 64: | |
267 | rtc->periodic_freq = 0x20; | |
268 | break; | |
269 | case 128: | |
270 | rtc->periodic_freq = 0x10 | PF_HP; | |
271 | break; | |
272 | case 256: | |
273 | rtc->periodic_freq = 0x10; | |
274 | break; | |
275 | default: | |
276 | ret = -ENOTSUPP; | |
277 | } | |
317a6104 | 278 | |
b420b1a7 AC |
279 | if (ret == 0) { |
280 | rtc->periodic_freq |= tmp; | |
281 | rtc->rtc_dev->irq_freq = freq; | |
282 | } | |
317a6104 PM |
283 | |
284 | spin_unlock_irq(&rtc->lock); | |
b420b1a7 | 285 | return ret; |
317a6104 PM |
286 | } |
287 | ||
b420b1a7 | 288 | static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) |
317a6104 PM |
289 | { |
290 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
291 | unsigned int tmp; | |
317a6104 | 292 | |
b420b1a7 | 293 | spin_lock_irq(&rtc->lock); |
317a6104 | 294 | |
b420b1a7 | 295 | tmp = readb(rtc->regbase + RCR1); |
317a6104 | 296 | |
b420b1a7 AC |
297 | if (!enable) |
298 | tmp &= ~RCR1_AIE; | |
299 | else | |
300 | tmp |= RCR1_AIE; | |
317a6104 | 301 | |
b420b1a7 | 302 | writeb(tmp, rtc->regbase + RCR1); |
317a6104 | 303 | |
b420b1a7 | 304 | spin_unlock_irq(&rtc->lock); |
317a6104 PM |
305 | } |
306 | ||
317a6104 PM |
307 | static int sh_rtc_proc(struct device *dev, struct seq_file *seq) |
308 | { | |
309 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
310 | unsigned int tmp; | |
311 | ||
312 | tmp = readb(rtc->regbase + RCR1); | |
b420b1a7 | 313 | seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); |
317a6104 PM |
314 | |
315 | tmp = readb(rtc->regbase + RCR2); | |
316 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
b420b1a7 | 317 | (tmp & RCR2_PESMASK) ? "yes" : "no"); |
317a6104 PM |
318 | |
319 | return 0; | |
320 | } | |
321 | ||
322 | static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
323 | { | |
b420b1a7 AC |
324 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
325 | unsigned int ret = 0; | |
317a6104 PM |
326 | |
327 | switch (cmd) { | |
328 | case RTC_PIE_OFF: | |
329 | case RTC_PIE_ON: | |
330 | sh_rtc_setpie(dev, cmd == RTC_PIE_ON); | |
317a6104 PM |
331 | break; |
332 | case RTC_AIE_OFF: | |
333 | case RTC_AIE_ON: | |
334 | sh_rtc_setaie(dev, cmd == RTC_AIE_ON); | |
317a6104 | 335 | break; |
b420b1a7 AC |
336 | case RTC_UIE_OFF: |
337 | rtc->periodic_freq &= ~PF_OXS; | |
338 | break; | |
339 | case RTC_UIE_ON: | |
340 | rtc->periodic_freq |= PF_OXS; | |
341 | break; | |
342 | case RTC_IRQP_READ: | |
343 | ret = put_user(rtc->rtc_dev->irq_freq, | |
344 | (unsigned long __user *)arg); | |
345 | break; | |
346 | case RTC_IRQP_SET: | |
347 | ret = sh_rtc_setfreq(dev, arg); | |
348 | break; | |
349 | default: | |
350 | ret = -ENOIOCTLCMD; | |
317a6104 PM |
351 | } |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
356 | static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
357 | { | |
358 | struct platform_device *pdev = to_platform_device(dev); | |
359 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
360 | unsigned int sec128, sec2, yr, yr100, cf_bit; | |
361 | ||
362 | do { | |
363 | unsigned int tmp; | |
364 | ||
365 | spin_lock_irq(&rtc->lock); | |
366 | ||
367 | tmp = readb(rtc->regbase + RCR1); | |
368 | tmp &= ~RCR1_CF; /* Clear CF-bit */ | |
369 | tmp |= RCR1_CIE; | |
370 | writeb(tmp, rtc->regbase + RCR1); | |
371 | ||
372 | sec128 = readb(rtc->regbase + R64CNT); | |
373 | ||
fe20ba70 AB |
374 | tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); |
375 | tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); | |
376 | tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); | |
377 | tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); | |
378 | tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); | |
379 | tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; | |
317a6104 | 380 | |
ad89f87a PM |
381 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
382 | yr = readw(rtc->regbase + RYRCNT); | |
fe20ba70 | 383 | yr100 = bcd2bin(yr >> 8); |
ad89f87a PM |
384 | yr &= 0xff; |
385 | } else { | |
386 | yr = readb(rtc->regbase + RYRCNT); | |
fe20ba70 | 387 | yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); |
ad89f87a | 388 | } |
317a6104 | 389 | |
fe20ba70 | 390 | tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; |
317a6104 PM |
391 | |
392 | sec2 = readb(rtc->regbase + R64CNT); | |
393 | cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; | |
394 | ||
395 | spin_unlock_irq(&rtc->lock); | |
396 | } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); | |
397 | ||
398 | #if RTC_BIT_INVERTED != 0 | |
399 | if ((sec128 & RTC_BIT_INVERTED)) | |
400 | tm->tm_sec--; | |
401 | #endif | |
402 | ||
435c55d1 | 403 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
317a6104 | 404 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 405 | __func__, |
317a6104 | 406 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
a1614796 | 407 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); |
317a6104 | 408 | |
0ac554b9 | 409 | if (rtc_valid_tm(tm) < 0) { |
317a6104 | 410 | dev_err(dev, "invalid date\n"); |
0ac554b9 PM |
411 | rtc_time_to_tm(0, tm); |
412 | } | |
317a6104 PM |
413 | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
418 | { | |
419 | struct platform_device *pdev = to_platform_device(dev); | |
420 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
421 | unsigned int tmp; | |
422 | int year; | |
423 | ||
424 | spin_lock_irq(&rtc->lock); | |
425 | ||
426 | /* Reset pre-scaler & stop RTC */ | |
427 | tmp = readb(rtc->regbase + RCR2); | |
428 | tmp |= RCR2_RESET; | |
699bc661 | 429 | tmp &= ~RCR2_START; |
317a6104 PM |
430 | writeb(tmp, rtc->regbase + RCR2); |
431 | ||
fe20ba70 AB |
432 | writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); |
433 | writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); | |
434 | writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); | |
435 | writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); | |
436 | writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); | |
437 | writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); | |
317a6104 | 438 | |
ad89f87a | 439 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
fe20ba70 AB |
440 | year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | |
441 | bin2bcd(tm->tm_year % 100); | |
ad89f87a PM |
442 | writew(year, rtc->regbase + RYRCNT); |
443 | } else { | |
444 | year = tm->tm_year % 100; | |
fe20ba70 | 445 | writeb(bin2bcd(year), rtc->regbase + RYRCNT); |
ad89f87a | 446 | } |
317a6104 PM |
447 | |
448 | /* Start RTC */ | |
449 | tmp = readb(rtc->regbase + RCR2); | |
450 | tmp &= ~RCR2_RESET; | |
451 | tmp |= RCR2_RTCEN | RCR2_START; | |
452 | writeb(tmp, rtc->regbase + RCR2); | |
453 | ||
454 | spin_unlock_irq(&rtc->lock); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
1b73e6ae JL |
459 | static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) |
460 | { | |
461 | unsigned int byte; | |
462 | int value = 0xff; /* return 0xff for ignored values */ | |
463 | ||
464 | byte = readb(rtc->regbase + reg_off); | |
465 | if (byte & AR_ENB) { | |
466 | byte &= ~AR_ENB; /* strip the enable bit */ | |
fe20ba70 | 467 | value = bcd2bin(byte); |
1b73e6ae JL |
468 | } |
469 | ||
470 | return value; | |
471 | } | |
472 | ||
473 | static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
474 | { | |
475 | struct platform_device *pdev = to_platform_device(dev); | |
476 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
b420b1a7 | 477 | struct rtc_time *tm = &wkalrm->time; |
1b73e6ae JL |
478 | |
479 | spin_lock_irq(&rtc->lock); | |
480 | ||
481 | tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); | |
482 | tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); | |
483 | tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); | |
484 | tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); | |
485 | tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); | |
486 | tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); | |
487 | if (tm->tm_mon > 0) | |
488 | tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ | |
489 | tm->tm_year = 0xffff; | |
490 | ||
0d103e90 DB |
491 | wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; |
492 | ||
1b73e6ae JL |
493 | spin_unlock_irq(&rtc->lock); |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, | |
499 | int value, int reg_off) | |
500 | { | |
501 | /* < 0 for a value that is ignored */ | |
502 | if (value < 0) | |
503 | writeb(0, rtc->regbase + reg_off); | |
504 | else | |
fe20ba70 | 505 | writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); |
1b73e6ae JL |
506 | } |
507 | ||
b420b1a7 | 508 | static int sh_rtc_check_alarm(struct rtc_time *tm) |
1b73e6ae JL |
509 | { |
510 | /* | |
511 | * The original rtc says anything > 0xc0 is "don't care" or "match | |
512 | * all" - most users use 0xff but rtc-dev uses -1 for the same thing. | |
513 | * The original rtc doesn't support years - some things use -1 and | |
514 | * some 0xffff. We use -1 to make out tests easier. | |
515 | */ | |
516 | if (tm->tm_year == 0xffff) | |
517 | tm->tm_year = -1; | |
518 | if (tm->tm_mon >= 0xff) | |
519 | tm->tm_mon = -1; | |
520 | if (tm->tm_mday >= 0xff) | |
521 | tm->tm_mday = -1; | |
522 | if (tm->tm_wday >= 0xff) | |
523 | tm->tm_wday = -1; | |
524 | if (tm->tm_hour >= 0xff) | |
525 | tm->tm_hour = -1; | |
526 | if (tm->tm_min >= 0xff) | |
527 | tm->tm_min = -1; | |
528 | if (tm->tm_sec >= 0xff) | |
529 | tm->tm_sec = -1; | |
530 | ||
531 | if (tm->tm_year > 9999 || | |
532 | tm->tm_mon >= 12 || | |
533 | tm->tm_mday == 0 || tm->tm_mday >= 32 || | |
534 | tm->tm_wday >= 7 || | |
535 | tm->tm_hour >= 24 || | |
536 | tm->tm_min >= 60 || | |
537 | tm->tm_sec >= 60) | |
538 | return -EINVAL; | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
544 | { | |
545 | struct platform_device *pdev = to_platform_device(dev); | |
546 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
547 | unsigned int rcr1; | |
548 | struct rtc_time *tm = &wkalrm->time; | |
549 | int mon, err; | |
550 | ||
551 | err = sh_rtc_check_alarm(tm); | |
552 | if (unlikely(err < 0)) | |
553 | return err; | |
554 | ||
555 | spin_lock_irq(&rtc->lock); | |
556 | ||
15c945c3 | 557 | /* disable alarm interrupt and clear the alarm flag */ |
1b73e6ae | 558 | rcr1 = readb(rtc->regbase + RCR1); |
b420b1a7 | 559 | rcr1 &= ~(RCR1_AF | RCR1_AIE); |
15c945c3 | 560 | writeb(rcr1, rtc->regbase + RCR1); |
1b73e6ae | 561 | |
1b73e6ae JL |
562 | /* set alarm time */ |
563 | sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); | |
564 | sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); | |
565 | sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); | |
566 | sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); | |
567 | sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); | |
568 | mon = tm->tm_mon; | |
569 | if (mon >= 0) | |
570 | mon += 1; | |
571 | sh_rtc_write_alarm_value(rtc, mon, RMONAR); | |
572 | ||
15c945c3 JL |
573 | if (wkalrm->enabled) { |
574 | rcr1 |= RCR1_AIE; | |
575 | writeb(rcr1, rtc->regbase + RCR1); | |
576 | } | |
1b73e6ae JL |
577 | |
578 | spin_unlock_irq(&rtc->lock); | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
b420b1a7 AC |
583 | static int sh_rtc_irq_set_state(struct device *dev, int enabled) |
584 | { | |
585 | struct platform_device *pdev = to_platform_device(dev); | |
586 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
587 | ||
588 | if (enabled) { | |
589 | rtc->periodic_freq |= PF_KOU; | |
590 | return sh_rtc_ioctl(dev, RTC_PIE_ON, 0); | |
591 | } else { | |
592 | rtc->periodic_freq &= ~PF_KOU; | |
593 | return sh_rtc_ioctl(dev, RTC_PIE_OFF, 0); | |
594 | } | |
595 | } | |
596 | ||
597 | static int sh_rtc_irq_set_freq(struct device *dev, int freq) | |
598 | { | |
5d2a5037 JC |
599 | if (!is_power_of_2(freq)) |
600 | return -EINVAL; | |
b420b1a7 AC |
601 | return sh_rtc_ioctl(dev, RTC_IRQP_SET, freq); |
602 | } | |
603 | ||
317a6104 | 604 | static struct rtc_class_ops sh_rtc_ops = { |
317a6104 PM |
605 | .ioctl = sh_rtc_ioctl, |
606 | .read_time = sh_rtc_read_time, | |
607 | .set_time = sh_rtc_set_time, | |
1b73e6ae JL |
608 | .read_alarm = sh_rtc_read_alarm, |
609 | .set_alarm = sh_rtc_set_alarm, | |
b420b1a7 AC |
610 | .irq_set_state = sh_rtc_irq_set_state, |
611 | .irq_set_freq = sh_rtc_irq_set_freq, | |
317a6104 PM |
612 | .proc = sh_rtc_proc, |
613 | }; | |
614 | ||
615 | static int __devinit sh_rtc_probe(struct platform_device *pdev) | |
616 | { | |
617 | struct sh_rtc *rtc; | |
618 | struct resource *res; | |
b420b1a7 | 619 | unsigned int tmp; |
2641dc92 | 620 | int ret; |
317a6104 PM |
621 | |
622 | rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL); | |
623 | if (unlikely(!rtc)) | |
624 | return -ENOMEM; | |
625 | ||
626 | spin_lock_init(&rtc->lock); | |
627 | ||
b420b1a7 | 628 | /* get periodic/carry/alarm irqs */ |
2641dc92 | 629 | ret = platform_get_irq(pdev, 0); |
2fac6674 | 630 | if (unlikely(ret <= 0)) { |
2641dc92 | 631 | ret = -ENOENT; |
5e084a15 | 632 | dev_err(&pdev->dev, "No IRQ resource\n"); |
317a6104 PM |
633 | goto err_badres; |
634 | } | |
2641dc92 | 635 | rtc->periodic_irq = ret; |
5e084a15 MD |
636 | rtc->carry_irq = platform_get_irq(pdev, 1); |
637 | rtc->alarm_irq = platform_get_irq(pdev, 2); | |
317a6104 PM |
638 | |
639 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
640 | if (unlikely(res == NULL)) { | |
2641dc92 | 641 | ret = -ENOENT; |
317a6104 PM |
642 | dev_err(&pdev->dev, "No IO resource\n"); |
643 | goto err_badres; | |
644 | } | |
645 | ||
646 | rtc->regsize = res->end - res->start + 1; | |
647 | ||
648 | rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name); | |
649 | if (unlikely(!rtc->res)) { | |
650 | ret = -EBUSY; | |
651 | goto err_badres; | |
652 | } | |
653 | ||
0305794c | 654 | rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize); |
317a6104 PM |
655 | if (unlikely(!rtc->regbase)) { |
656 | ret = -EINVAL; | |
657 | goto err_badmap; | |
658 | } | |
659 | ||
660 | rtc->rtc_dev = rtc_device_register("sh", &pdev->dev, | |
661 | &sh_rtc_ops, THIS_MODULE); | |
29dd0dae | 662 | if (IS_ERR(rtc->rtc_dev)) { |
317a6104 | 663 | ret = PTR_ERR(rtc->rtc_dev); |
0305794c | 664 | goto err_unmap; |
317a6104 PM |
665 | } |
666 | ||
ad89f87a PM |
667 | rtc->capabilities = RTC_DEF_CAPABILITIES; |
668 | if (pdev->dev.platform_data) { | |
669 | struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; | |
670 | ||
671 | /* | |
672 | * Some CPUs have special capabilities in addition to the | |
673 | * default set. Add those in here. | |
674 | */ | |
675 | rtc->capabilities |= pinfo->capabilities; | |
676 | } | |
677 | ||
b420b1a7 AC |
678 | rtc->rtc_dev->max_user_freq = 256; |
679 | rtc->rtc_dev->irq_freq = 1; | |
680 | rtc->periodic_freq = 0x60; | |
681 | ||
317a6104 PM |
682 | platform_set_drvdata(pdev, rtc); |
683 | ||
5e084a15 MD |
684 | if (rtc->carry_irq <= 0) { |
685 | /* register shared periodic/carry/alarm irq */ | |
686 | ret = request_irq(rtc->periodic_irq, sh_rtc_shared, | |
687 | IRQF_DISABLED, "sh-rtc", rtc); | |
688 | if (unlikely(ret)) { | |
689 | dev_err(&pdev->dev, | |
690 | "request IRQ failed with %d, IRQ %d\n", ret, | |
691 | rtc->periodic_irq); | |
692 | goto err_unmap; | |
693 | } | |
694 | } else { | |
695 | /* register periodic/carry/alarm irqs */ | |
696 | ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, | |
697 | IRQF_DISABLED, "sh-rtc period", rtc); | |
698 | if (unlikely(ret)) { | |
699 | dev_err(&pdev->dev, | |
700 | "request period IRQ failed with %d, IRQ %d\n", | |
701 | ret, rtc->periodic_irq); | |
702 | goto err_unmap; | |
703 | } | |
b420b1a7 | 704 | |
5e084a15 MD |
705 | ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, |
706 | IRQF_DISABLED, "sh-rtc carry", rtc); | |
707 | if (unlikely(ret)) { | |
708 | dev_err(&pdev->dev, | |
709 | "request carry IRQ failed with %d, IRQ %d\n", | |
710 | ret, rtc->carry_irq); | |
711 | free_irq(rtc->periodic_irq, rtc); | |
712 | goto err_unmap; | |
713 | } | |
b420b1a7 | 714 | |
5e084a15 MD |
715 | ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, |
716 | IRQF_DISABLED, "sh-rtc alarm", rtc); | |
717 | if (unlikely(ret)) { | |
718 | dev_err(&pdev->dev, | |
719 | "request alarm IRQ failed with %d, IRQ %d\n", | |
720 | ret, rtc->alarm_irq); | |
721 | free_irq(rtc->carry_irq, rtc); | |
722 | free_irq(rtc->periodic_irq, rtc); | |
723 | goto err_unmap; | |
724 | } | |
b420b1a7 AC |
725 | } |
726 | ||
727 | tmp = readb(rtc->regbase + RCR1); | |
728 | tmp &= ~RCR1_CF; | |
729 | tmp |= RCR1_CIE; | |
730 | writeb(tmp, rtc->regbase + RCR1); | |
731 | ||
317a6104 PM |
732 | return 0; |
733 | ||
0305794c PM |
734 | err_unmap: |
735 | iounmap(rtc->regbase); | |
317a6104 PM |
736 | err_badmap: |
737 | release_resource(rtc->res); | |
738 | err_badres: | |
739 | kfree(rtc); | |
740 | ||
741 | return ret; | |
742 | } | |
743 | ||
744 | static int __devexit sh_rtc_remove(struct platform_device *pdev) | |
745 | { | |
746 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
747 | ||
748 | if (likely(rtc->rtc_dev)) | |
749 | rtc_device_unregister(rtc->rtc_dev); | |
750 | ||
751 | sh_rtc_setpie(&pdev->dev, 0); | |
752 | sh_rtc_setaie(&pdev->dev, 0); | |
753 | ||
b420b1a7 | 754 | free_irq(rtc->periodic_irq, rtc); |
5e084a15 MD |
755 | if (rtc->carry_irq > 0) { |
756 | free_irq(rtc->carry_irq, rtc); | |
757 | free_irq(rtc->alarm_irq, rtc); | |
758 | } | |
b420b1a7 | 759 | |
317a6104 PM |
760 | release_resource(rtc->res); |
761 | ||
0305794c PM |
762 | iounmap(rtc->regbase); |
763 | ||
317a6104 PM |
764 | platform_set_drvdata(pdev, NULL); |
765 | ||
766 | kfree(rtc); | |
767 | ||
768 | return 0; | |
769 | } | |
770 | static struct platform_driver sh_rtc_platform_driver = { | |
771 | .driver = { | |
1b73e6ae | 772 | .name = DRV_NAME, |
317a6104 PM |
773 | .owner = THIS_MODULE, |
774 | }, | |
775 | .probe = sh_rtc_probe, | |
776 | .remove = __devexit_p(sh_rtc_remove), | |
777 | }; | |
778 | ||
779 | static int __init sh_rtc_init(void) | |
780 | { | |
781 | return platform_driver_register(&sh_rtc_platform_driver); | |
782 | } | |
783 | ||
784 | static void __exit sh_rtc_exit(void) | |
785 | { | |
786 | platform_driver_unregister(&sh_rtc_platform_driver); | |
787 | } | |
788 | ||
789 | module_init(sh_rtc_init); | |
790 | module_exit(sh_rtc_exit); | |
791 | ||
792 | MODULE_DESCRIPTION("SuperH on-chip RTC driver"); | |
1b73e6ae | 793 | MODULE_VERSION(DRV_VERSION); |
b420b1a7 AC |
794 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, " |
795 | "Jamie Lenehan <lenehan@twibble.org>, " | |
796 | "Angelo Castello <angelo.castello@st.com>"); | |
317a6104 | 797 | MODULE_LICENSE("GPL"); |
ad28a07b | 798 | MODULE_ALIAS("platform:" DRV_NAME); |