Commit | Line | Data |
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317a6104 PM |
1 | /* |
2 | * SuperH On-Chip RTC Support | |
3 | * | |
063adc75 | 4 | * Copyright (C) 2006 - 2009 Paul Mundt |
1b73e6ae | 5 | * Copyright (C) 2006 Jamie Lenehan |
b420b1a7 | 6 | * Copyright (C) 2008 Angelo Castello |
317a6104 PM |
7 | * |
8 | * Based on the old arch/sh/kernel/cpu/rtc.c by: | |
9 | * | |
10 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> | |
11 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka | |
12 | * | |
13 | * This file is subject to the terms and conditions of the GNU General Public | |
14 | * License. See the file "COPYING" in the main directory of this archive | |
15 | * for more details. | |
16 | */ | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/bcd.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/seq_file.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spinlock.h> | |
31ccb081 | 26 | #include <linux/io.h> |
5d2a5037 | 27 | #include <linux/log2.h> |
063adc75 | 28 | #include <linux/clk.h> |
ad89f87a | 29 | #include <asm/rtc.h> |
317a6104 | 30 | |
1b73e6ae | 31 | #define DRV_NAME "sh-rtc" |
063adc75 | 32 | #define DRV_VERSION "0.2.2" |
317a6104 PM |
33 | |
34 | #define RTC_REG(r) ((r) * rtc_reg_size) | |
35 | ||
31ccb081 | 36 | #define R64CNT RTC_REG(0) |
1b73e6ae JL |
37 | |
38 | #define RSECCNT RTC_REG(1) /* RTC sec */ | |
39 | #define RMINCNT RTC_REG(2) /* RTC min */ | |
40 | #define RHRCNT RTC_REG(3) /* RTC hour */ | |
41 | #define RWKCNT RTC_REG(4) /* RTC week */ | |
42 | #define RDAYCNT RTC_REG(5) /* RTC day */ | |
43 | #define RMONCNT RTC_REG(6) /* RTC month */ | |
44 | #define RYRCNT RTC_REG(7) /* RTC year */ | |
45 | #define RSECAR RTC_REG(8) /* ALARM sec */ | |
46 | #define RMINAR RTC_REG(9) /* ALARM min */ | |
47 | #define RHRAR RTC_REG(10) /* ALARM hour */ | |
48 | #define RWKAR RTC_REG(11) /* ALARM week */ | |
49 | #define RDAYAR RTC_REG(12) /* ALARM day */ | |
50 | #define RMONAR RTC_REG(13) /* ALARM month */ | |
51 | #define RCR1 RTC_REG(14) /* Control */ | |
52 | #define RCR2 RTC_REG(15) /* Control */ | |
53 | ||
ff1b7506 PM |
54 | /* |
55 | * Note on RYRAR and RCR3: Up until this point most of the register | |
56 | * definitions are consistent across all of the available parts. However, | |
57 | * the placement of the optional RYRAR and RCR3 (the RYRAR control | |
58 | * register used to control RYRCNT/RYRAR compare) varies considerably | |
59 | * across various parts, occasionally being mapped in to a completely | |
60 | * unrelated address space. For proper RYRAR support a separate resource | |
61 | * would have to be handed off, but as this is purely optional in | |
62 | * practice, we simply opt not to support it, thereby keeping the code | |
63 | * quite a bit more simplified. | |
64 | */ | |
65 | ||
1b73e6ae JL |
66 | /* ALARM Bits - or with BCD encoded value */ |
67 | #define AR_ENB 0x80 /* Enable for alarm cmp */ | |
317a6104 | 68 | |
b420b1a7 AC |
69 | /* Period Bits */ |
70 | #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ | |
71 | #define PF_COUNT 0x200 /* Half periodic counter */ | |
72 | #define PF_OXS 0x400 /* Periodic One x Second */ | |
73 | #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ | |
74 | #define PF_MASK 0xf00 | |
75 | ||
317a6104 PM |
76 | /* RCR1 Bits */ |
77 | #define RCR1_CF 0x80 /* Carry Flag */ | |
78 | #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ | |
79 | #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ | |
80 | #define RCR1_AF 0x01 /* Alarm Flag */ | |
81 | ||
82 | /* RCR2 Bits */ | |
83 | #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ | |
84 | #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ | |
85 | #define RCR2_RTCEN 0x08 /* ENable RTC */ | |
86 | #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ | |
87 | #define RCR2_RESET 0x02 /* Reset bit */ | |
88 | #define RCR2_START 0x01 /* Start bit */ | |
89 | ||
90 | struct sh_rtc { | |
063adc75 PM |
91 | void __iomem *regbase; |
92 | unsigned long regsize; | |
93 | struct resource *res; | |
94 | int alarm_irq; | |
95 | int periodic_irq; | |
96 | int carry_irq; | |
97 | struct clk *clk; | |
98 | struct rtc_device *rtc_dev; | |
99 | spinlock_t lock; | |
100 | unsigned long capabilities; /* See asm/rtc.h for cap bits */ | |
101 | unsigned short periodic_freq; | |
317a6104 PM |
102 | }; |
103 | ||
5e084a15 | 104 | static int __sh_rtc_interrupt(struct sh_rtc *rtc) |
317a6104 | 105 | { |
5e084a15 | 106 | unsigned int tmp, pending; |
317a6104 PM |
107 | |
108 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 109 | pending = tmp & RCR1_CF; |
1b73e6ae | 110 | tmp &= ~RCR1_CF; |
317a6104 PM |
111 | writeb(tmp, rtc->regbase + RCR1); |
112 | ||
b420b1a7 | 113 | /* Users have requested One x Second IRQ */ |
5e084a15 | 114 | if (pending && rtc->periodic_freq & PF_OXS) |
b420b1a7 | 115 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); |
317a6104 | 116 | |
5e084a15 | 117 | return pending; |
317a6104 PM |
118 | } |
119 | ||
5e084a15 | 120 | static int __sh_rtc_alarm(struct sh_rtc *rtc) |
1b73e6ae | 121 | { |
5e084a15 | 122 | unsigned int tmp, pending; |
1b73e6ae JL |
123 | |
124 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 125 | pending = tmp & RCR1_AF; |
b420b1a7 | 126 | tmp &= ~(RCR1_AF | RCR1_AIE); |
5e084a15 | 127 | writeb(tmp, rtc->regbase + RCR1); |
1b73e6ae | 128 | |
5e084a15 MD |
129 | if (pending) |
130 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); | |
b420b1a7 | 131 | |
5e084a15 | 132 | return pending; |
1b73e6ae JL |
133 | } |
134 | ||
5e084a15 | 135 | static int __sh_rtc_periodic(struct sh_rtc *rtc) |
317a6104 | 136 | { |
b420b1a7 | 137 | struct rtc_device *rtc_dev = rtc->rtc_dev; |
5e084a15 MD |
138 | struct rtc_task *irq_task; |
139 | unsigned int tmp, pending; | |
317a6104 | 140 | |
b420b1a7 | 141 | tmp = readb(rtc->regbase + RCR2); |
5e084a15 | 142 | pending = tmp & RCR2_PEF; |
b420b1a7 AC |
143 | tmp &= ~RCR2_PEF; |
144 | writeb(tmp, rtc->regbase + RCR2); | |
145 | ||
5e084a15 MD |
146 | if (!pending) |
147 | return 0; | |
148 | ||
b420b1a7 AC |
149 | /* Half period enabled than one skipped and the next notified */ |
150 | if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) | |
151 | rtc->periodic_freq &= ~PF_COUNT; | |
152 | else { | |
153 | if (rtc->periodic_freq & PF_HP) | |
154 | rtc->periodic_freq |= PF_COUNT; | |
155 | if (rtc->periodic_freq & PF_KOU) { | |
156 | spin_lock(&rtc_dev->irq_task_lock); | |
5e084a15 MD |
157 | irq_task = rtc_dev->irq_task; |
158 | if (irq_task) | |
159 | irq_task->func(irq_task->private_data); | |
b420b1a7 AC |
160 | spin_unlock(&rtc_dev->irq_task_lock); |
161 | } else | |
162 | rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); | |
163 | } | |
317a6104 | 164 | |
5e084a15 MD |
165 | return pending; |
166 | } | |
167 | ||
168 | static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) | |
169 | { | |
170 | struct sh_rtc *rtc = dev_id; | |
171 | int ret; | |
172 | ||
173 | spin_lock(&rtc->lock); | |
174 | ret = __sh_rtc_interrupt(rtc); | |
175 | spin_unlock(&rtc->lock); | |
176 | ||
177 | return IRQ_RETVAL(ret); | |
178 | } | |
179 | ||
180 | static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) | |
181 | { | |
182 | struct sh_rtc *rtc = dev_id; | |
183 | int ret; | |
184 | ||
185 | spin_lock(&rtc->lock); | |
186 | ret = __sh_rtc_alarm(rtc); | |
187 | spin_unlock(&rtc->lock); | |
188 | ||
189 | return IRQ_RETVAL(ret); | |
190 | } | |
191 | ||
192 | static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) | |
193 | { | |
194 | struct sh_rtc *rtc = dev_id; | |
195 | int ret; | |
196 | ||
197 | spin_lock(&rtc->lock); | |
198 | ret = __sh_rtc_periodic(rtc); | |
317a6104 PM |
199 | spin_unlock(&rtc->lock); |
200 | ||
5e084a15 MD |
201 | return IRQ_RETVAL(ret); |
202 | } | |
203 | ||
204 | static irqreturn_t sh_rtc_shared(int irq, void *dev_id) | |
205 | { | |
206 | struct sh_rtc *rtc = dev_id; | |
207 | int ret; | |
208 | ||
209 | spin_lock(&rtc->lock); | |
210 | ret = __sh_rtc_interrupt(rtc); | |
211 | ret |= __sh_rtc_alarm(rtc); | |
212 | ret |= __sh_rtc_periodic(rtc); | |
213 | spin_unlock(&rtc->lock); | |
214 | ||
215 | return IRQ_RETVAL(ret); | |
317a6104 PM |
216 | } |
217 | ||
218 | static inline void sh_rtc_setpie(struct device *dev, unsigned int enable) | |
219 | { | |
220 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
221 | unsigned int tmp; | |
222 | ||
223 | spin_lock_irq(&rtc->lock); | |
224 | ||
225 | tmp = readb(rtc->regbase + RCR2); | |
226 | ||
227 | if (enable) { | |
b420b1a7 AC |
228 | tmp &= ~RCR2_PEF; /* Clear PES bit */ |
229 | tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ | |
317a6104 PM |
230 | } else |
231 | tmp &= ~(RCR2_PESMASK | RCR2_PEF); | |
232 | ||
233 | writeb(tmp, rtc->regbase + RCR2); | |
234 | ||
235 | spin_unlock_irq(&rtc->lock); | |
236 | } | |
237 | ||
b420b1a7 | 238 | static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq) |
317a6104 PM |
239 | { |
240 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
b420b1a7 | 241 | int tmp, ret = 0; |
317a6104 PM |
242 | |
243 | spin_lock_irq(&rtc->lock); | |
b420b1a7 | 244 | tmp = rtc->periodic_freq & PF_MASK; |
317a6104 | 245 | |
b420b1a7 AC |
246 | switch (freq) { |
247 | case 0: | |
248 | rtc->periodic_freq = 0x00; | |
249 | break; | |
250 | case 1: | |
251 | rtc->periodic_freq = 0x60; | |
252 | break; | |
253 | case 2: | |
254 | rtc->periodic_freq = 0x50; | |
255 | break; | |
256 | case 4: | |
257 | rtc->periodic_freq = 0x40; | |
258 | break; | |
259 | case 8: | |
260 | rtc->periodic_freq = 0x30 | PF_HP; | |
261 | break; | |
262 | case 16: | |
263 | rtc->periodic_freq = 0x30; | |
264 | break; | |
265 | case 32: | |
266 | rtc->periodic_freq = 0x20 | PF_HP; | |
267 | break; | |
268 | case 64: | |
269 | rtc->periodic_freq = 0x20; | |
270 | break; | |
271 | case 128: | |
272 | rtc->periodic_freq = 0x10 | PF_HP; | |
273 | break; | |
274 | case 256: | |
275 | rtc->periodic_freq = 0x10; | |
276 | break; | |
277 | default: | |
278 | ret = -ENOTSUPP; | |
279 | } | |
317a6104 | 280 | |
b420b1a7 AC |
281 | if (ret == 0) { |
282 | rtc->periodic_freq |= tmp; | |
283 | rtc->rtc_dev->irq_freq = freq; | |
284 | } | |
317a6104 PM |
285 | |
286 | spin_unlock_irq(&rtc->lock); | |
b420b1a7 | 287 | return ret; |
317a6104 PM |
288 | } |
289 | ||
b420b1a7 | 290 | static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) |
317a6104 PM |
291 | { |
292 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
293 | unsigned int tmp; | |
317a6104 | 294 | |
b420b1a7 | 295 | spin_lock_irq(&rtc->lock); |
317a6104 | 296 | |
b420b1a7 | 297 | tmp = readb(rtc->regbase + RCR1); |
317a6104 | 298 | |
063adc75 | 299 | if (enable) |
b420b1a7 | 300 | tmp |= RCR1_AIE; |
063adc75 PM |
301 | else |
302 | tmp &= ~RCR1_AIE; | |
317a6104 | 303 | |
b420b1a7 | 304 | writeb(tmp, rtc->regbase + RCR1); |
317a6104 | 305 | |
b420b1a7 | 306 | spin_unlock_irq(&rtc->lock); |
317a6104 PM |
307 | } |
308 | ||
317a6104 PM |
309 | static int sh_rtc_proc(struct device *dev, struct seq_file *seq) |
310 | { | |
311 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
312 | unsigned int tmp; | |
313 | ||
314 | tmp = readb(rtc->regbase + RCR1); | |
b420b1a7 | 315 | seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); |
317a6104 PM |
316 | |
317 | tmp = readb(rtc->regbase + RCR2); | |
318 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
b420b1a7 | 319 | (tmp & RCR2_PESMASK) ? "yes" : "no"); |
317a6104 PM |
320 | |
321 | return 0; | |
322 | } | |
323 | ||
9cd88b90 MD |
324 | static inline void sh_rtc_setcie(struct device *dev, unsigned int enable) |
325 | { | |
326 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
327 | unsigned int tmp; | |
328 | ||
329 | spin_lock_irq(&rtc->lock); | |
330 | ||
331 | tmp = readb(rtc->regbase + RCR1); | |
332 | ||
333 | if (!enable) | |
334 | tmp &= ~RCR1_CIE; | |
335 | else | |
336 | tmp |= RCR1_CIE; | |
337 | ||
338 | writeb(tmp, rtc->regbase + RCR1); | |
339 | ||
340 | spin_unlock_irq(&rtc->lock); | |
341 | } | |
342 | ||
317a6104 PM |
343 | static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) |
344 | { | |
b420b1a7 AC |
345 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
346 | unsigned int ret = 0; | |
317a6104 PM |
347 | |
348 | switch (cmd) { | |
349 | case RTC_PIE_OFF: | |
350 | case RTC_PIE_ON: | |
351 | sh_rtc_setpie(dev, cmd == RTC_PIE_ON); | |
317a6104 PM |
352 | break; |
353 | case RTC_AIE_OFF: | |
354 | case RTC_AIE_ON: | |
355 | sh_rtc_setaie(dev, cmd == RTC_AIE_ON); | |
317a6104 | 356 | break; |
b420b1a7 AC |
357 | case RTC_UIE_OFF: |
358 | rtc->periodic_freq &= ~PF_OXS; | |
9cd88b90 | 359 | sh_rtc_setcie(dev, 0); |
b420b1a7 AC |
360 | break; |
361 | case RTC_UIE_ON: | |
362 | rtc->periodic_freq |= PF_OXS; | |
9cd88b90 | 363 | sh_rtc_setcie(dev, 1); |
b420b1a7 AC |
364 | break; |
365 | case RTC_IRQP_READ: | |
366 | ret = put_user(rtc->rtc_dev->irq_freq, | |
367 | (unsigned long __user *)arg); | |
368 | break; | |
369 | case RTC_IRQP_SET: | |
370 | ret = sh_rtc_setfreq(dev, arg); | |
371 | break; | |
372 | default: | |
373 | ret = -ENOIOCTLCMD; | |
317a6104 PM |
374 | } |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
379 | static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
380 | { | |
381 | struct platform_device *pdev = to_platform_device(dev); | |
382 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
383 | unsigned int sec128, sec2, yr, yr100, cf_bit; | |
384 | ||
385 | do { | |
386 | unsigned int tmp; | |
387 | ||
388 | spin_lock_irq(&rtc->lock); | |
389 | ||
390 | tmp = readb(rtc->regbase + RCR1); | |
391 | tmp &= ~RCR1_CF; /* Clear CF-bit */ | |
392 | tmp |= RCR1_CIE; | |
393 | writeb(tmp, rtc->regbase + RCR1); | |
394 | ||
395 | sec128 = readb(rtc->regbase + R64CNT); | |
396 | ||
fe20ba70 AB |
397 | tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); |
398 | tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); | |
399 | tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); | |
400 | tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); | |
401 | tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); | |
402 | tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; | |
317a6104 | 403 | |
ad89f87a PM |
404 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
405 | yr = readw(rtc->regbase + RYRCNT); | |
fe20ba70 | 406 | yr100 = bcd2bin(yr >> 8); |
ad89f87a PM |
407 | yr &= 0xff; |
408 | } else { | |
409 | yr = readb(rtc->regbase + RYRCNT); | |
fe20ba70 | 410 | yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); |
ad89f87a | 411 | } |
317a6104 | 412 | |
fe20ba70 | 413 | tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; |
317a6104 PM |
414 | |
415 | sec2 = readb(rtc->regbase + R64CNT); | |
416 | cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; | |
417 | ||
418 | spin_unlock_irq(&rtc->lock); | |
419 | } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); | |
420 | ||
421 | #if RTC_BIT_INVERTED != 0 | |
422 | if ((sec128 & RTC_BIT_INVERTED)) | |
423 | tm->tm_sec--; | |
424 | #endif | |
425 | ||
9cd88b90 MD |
426 | /* only keep the carry interrupt enabled if UIE is on */ |
427 | if (!(rtc->periodic_freq & PF_OXS)) | |
428 | sh_rtc_setcie(dev, 0); | |
429 | ||
435c55d1 | 430 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
317a6104 | 431 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 432 | __func__, |
317a6104 | 433 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
a1614796 | 434 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); |
317a6104 | 435 | |
edf22477 | 436 | return rtc_valid_tm(tm); |
317a6104 PM |
437 | } |
438 | ||
439 | static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
440 | { | |
441 | struct platform_device *pdev = to_platform_device(dev); | |
442 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
443 | unsigned int tmp; | |
444 | int year; | |
445 | ||
446 | spin_lock_irq(&rtc->lock); | |
447 | ||
448 | /* Reset pre-scaler & stop RTC */ | |
449 | tmp = readb(rtc->regbase + RCR2); | |
450 | tmp |= RCR2_RESET; | |
699bc661 | 451 | tmp &= ~RCR2_START; |
317a6104 PM |
452 | writeb(tmp, rtc->regbase + RCR2); |
453 | ||
fe20ba70 AB |
454 | writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); |
455 | writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); | |
456 | writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); | |
457 | writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); | |
458 | writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); | |
459 | writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); | |
317a6104 | 460 | |
ad89f87a | 461 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
fe20ba70 AB |
462 | year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | |
463 | bin2bcd(tm->tm_year % 100); | |
ad89f87a PM |
464 | writew(year, rtc->regbase + RYRCNT); |
465 | } else { | |
466 | year = tm->tm_year % 100; | |
fe20ba70 | 467 | writeb(bin2bcd(year), rtc->regbase + RYRCNT); |
ad89f87a | 468 | } |
317a6104 PM |
469 | |
470 | /* Start RTC */ | |
471 | tmp = readb(rtc->regbase + RCR2); | |
472 | tmp &= ~RCR2_RESET; | |
473 | tmp |= RCR2_RTCEN | RCR2_START; | |
474 | writeb(tmp, rtc->regbase + RCR2); | |
475 | ||
476 | spin_unlock_irq(&rtc->lock); | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
1b73e6ae JL |
481 | static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) |
482 | { | |
483 | unsigned int byte; | |
484 | int value = 0xff; /* return 0xff for ignored values */ | |
485 | ||
486 | byte = readb(rtc->regbase + reg_off); | |
487 | if (byte & AR_ENB) { | |
488 | byte &= ~AR_ENB; /* strip the enable bit */ | |
fe20ba70 | 489 | value = bcd2bin(byte); |
1b73e6ae JL |
490 | } |
491 | ||
492 | return value; | |
493 | } | |
494 | ||
495 | static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
496 | { | |
497 | struct platform_device *pdev = to_platform_device(dev); | |
498 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
b420b1a7 | 499 | struct rtc_time *tm = &wkalrm->time; |
1b73e6ae JL |
500 | |
501 | spin_lock_irq(&rtc->lock); | |
502 | ||
503 | tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); | |
504 | tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); | |
505 | tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); | |
506 | tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); | |
507 | tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); | |
508 | tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); | |
509 | if (tm->tm_mon > 0) | |
510 | tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ | |
511 | tm->tm_year = 0xffff; | |
512 | ||
0d103e90 DB |
513 | wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; |
514 | ||
1b73e6ae JL |
515 | spin_unlock_irq(&rtc->lock); |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, | |
521 | int value, int reg_off) | |
522 | { | |
523 | /* < 0 for a value that is ignored */ | |
524 | if (value < 0) | |
525 | writeb(0, rtc->regbase + reg_off); | |
526 | else | |
fe20ba70 | 527 | writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); |
1b73e6ae JL |
528 | } |
529 | ||
b420b1a7 | 530 | static int sh_rtc_check_alarm(struct rtc_time *tm) |
1b73e6ae JL |
531 | { |
532 | /* | |
533 | * The original rtc says anything > 0xc0 is "don't care" or "match | |
534 | * all" - most users use 0xff but rtc-dev uses -1 for the same thing. | |
535 | * The original rtc doesn't support years - some things use -1 and | |
536 | * some 0xffff. We use -1 to make out tests easier. | |
537 | */ | |
538 | if (tm->tm_year == 0xffff) | |
539 | tm->tm_year = -1; | |
540 | if (tm->tm_mon >= 0xff) | |
541 | tm->tm_mon = -1; | |
542 | if (tm->tm_mday >= 0xff) | |
543 | tm->tm_mday = -1; | |
544 | if (tm->tm_wday >= 0xff) | |
545 | tm->tm_wday = -1; | |
546 | if (tm->tm_hour >= 0xff) | |
547 | tm->tm_hour = -1; | |
548 | if (tm->tm_min >= 0xff) | |
549 | tm->tm_min = -1; | |
550 | if (tm->tm_sec >= 0xff) | |
551 | tm->tm_sec = -1; | |
552 | ||
553 | if (tm->tm_year > 9999 || | |
554 | tm->tm_mon >= 12 || | |
555 | tm->tm_mday == 0 || tm->tm_mday >= 32 || | |
556 | tm->tm_wday >= 7 || | |
557 | tm->tm_hour >= 24 || | |
558 | tm->tm_min >= 60 || | |
559 | tm->tm_sec >= 60) | |
560 | return -EINVAL; | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
566 | { | |
567 | struct platform_device *pdev = to_platform_device(dev); | |
568 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
569 | unsigned int rcr1; | |
570 | struct rtc_time *tm = &wkalrm->time; | |
571 | int mon, err; | |
572 | ||
573 | err = sh_rtc_check_alarm(tm); | |
574 | if (unlikely(err < 0)) | |
575 | return err; | |
576 | ||
577 | spin_lock_irq(&rtc->lock); | |
578 | ||
15c945c3 | 579 | /* disable alarm interrupt and clear the alarm flag */ |
1b73e6ae | 580 | rcr1 = readb(rtc->regbase + RCR1); |
b420b1a7 | 581 | rcr1 &= ~(RCR1_AF | RCR1_AIE); |
15c945c3 | 582 | writeb(rcr1, rtc->regbase + RCR1); |
1b73e6ae | 583 | |
1b73e6ae JL |
584 | /* set alarm time */ |
585 | sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); | |
586 | sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); | |
587 | sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); | |
588 | sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); | |
589 | sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); | |
590 | mon = tm->tm_mon; | |
591 | if (mon >= 0) | |
592 | mon += 1; | |
593 | sh_rtc_write_alarm_value(rtc, mon, RMONAR); | |
594 | ||
15c945c3 JL |
595 | if (wkalrm->enabled) { |
596 | rcr1 |= RCR1_AIE; | |
597 | writeb(rcr1, rtc->regbase + RCR1); | |
598 | } | |
1b73e6ae JL |
599 | |
600 | spin_unlock_irq(&rtc->lock); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
b420b1a7 AC |
605 | static int sh_rtc_irq_set_state(struct device *dev, int enabled) |
606 | { | |
607 | struct platform_device *pdev = to_platform_device(dev); | |
608 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
609 | ||
610 | if (enabled) { | |
611 | rtc->periodic_freq |= PF_KOU; | |
612 | return sh_rtc_ioctl(dev, RTC_PIE_ON, 0); | |
613 | } else { | |
614 | rtc->periodic_freq &= ~PF_KOU; | |
615 | return sh_rtc_ioctl(dev, RTC_PIE_OFF, 0); | |
616 | } | |
617 | } | |
618 | ||
619 | static int sh_rtc_irq_set_freq(struct device *dev, int freq) | |
620 | { | |
5d2a5037 JC |
621 | if (!is_power_of_2(freq)) |
622 | return -EINVAL; | |
063adc75 | 623 | |
b420b1a7 AC |
624 | return sh_rtc_ioctl(dev, RTC_IRQP_SET, freq); |
625 | } | |
626 | ||
317a6104 | 627 | static struct rtc_class_ops sh_rtc_ops = { |
317a6104 PM |
628 | .ioctl = sh_rtc_ioctl, |
629 | .read_time = sh_rtc_read_time, | |
630 | .set_time = sh_rtc_set_time, | |
1b73e6ae JL |
631 | .read_alarm = sh_rtc_read_alarm, |
632 | .set_alarm = sh_rtc_set_alarm, | |
b420b1a7 AC |
633 | .irq_set_state = sh_rtc_irq_set_state, |
634 | .irq_set_freq = sh_rtc_irq_set_freq, | |
317a6104 PM |
635 | .proc = sh_rtc_proc, |
636 | }; | |
637 | ||
638 | static int __devinit sh_rtc_probe(struct platform_device *pdev) | |
639 | { | |
640 | struct sh_rtc *rtc; | |
641 | struct resource *res; | |
edf22477 | 642 | struct rtc_time r; |
063adc75 PM |
643 | char clk_name[6]; |
644 | int clk_id, ret; | |
317a6104 PM |
645 | |
646 | rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL); | |
647 | if (unlikely(!rtc)) | |
648 | return -ENOMEM; | |
649 | ||
650 | spin_lock_init(&rtc->lock); | |
651 | ||
b420b1a7 | 652 | /* get periodic/carry/alarm irqs */ |
2641dc92 | 653 | ret = platform_get_irq(pdev, 0); |
2fac6674 | 654 | if (unlikely(ret <= 0)) { |
2641dc92 | 655 | ret = -ENOENT; |
5e084a15 | 656 | dev_err(&pdev->dev, "No IRQ resource\n"); |
317a6104 PM |
657 | goto err_badres; |
658 | } | |
063adc75 | 659 | |
2641dc92 | 660 | rtc->periodic_irq = ret; |
5e084a15 MD |
661 | rtc->carry_irq = platform_get_irq(pdev, 1); |
662 | rtc->alarm_irq = platform_get_irq(pdev, 2); | |
317a6104 PM |
663 | |
664 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
665 | if (unlikely(res == NULL)) { | |
2641dc92 | 666 | ret = -ENOENT; |
317a6104 PM |
667 | dev_err(&pdev->dev, "No IO resource\n"); |
668 | goto err_badres; | |
669 | } | |
670 | ||
063adc75 | 671 | rtc->regsize = resource_size(res); |
317a6104 PM |
672 | |
673 | rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name); | |
674 | if (unlikely(!rtc->res)) { | |
675 | ret = -EBUSY; | |
676 | goto err_badres; | |
677 | } | |
678 | ||
0305794c | 679 | rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize); |
317a6104 PM |
680 | if (unlikely(!rtc->regbase)) { |
681 | ret = -EINVAL; | |
682 | goto err_badmap; | |
683 | } | |
684 | ||
063adc75 PM |
685 | clk_id = pdev->id; |
686 | /* With a single device, the clock id is still "rtc0" */ | |
687 | if (clk_id < 0) | |
688 | clk_id = 0; | |
689 | ||
690 | snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); | |
691 | ||
692 | rtc->clk = clk_get(&pdev->dev, clk_name); | |
693 | if (IS_ERR(rtc->clk)) { | |
694 | /* | |
695 | * No error handling for rtc->clk intentionally, not all | |
696 | * platforms will have a unique clock for the RTC, and | |
697 | * the clk API can handle the struct clk pointer being | |
698 | * NULL. | |
699 | */ | |
700 | rtc->clk = NULL; | |
701 | } | |
702 | ||
703 | clk_enable(rtc->clk); | |
704 | ||
317a6104 PM |
705 | rtc->rtc_dev = rtc_device_register("sh", &pdev->dev, |
706 | &sh_rtc_ops, THIS_MODULE); | |
29dd0dae | 707 | if (IS_ERR(rtc->rtc_dev)) { |
317a6104 | 708 | ret = PTR_ERR(rtc->rtc_dev); |
0305794c | 709 | goto err_unmap; |
317a6104 PM |
710 | } |
711 | ||
ad89f87a PM |
712 | rtc->capabilities = RTC_DEF_CAPABILITIES; |
713 | if (pdev->dev.platform_data) { | |
714 | struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; | |
715 | ||
716 | /* | |
717 | * Some CPUs have special capabilities in addition to the | |
718 | * default set. Add those in here. | |
719 | */ | |
720 | rtc->capabilities |= pinfo->capabilities; | |
721 | } | |
722 | ||
b420b1a7 | 723 | rtc->rtc_dev->max_user_freq = 256; |
b420b1a7 | 724 | |
317a6104 PM |
725 | platform_set_drvdata(pdev, rtc); |
726 | ||
5e084a15 MD |
727 | if (rtc->carry_irq <= 0) { |
728 | /* register shared periodic/carry/alarm irq */ | |
729 | ret = request_irq(rtc->periodic_irq, sh_rtc_shared, | |
730 | IRQF_DISABLED, "sh-rtc", rtc); | |
731 | if (unlikely(ret)) { | |
732 | dev_err(&pdev->dev, | |
733 | "request IRQ failed with %d, IRQ %d\n", ret, | |
734 | rtc->periodic_irq); | |
735 | goto err_unmap; | |
736 | } | |
737 | } else { | |
738 | /* register periodic/carry/alarm irqs */ | |
739 | ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, | |
740 | IRQF_DISABLED, "sh-rtc period", rtc); | |
741 | if (unlikely(ret)) { | |
742 | dev_err(&pdev->dev, | |
743 | "request period IRQ failed with %d, IRQ %d\n", | |
744 | ret, rtc->periodic_irq); | |
745 | goto err_unmap; | |
746 | } | |
b420b1a7 | 747 | |
5e084a15 MD |
748 | ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, |
749 | IRQF_DISABLED, "sh-rtc carry", rtc); | |
750 | if (unlikely(ret)) { | |
751 | dev_err(&pdev->dev, | |
752 | "request carry IRQ failed with %d, IRQ %d\n", | |
753 | ret, rtc->carry_irq); | |
754 | free_irq(rtc->periodic_irq, rtc); | |
755 | goto err_unmap; | |
756 | } | |
b420b1a7 | 757 | |
5e084a15 MD |
758 | ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, |
759 | IRQF_DISABLED, "sh-rtc alarm", rtc); | |
760 | if (unlikely(ret)) { | |
761 | dev_err(&pdev->dev, | |
762 | "request alarm IRQ failed with %d, IRQ %d\n", | |
763 | ret, rtc->alarm_irq); | |
764 | free_irq(rtc->carry_irq, rtc); | |
765 | free_irq(rtc->periodic_irq, rtc); | |
766 | goto err_unmap; | |
767 | } | |
b420b1a7 AC |
768 | } |
769 | ||
9cd88b90 MD |
770 | /* everything disabled by default */ |
771 | rtc->periodic_freq = 0; | |
772 | rtc->rtc_dev->irq_freq = 0; | |
773 | sh_rtc_setpie(&pdev->dev, 0); | |
774 | sh_rtc_setaie(&pdev->dev, 0); | |
775 | sh_rtc_setcie(&pdev->dev, 0); | |
edf22477 MD |
776 | |
777 | /* reset rtc to epoch 0 if time is invalid */ | |
778 | if (rtc_read_time(rtc->rtc_dev, &r) < 0) { | |
779 | rtc_time_to_tm(0, &r); | |
780 | rtc_set_time(rtc->rtc_dev, &r); | |
781 | } | |
782 | ||
7a8fe8e3 | 783 | device_init_wakeup(&pdev->dev, 1); |
317a6104 PM |
784 | return 0; |
785 | ||
0305794c | 786 | err_unmap: |
063adc75 PM |
787 | clk_disable(rtc->clk); |
788 | clk_put(rtc->clk); | |
0305794c | 789 | iounmap(rtc->regbase); |
317a6104 PM |
790 | err_badmap: |
791 | release_resource(rtc->res); | |
792 | err_badres: | |
793 | kfree(rtc); | |
794 | ||
795 | return ret; | |
796 | } | |
797 | ||
798 | static int __devexit sh_rtc_remove(struct platform_device *pdev) | |
799 | { | |
800 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
801 | ||
802 | if (likely(rtc->rtc_dev)) | |
803 | rtc_device_unregister(rtc->rtc_dev); | |
804 | ||
805 | sh_rtc_setpie(&pdev->dev, 0); | |
806 | sh_rtc_setaie(&pdev->dev, 0); | |
9cd88b90 | 807 | sh_rtc_setcie(&pdev->dev, 0); |
317a6104 | 808 | |
b420b1a7 | 809 | free_irq(rtc->periodic_irq, rtc); |
063adc75 | 810 | |
5e084a15 MD |
811 | if (rtc->carry_irq > 0) { |
812 | free_irq(rtc->carry_irq, rtc); | |
813 | free_irq(rtc->alarm_irq, rtc); | |
814 | } | |
b420b1a7 | 815 | |
317a6104 PM |
816 | release_resource(rtc->res); |
817 | ||
0305794c PM |
818 | iounmap(rtc->regbase); |
819 | ||
063adc75 PM |
820 | clk_disable(rtc->clk); |
821 | clk_put(rtc->clk); | |
822 | ||
317a6104 PM |
823 | platform_set_drvdata(pdev, NULL); |
824 | ||
825 | kfree(rtc); | |
826 | ||
827 | return 0; | |
828 | } | |
faa9fa8e MD |
829 | |
830 | static void sh_rtc_set_irq_wake(struct device *dev, int enabled) | |
831 | { | |
832 | struct platform_device *pdev = to_platform_device(dev); | |
833 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
834 | ||
835 | set_irq_wake(rtc->periodic_irq, enabled); | |
063adc75 | 836 | |
faa9fa8e MD |
837 | if (rtc->carry_irq > 0) { |
838 | set_irq_wake(rtc->carry_irq, enabled); | |
839 | set_irq_wake(rtc->alarm_irq, enabled); | |
840 | } | |
faa9fa8e MD |
841 | } |
842 | ||
843 | static int sh_rtc_suspend(struct device *dev) | |
844 | { | |
845 | if (device_may_wakeup(dev)) | |
846 | sh_rtc_set_irq_wake(dev, 1); | |
847 | ||
848 | return 0; | |
849 | } | |
850 | ||
851 | static int sh_rtc_resume(struct device *dev) | |
852 | { | |
853 | if (device_may_wakeup(dev)) | |
854 | sh_rtc_set_irq_wake(dev, 0); | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | static struct dev_pm_ops sh_rtc_dev_pm_ops = { | |
860 | .suspend = sh_rtc_suspend, | |
861 | .resume = sh_rtc_resume, | |
862 | }; | |
863 | ||
317a6104 PM |
864 | static struct platform_driver sh_rtc_platform_driver = { |
865 | .driver = { | |
1b73e6ae | 866 | .name = DRV_NAME, |
317a6104 | 867 | .owner = THIS_MODULE, |
faa9fa8e | 868 | .pm = &sh_rtc_dev_pm_ops, |
317a6104 PM |
869 | }, |
870 | .probe = sh_rtc_probe, | |
871 | .remove = __devexit_p(sh_rtc_remove), | |
872 | }; | |
873 | ||
874 | static int __init sh_rtc_init(void) | |
875 | { | |
876 | return platform_driver_register(&sh_rtc_platform_driver); | |
877 | } | |
878 | ||
879 | static void __exit sh_rtc_exit(void) | |
880 | { | |
881 | platform_driver_unregister(&sh_rtc_platform_driver); | |
882 | } | |
883 | ||
884 | module_init(sh_rtc_init); | |
885 | module_exit(sh_rtc_exit); | |
886 | ||
887 | MODULE_DESCRIPTION("SuperH on-chip RTC driver"); | |
1b73e6ae | 888 | MODULE_VERSION(DRV_VERSION); |
b420b1a7 AC |
889 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, " |
890 | "Jamie Lenehan <lenehan@twibble.org>, " | |
891 | "Angelo Castello <angelo.castello@st.com>"); | |
317a6104 | 892 | MODULE_LICENSE("GPL"); |
ad28a07b | 893 | MODULE_ALIAS("platform:" DRV_NAME); |