Commit | Line | Data |
---|---|---|
4ff6f024 | 1 | // SPDX-License-Identifier: GPL-2.0 |
317a6104 PM |
2 | /* |
3 | * SuperH On-Chip RTC Support | |
4 | * | |
063adc75 | 5 | * Copyright (C) 2006 - 2009 Paul Mundt |
1b73e6ae | 6 | * Copyright (C) 2006 Jamie Lenehan |
b420b1a7 | 7 | * Copyright (C) 2008 Angelo Castello |
317a6104 PM |
8 | * |
9 | * Based on the old arch/sh/kernel/cpu/rtc.c by: | |
10 | * | |
11 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> | |
12 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka | |
317a6104 PM |
13 | */ |
14 | #include <linux/module.h> | |
ac316725 | 15 | #include <linux/mod_devicetable.h> |
317a6104 PM |
16 | #include <linux/kernel.h> |
17 | #include <linux/bcd.h> | |
18 | #include <linux/rtc.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/seq_file.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/spinlock.h> | |
31ccb081 | 24 | #include <linux/io.h> |
5d2a5037 | 25 | #include <linux/log2.h> |
063adc75 | 26 | #include <linux/clk.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
dab5aec6 | 28 | #ifdef CONFIG_SUPERH |
ad89f87a | 29 | #include <asm/rtc.h> |
dab5aec6 CB |
30 | #else |
31 | /* Default values for RZ/A RTC */ | |
32 | #define rtc_reg_size sizeof(u16) | |
33 | #define RTC_BIT_INVERTED 0 /* no chip bugs */ | |
34 | #define RTC_CAP_4_DIGIT_YEAR (1 << 0) | |
35 | #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR | |
36 | #endif | |
317a6104 | 37 | |
1b73e6ae | 38 | #define DRV_NAME "sh-rtc" |
317a6104 PM |
39 | |
40 | #define RTC_REG(r) ((r) * rtc_reg_size) | |
41 | ||
31ccb081 | 42 | #define R64CNT RTC_REG(0) |
1b73e6ae JL |
43 | |
44 | #define RSECCNT RTC_REG(1) /* RTC sec */ | |
45 | #define RMINCNT RTC_REG(2) /* RTC min */ | |
46 | #define RHRCNT RTC_REG(3) /* RTC hour */ | |
47 | #define RWKCNT RTC_REG(4) /* RTC week */ | |
48 | #define RDAYCNT RTC_REG(5) /* RTC day */ | |
49 | #define RMONCNT RTC_REG(6) /* RTC month */ | |
50 | #define RYRCNT RTC_REG(7) /* RTC year */ | |
51 | #define RSECAR RTC_REG(8) /* ALARM sec */ | |
52 | #define RMINAR RTC_REG(9) /* ALARM min */ | |
53 | #define RHRAR RTC_REG(10) /* ALARM hour */ | |
54 | #define RWKAR RTC_REG(11) /* ALARM week */ | |
55 | #define RDAYAR RTC_REG(12) /* ALARM day */ | |
56 | #define RMONAR RTC_REG(13) /* ALARM month */ | |
57 | #define RCR1 RTC_REG(14) /* Control */ | |
58 | #define RCR2 RTC_REG(15) /* Control */ | |
59 | ||
ff1b7506 PM |
60 | /* |
61 | * Note on RYRAR and RCR3: Up until this point most of the register | |
62 | * definitions are consistent across all of the available parts. However, | |
63 | * the placement of the optional RYRAR and RCR3 (the RYRAR control | |
64 | * register used to control RYRCNT/RYRAR compare) varies considerably | |
65 | * across various parts, occasionally being mapped in to a completely | |
66 | * unrelated address space. For proper RYRAR support a separate resource | |
67 | * would have to be handed off, but as this is purely optional in | |
68 | * practice, we simply opt not to support it, thereby keeping the code | |
69 | * quite a bit more simplified. | |
70 | */ | |
71 | ||
1b73e6ae JL |
72 | /* ALARM Bits - or with BCD encoded value */ |
73 | #define AR_ENB 0x80 /* Enable for alarm cmp */ | |
317a6104 | 74 | |
b420b1a7 AC |
75 | /* Period Bits */ |
76 | #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ | |
77 | #define PF_COUNT 0x200 /* Half periodic counter */ | |
78 | #define PF_OXS 0x400 /* Periodic One x Second */ | |
79 | #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ | |
80 | #define PF_MASK 0xf00 | |
81 | ||
317a6104 PM |
82 | /* RCR1 Bits */ |
83 | #define RCR1_CF 0x80 /* Carry Flag */ | |
84 | #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ | |
85 | #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ | |
86 | #define RCR1_AF 0x01 /* Alarm Flag */ | |
87 | ||
88 | /* RCR2 Bits */ | |
89 | #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ | |
90 | #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ | |
91 | #define RCR2_RTCEN 0x08 /* ENable RTC */ | |
92 | #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ | |
93 | #define RCR2_RESET 0x02 /* Reset bit */ | |
94 | #define RCR2_START 0x01 /* Start bit */ | |
95 | ||
96 | struct sh_rtc { | |
063adc75 PM |
97 | void __iomem *regbase; |
98 | unsigned long regsize; | |
99 | struct resource *res; | |
100 | int alarm_irq; | |
101 | int periodic_irq; | |
102 | int carry_irq; | |
103 | struct clk *clk; | |
104 | struct rtc_device *rtc_dev; | |
105 | spinlock_t lock; | |
106 | unsigned long capabilities; /* See asm/rtc.h for cap bits */ | |
107 | unsigned short periodic_freq; | |
317a6104 PM |
108 | }; |
109 | ||
5e084a15 | 110 | static int __sh_rtc_interrupt(struct sh_rtc *rtc) |
317a6104 | 111 | { |
5e084a15 | 112 | unsigned int tmp, pending; |
317a6104 PM |
113 | |
114 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 115 | pending = tmp & RCR1_CF; |
1b73e6ae | 116 | tmp &= ~RCR1_CF; |
317a6104 PM |
117 | writeb(tmp, rtc->regbase + RCR1); |
118 | ||
b420b1a7 | 119 | /* Users have requested One x Second IRQ */ |
5e084a15 | 120 | if (pending && rtc->periodic_freq & PF_OXS) |
b420b1a7 | 121 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); |
317a6104 | 122 | |
5e084a15 | 123 | return pending; |
317a6104 PM |
124 | } |
125 | ||
5e084a15 | 126 | static int __sh_rtc_alarm(struct sh_rtc *rtc) |
1b73e6ae | 127 | { |
5e084a15 | 128 | unsigned int tmp, pending; |
1b73e6ae JL |
129 | |
130 | tmp = readb(rtc->regbase + RCR1); | |
5e084a15 | 131 | pending = tmp & RCR1_AF; |
b420b1a7 | 132 | tmp &= ~(RCR1_AF | RCR1_AIE); |
5e084a15 | 133 | writeb(tmp, rtc->regbase + RCR1); |
1b73e6ae | 134 | |
5e084a15 MD |
135 | if (pending) |
136 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); | |
b420b1a7 | 137 | |
5e084a15 | 138 | return pending; |
1b73e6ae JL |
139 | } |
140 | ||
5e084a15 | 141 | static int __sh_rtc_periodic(struct sh_rtc *rtc) |
317a6104 | 142 | { |
5e084a15 | 143 | unsigned int tmp, pending; |
317a6104 | 144 | |
b420b1a7 | 145 | tmp = readb(rtc->regbase + RCR2); |
5e084a15 | 146 | pending = tmp & RCR2_PEF; |
b420b1a7 AC |
147 | tmp &= ~RCR2_PEF; |
148 | writeb(tmp, rtc->regbase + RCR2); | |
149 | ||
5e084a15 MD |
150 | if (!pending) |
151 | return 0; | |
152 | ||
b420b1a7 AC |
153 | /* Half period enabled than one skipped and the next notified */ |
154 | if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) | |
155 | rtc->periodic_freq &= ~PF_COUNT; | |
156 | else { | |
157 | if (rtc->periodic_freq & PF_HP) | |
158 | rtc->periodic_freq |= PF_COUNT; | |
ec623ff0 | 159 | rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); |
b420b1a7 | 160 | } |
317a6104 | 161 | |
5e084a15 MD |
162 | return pending; |
163 | } | |
164 | ||
165 | static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) | |
166 | { | |
167 | struct sh_rtc *rtc = dev_id; | |
168 | int ret; | |
169 | ||
170 | spin_lock(&rtc->lock); | |
171 | ret = __sh_rtc_interrupt(rtc); | |
172 | spin_unlock(&rtc->lock); | |
173 | ||
174 | return IRQ_RETVAL(ret); | |
175 | } | |
176 | ||
177 | static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) | |
178 | { | |
179 | struct sh_rtc *rtc = dev_id; | |
180 | int ret; | |
181 | ||
182 | spin_lock(&rtc->lock); | |
183 | ret = __sh_rtc_alarm(rtc); | |
184 | spin_unlock(&rtc->lock); | |
185 | ||
186 | return IRQ_RETVAL(ret); | |
187 | } | |
188 | ||
189 | static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) | |
190 | { | |
191 | struct sh_rtc *rtc = dev_id; | |
192 | int ret; | |
193 | ||
194 | spin_lock(&rtc->lock); | |
195 | ret = __sh_rtc_periodic(rtc); | |
317a6104 PM |
196 | spin_unlock(&rtc->lock); |
197 | ||
5e084a15 MD |
198 | return IRQ_RETVAL(ret); |
199 | } | |
200 | ||
201 | static irqreturn_t sh_rtc_shared(int irq, void *dev_id) | |
202 | { | |
203 | struct sh_rtc *rtc = dev_id; | |
204 | int ret; | |
205 | ||
206 | spin_lock(&rtc->lock); | |
207 | ret = __sh_rtc_interrupt(rtc); | |
208 | ret |= __sh_rtc_alarm(rtc); | |
209 | ret |= __sh_rtc_periodic(rtc); | |
210 | spin_unlock(&rtc->lock); | |
211 | ||
212 | return IRQ_RETVAL(ret); | |
317a6104 PM |
213 | } |
214 | ||
b420b1a7 | 215 | static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) |
317a6104 PM |
216 | { |
217 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
218 | unsigned int tmp; | |
317a6104 | 219 | |
b420b1a7 | 220 | spin_lock_irq(&rtc->lock); |
317a6104 | 221 | |
b420b1a7 | 222 | tmp = readb(rtc->regbase + RCR1); |
317a6104 | 223 | |
063adc75 | 224 | if (enable) |
b420b1a7 | 225 | tmp |= RCR1_AIE; |
063adc75 PM |
226 | else |
227 | tmp &= ~RCR1_AIE; | |
317a6104 | 228 | |
b420b1a7 | 229 | writeb(tmp, rtc->regbase + RCR1); |
317a6104 | 230 | |
b420b1a7 | 231 | spin_unlock_irq(&rtc->lock); |
317a6104 PM |
232 | } |
233 | ||
317a6104 PM |
234 | static int sh_rtc_proc(struct device *dev, struct seq_file *seq) |
235 | { | |
236 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
237 | unsigned int tmp; | |
238 | ||
239 | tmp = readb(rtc->regbase + RCR1); | |
b420b1a7 | 240 | seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); |
317a6104 PM |
241 | |
242 | tmp = readb(rtc->regbase + RCR2); | |
243 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
b420b1a7 | 244 | (tmp & RCR2_PESMASK) ? "yes" : "no"); |
317a6104 PM |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
9cd88b90 MD |
249 | static inline void sh_rtc_setcie(struct device *dev, unsigned int enable) |
250 | { | |
251 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
252 | unsigned int tmp; | |
253 | ||
254 | spin_lock_irq(&rtc->lock); | |
255 | ||
256 | tmp = readb(rtc->regbase + RCR1); | |
257 | ||
258 | if (!enable) | |
259 | tmp &= ~RCR1_CIE; | |
260 | else | |
261 | tmp |= RCR1_CIE; | |
262 | ||
263 | writeb(tmp, rtc->regbase + RCR1); | |
264 | ||
265 | spin_unlock_irq(&rtc->lock); | |
266 | } | |
267 | ||
16380c15 JS |
268 | static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
269 | { | |
270 | sh_rtc_setaie(dev, enabled); | |
271 | return 0; | |
272 | } | |
273 | ||
317a6104 PM |
274 | static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) |
275 | { | |
85368bb9 | 276 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
317a6104 PM |
277 | unsigned int sec128, sec2, yr, yr100, cf_bit; |
278 | ||
9852023d AB |
279 | if (!(readb(rtc->regbase + RCR2) & RCR2_RTCEN)) |
280 | return -EINVAL; | |
281 | ||
317a6104 PM |
282 | do { |
283 | unsigned int tmp; | |
284 | ||
285 | spin_lock_irq(&rtc->lock); | |
286 | ||
287 | tmp = readb(rtc->regbase + RCR1); | |
288 | tmp &= ~RCR1_CF; /* Clear CF-bit */ | |
289 | tmp |= RCR1_CIE; | |
290 | writeb(tmp, rtc->regbase + RCR1); | |
291 | ||
292 | sec128 = readb(rtc->regbase + R64CNT); | |
293 | ||
fe20ba70 AB |
294 | tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); |
295 | tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); | |
296 | tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); | |
297 | tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); | |
298 | tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); | |
299 | tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; | |
317a6104 | 300 | |
ad89f87a PM |
301 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
302 | yr = readw(rtc->regbase + RYRCNT); | |
fe20ba70 | 303 | yr100 = bcd2bin(yr >> 8); |
ad89f87a PM |
304 | yr &= 0xff; |
305 | } else { | |
306 | yr = readb(rtc->regbase + RYRCNT); | |
fe20ba70 | 307 | yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); |
ad89f87a | 308 | } |
317a6104 | 309 | |
fe20ba70 | 310 | tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; |
317a6104 PM |
311 | |
312 | sec2 = readb(rtc->regbase + R64CNT); | |
313 | cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; | |
314 | ||
315 | spin_unlock_irq(&rtc->lock); | |
316 | } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); | |
317 | ||
318 | #if RTC_BIT_INVERTED != 0 | |
319 | if ((sec128 & RTC_BIT_INVERTED)) | |
320 | tm->tm_sec--; | |
321 | #endif | |
322 | ||
9cd88b90 MD |
323 | /* only keep the carry interrupt enabled if UIE is on */ |
324 | if (!(rtc->periodic_freq & PF_OXS)) | |
325 | sh_rtc_setcie(dev, 0); | |
326 | ||
435c55d1 | 327 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
317a6104 | 328 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 329 | __func__, |
317a6104 | 330 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
a1614796 | 331 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); |
317a6104 | 332 | |
22652ba7 | 333 | return 0; |
317a6104 PM |
334 | } |
335 | ||
336 | static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
337 | { | |
85368bb9 | 338 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
317a6104 PM |
339 | unsigned int tmp; |
340 | int year; | |
341 | ||
342 | spin_lock_irq(&rtc->lock); | |
343 | ||
344 | /* Reset pre-scaler & stop RTC */ | |
345 | tmp = readb(rtc->regbase + RCR2); | |
346 | tmp |= RCR2_RESET; | |
699bc661 | 347 | tmp &= ~RCR2_START; |
317a6104 PM |
348 | writeb(tmp, rtc->regbase + RCR2); |
349 | ||
fe20ba70 AB |
350 | writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); |
351 | writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); | |
352 | writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); | |
353 | writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); | |
354 | writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); | |
355 | writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); | |
317a6104 | 356 | |
ad89f87a | 357 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
fe20ba70 AB |
358 | year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | |
359 | bin2bcd(tm->tm_year % 100); | |
ad89f87a PM |
360 | writew(year, rtc->regbase + RYRCNT); |
361 | } else { | |
362 | year = tm->tm_year % 100; | |
fe20ba70 | 363 | writeb(bin2bcd(year), rtc->regbase + RYRCNT); |
ad89f87a | 364 | } |
317a6104 PM |
365 | |
366 | /* Start RTC */ | |
367 | tmp = readb(rtc->regbase + RCR2); | |
368 | tmp &= ~RCR2_RESET; | |
369 | tmp |= RCR2_RTCEN | RCR2_START; | |
370 | writeb(tmp, rtc->regbase + RCR2); | |
371 | ||
372 | spin_unlock_irq(&rtc->lock); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
1b73e6ae JL |
377 | static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) |
378 | { | |
379 | unsigned int byte; | |
15d82d22 | 380 | int value = -1; /* return -1 for ignored values */ |
1b73e6ae JL |
381 | |
382 | byte = readb(rtc->regbase + reg_off); | |
383 | if (byte & AR_ENB) { | |
384 | byte &= ~AR_ENB; /* strip the enable bit */ | |
fe20ba70 | 385 | value = bcd2bin(byte); |
1b73e6ae JL |
386 | } |
387 | ||
388 | return value; | |
389 | } | |
390 | ||
391 | static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
392 | { | |
85368bb9 | 393 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
b420b1a7 | 394 | struct rtc_time *tm = &wkalrm->time; |
1b73e6ae JL |
395 | |
396 | spin_lock_irq(&rtc->lock); | |
397 | ||
398 | tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); | |
399 | tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); | |
400 | tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); | |
401 | tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); | |
402 | tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); | |
403 | tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); | |
404 | if (tm->tm_mon > 0) | |
405 | tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ | |
1b73e6ae | 406 | |
0d103e90 DB |
407 | wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; |
408 | ||
1b73e6ae JL |
409 | spin_unlock_irq(&rtc->lock); |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, | |
415 | int value, int reg_off) | |
416 | { | |
417 | /* < 0 for a value that is ignored */ | |
418 | if (value < 0) | |
419 | writeb(0, rtc->regbase + reg_off); | |
420 | else | |
fe20ba70 | 421 | writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); |
1b73e6ae JL |
422 | } |
423 | ||
1b73e6ae JL |
424 | static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) |
425 | { | |
85368bb9 | 426 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
1b73e6ae JL |
427 | unsigned int rcr1; |
428 | struct rtc_time *tm = &wkalrm->time; | |
8441189e | 429 | int mon; |
1b73e6ae JL |
430 | |
431 | spin_lock_irq(&rtc->lock); | |
432 | ||
15c945c3 | 433 | /* disable alarm interrupt and clear the alarm flag */ |
1b73e6ae | 434 | rcr1 = readb(rtc->regbase + RCR1); |
b420b1a7 | 435 | rcr1 &= ~(RCR1_AF | RCR1_AIE); |
15c945c3 | 436 | writeb(rcr1, rtc->regbase + RCR1); |
1b73e6ae | 437 | |
1b73e6ae JL |
438 | /* set alarm time */ |
439 | sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); | |
440 | sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); | |
441 | sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); | |
442 | sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); | |
443 | sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); | |
444 | mon = tm->tm_mon; | |
445 | if (mon >= 0) | |
446 | mon += 1; | |
447 | sh_rtc_write_alarm_value(rtc, mon, RMONAR); | |
448 | ||
15c945c3 JL |
449 | if (wkalrm->enabled) { |
450 | rcr1 |= RCR1_AIE; | |
451 | writeb(rcr1, rtc->regbase + RCR1); | |
452 | } | |
1b73e6ae JL |
453 | |
454 | spin_unlock_irq(&rtc->lock); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
8bc57e7f | 459 | static const struct rtc_class_ops sh_rtc_ops = { |
317a6104 PM |
460 | .read_time = sh_rtc_read_time, |
461 | .set_time = sh_rtc_set_time, | |
1b73e6ae JL |
462 | .read_alarm = sh_rtc_read_alarm, |
463 | .set_alarm = sh_rtc_set_alarm, | |
317a6104 | 464 | .proc = sh_rtc_proc, |
16380c15 | 465 | .alarm_irq_enable = sh_rtc_alarm_irq_enable, |
317a6104 PM |
466 | }; |
467 | ||
5c9740a8 | 468 | static int __init sh_rtc_probe(struct platform_device *pdev) |
317a6104 PM |
469 | { |
470 | struct sh_rtc *rtc; | |
471 | struct resource *res; | |
063adc75 PM |
472 | char clk_name[6]; |
473 | int clk_id, ret; | |
317a6104 | 474 | |
0209affa | 475 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
317a6104 PM |
476 | if (unlikely(!rtc)) |
477 | return -ENOMEM; | |
478 | ||
479 | spin_lock_init(&rtc->lock); | |
480 | ||
b420b1a7 | 481 | /* get periodic/carry/alarm irqs */ |
2641dc92 | 482 | ret = platform_get_irq(pdev, 0); |
2fac6674 | 483 | if (unlikely(ret <= 0)) { |
5e084a15 | 484 | dev_err(&pdev->dev, "No IRQ resource\n"); |
0209affa | 485 | return -ENOENT; |
317a6104 | 486 | } |
063adc75 | 487 | |
2641dc92 | 488 | rtc->periodic_irq = ret; |
5e084a15 MD |
489 | rtc->carry_irq = platform_get_irq(pdev, 1); |
490 | rtc->alarm_irq = platform_get_irq(pdev, 2); | |
317a6104 PM |
491 | |
492 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
dab5aec6 CB |
493 | if (!res) |
494 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
317a6104 PM |
495 | if (unlikely(res == NULL)) { |
496 | dev_err(&pdev->dev, "No IO resource\n"); | |
0209affa | 497 | return -ENOENT; |
317a6104 PM |
498 | } |
499 | ||
063adc75 | 500 | rtc->regsize = resource_size(res); |
317a6104 | 501 | |
0209affa JH |
502 | rtc->res = devm_request_mem_region(&pdev->dev, res->start, |
503 | rtc->regsize, pdev->name); | |
504 | if (unlikely(!rtc->res)) | |
505 | return -EBUSY; | |
317a6104 | 506 | |
0209affa JH |
507 | rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start, |
508 | rtc->regsize); | |
509 | if (unlikely(!rtc->regbase)) | |
510 | return -EINVAL; | |
317a6104 | 511 | |
dab5aec6 CB |
512 | if (!pdev->dev.of_node) { |
513 | clk_id = pdev->id; | |
514 | /* With a single device, the clock id is still "rtc0" */ | |
515 | if (clk_id < 0) | |
516 | clk_id = 0; | |
063adc75 | 517 | |
dab5aec6 CB |
518 | snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); |
519 | } else | |
520 | snprintf(clk_name, sizeof(clk_name), "fck"); | |
063adc75 | 521 | |
0209affa | 522 | rtc->clk = devm_clk_get(&pdev->dev, clk_name); |
063adc75 PM |
523 | if (IS_ERR(rtc->clk)) { |
524 | /* | |
525 | * No error handling for rtc->clk intentionally, not all | |
526 | * platforms will have a unique clock for the RTC, and | |
527 | * the clk API can handle the struct clk pointer being | |
528 | * NULL. | |
529 | */ | |
530 | rtc->clk = NULL; | |
531 | } | |
532 | ||
1097998d AB |
533 | rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); |
534 | if (IS_ERR(rtc->rtc_dev)) | |
535 | return PTR_ERR(rtc->rtc_dev); | |
536 | ||
063adc75 PM |
537 | clk_enable(rtc->clk); |
538 | ||
ad89f87a | 539 | rtc->capabilities = RTC_DEF_CAPABILITIES; |
dab5aec6 CB |
540 | |
541 | #ifdef CONFIG_SUPERH | |
e58c18d4 JH |
542 | if (dev_get_platdata(&pdev->dev)) { |
543 | struct sh_rtc_platform_info *pinfo = | |
544 | dev_get_platdata(&pdev->dev); | |
ad89f87a PM |
545 | |
546 | /* | |
547 | * Some CPUs have special capabilities in addition to the | |
548 | * default set. Add those in here. | |
549 | */ | |
550 | rtc->capabilities |= pinfo->capabilities; | |
551 | } | |
dab5aec6 | 552 | #endif |
ad89f87a | 553 | |
5e084a15 MD |
554 | if (rtc->carry_irq <= 0) { |
555 | /* register shared periodic/carry/alarm irq */ | |
0209affa JH |
556 | ret = devm_request_irq(&pdev->dev, rtc->periodic_irq, |
557 | sh_rtc_shared, 0, "sh-rtc", rtc); | |
5e084a15 MD |
558 | if (unlikely(ret)) { |
559 | dev_err(&pdev->dev, | |
560 | "request IRQ failed with %d, IRQ %d\n", ret, | |
561 | rtc->periodic_irq); | |
562 | goto err_unmap; | |
563 | } | |
564 | } else { | |
565 | /* register periodic/carry/alarm irqs */ | |
0209affa JH |
566 | ret = devm_request_irq(&pdev->dev, rtc->periodic_irq, |
567 | sh_rtc_periodic, 0, "sh-rtc period", rtc); | |
5e084a15 MD |
568 | if (unlikely(ret)) { |
569 | dev_err(&pdev->dev, | |
570 | "request period IRQ failed with %d, IRQ %d\n", | |
571 | ret, rtc->periodic_irq); | |
572 | goto err_unmap; | |
573 | } | |
b420b1a7 | 574 | |
0209affa JH |
575 | ret = devm_request_irq(&pdev->dev, rtc->carry_irq, |
576 | sh_rtc_interrupt, 0, "sh-rtc carry", rtc); | |
5e084a15 MD |
577 | if (unlikely(ret)) { |
578 | dev_err(&pdev->dev, | |
579 | "request carry IRQ failed with %d, IRQ %d\n", | |
580 | ret, rtc->carry_irq); | |
5e084a15 MD |
581 | goto err_unmap; |
582 | } | |
b420b1a7 | 583 | |
0209affa JH |
584 | ret = devm_request_irq(&pdev->dev, rtc->alarm_irq, |
585 | sh_rtc_alarm, 0, "sh-rtc alarm", rtc); | |
5e084a15 MD |
586 | if (unlikely(ret)) { |
587 | dev_err(&pdev->dev, | |
588 | "request alarm IRQ failed with %d, IRQ %d\n", | |
589 | ret, rtc->alarm_irq); | |
5e084a15 MD |
590 | goto err_unmap; |
591 | } | |
b420b1a7 AC |
592 | } |
593 | ||
5c9740a8 AZ |
594 | platform_set_drvdata(pdev, rtc); |
595 | ||
9cd88b90 | 596 | /* everything disabled by default */ |
9cd88b90 MD |
597 | sh_rtc_setaie(&pdev->dev, 0); |
598 | sh_rtc_setcie(&pdev->dev, 0); | |
edf22477 | 599 | |
1097998d | 600 | rtc->rtc_dev->ops = &sh_rtc_ops; |
5c9740a8 AZ |
601 | rtc->rtc_dev->max_user_freq = 256; |
602 | ||
beee05df AB |
603 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
604 | rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_1900; | |
605 | rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_9999; | |
606 | } else { | |
607 | rtc->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0); | |
608 | rtc->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59); | |
edf22477 MD |
609 | } |
610 | ||
1097998d AB |
611 | ret = rtc_register_device(rtc->rtc_dev); |
612 | if (ret) | |
613 | goto err_unmap; | |
614 | ||
7a8fe8e3 | 615 | device_init_wakeup(&pdev->dev, 1); |
317a6104 PM |
616 | return 0; |
617 | ||
0305794c | 618 | err_unmap: |
063adc75 | 619 | clk_disable(rtc->clk); |
317a6104 PM |
620 | |
621 | return ret; | |
622 | } | |
623 | ||
5c9740a8 | 624 | static int __exit sh_rtc_remove(struct platform_device *pdev) |
317a6104 PM |
625 | { |
626 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
627 | ||
317a6104 | 628 | sh_rtc_setaie(&pdev->dev, 0); |
9cd88b90 | 629 | sh_rtc_setcie(&pdev->dev, 0); |
317a6104 | 630 | |
063adc75 | 631 | clk_disable(rtc->clk); |
317a6104 PM |
632 | |
633 | return 0; | |
634 | } | |
faa9fa8e MD |
635 | |
636 | static void sh_rtc_set_irq_wake(struct device *dev, int enabled) | |
637 | { | |
85368bb9 | 638 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
faa9fa8e | 639 | |
dced35ae | 640 | irq_set_irq_wake(rtc->periodic_irq, enabled); |
063adc75 | 641 | |
faa9fa8e | 642 | if (rtc->carry_irq > 0) { |
dced35ae TG |
643 | irq_set_irq_wake(rtc->carry_irq, enabled); |
644 | irq_set_irq_wake(rtc->alarm_irq, enabled); | |
faa9fa8e | 645 | } |
faa9fa8e MD |
646 | } |
647 | ||
5d05e815 | 648 | static int __maybe_unused sh_rtc_suspend(struct device *dev) |
faa9fa8e MD |
649 | { |
650 | if (device_may_wakeup(dev)) | |
651 | sh_rtc_set_irq_wake(dev, 1); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
5d05e815 | 656 | static int __maybe_unused sh_rtc_resume(struct device *dev) |
faa9fa8e MD |
657 | { |
658 | if (device_may_wakeup(dev)) | |
659 | sh_rtc_set_irq_wake(dev, 0); | |
660 | ||
661 | return 0; | |
662 | } | |
663 | ||
0ed50544 | 664 | static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume); |
faa9fa8e | 665 | |
dab5aec6 CB |
666 | static const struct of_device_id sh_rtc_of_match[] = { |
667 | { .compatible = "renesas,sh-rtc", }, | |
668 | { /* sentinel */ } | |
669 | }; | |
670 | MODULE_DEVICE_TABLE(of, sh_rtc_of_match); | |
671 | ||
317a6104 PM |
672 | static struct platform_driver sh_rtc_platform_driver = { |
673 | .driver = { | |
1b73e6ae | 674 | .name = DRV_NAME, |
0ed50544 | 675 | .pm = &sh_rtc_pm_ops, |
dab5aec6 | 676 | .of_match_table = sh_rtc_of_match, |
317a6104 | 677 | }, |
5c9740a8 | 678 | .remove = __exit_p(sh_rtc_remove), |
317a6104 PM |
679 | }; |
680 | ||
deed5a9d | 681 | module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe); |
317a6104 PM |
682 | |
683 | MODULE_DESCRIPTION("SuperH on-chip RTC driver"); | |
b420b1a7 AC |
684 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, " |
685 | "Jamie Lenehan <lenehan@twibble.org>, " | |
686 | "Angelo Castello <angelo.castello@st.com>"); | |
4ff6f024 | 687 | MODULE_LICENSE("GPL v2"); |
ad28a07b | 688 | MODULE_ALIAS("platform:" DRV_NAME); |