[linux-2.6-block.git] / drivers / rtc / rtc-sa1100.c

/*
 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
 *
 * Copyright (c) 2000 Nils Faerber
 *
 * Based on rtc.c by Paul Gortmaker
 *
 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
 *
 * Modifications from:
 *   CIH <cih@coventive.com>
 *   Nicolas Pitre <nico@fluxnic.net>
 *   Andrew Christian <andrew.christian@hp.com>
 *
 * Converted to the RTC subsystem and Driver Model
 *   by Richard Purdie <rpurdie@rpsys.net>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include <linux/pm.h>
#include <linux/bitops.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#ifdef CONFIG_ARCH_PXA
#include <mach/regs-rtc.h>
#endif

#define RTC_DEF_DIVIDER		(32768 - 1)
#define RTC_DEF_TRIM		0

static const unsigned long RTC_FREQ = 1024;
static DEFINE_SPINLOCK(sa1100_rtc_lock);

/*
 * Calculate the next alarm time given the requested alarm time mask
 * and the current time.
 */
static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now,
	struct rtc_time *alrm)
{
	unsigned long next_time;
	unsigned long now_time;

	next->tm_year = now->tm_year;
	next->tm_mon = now->tm_mon;
	next->tm_mday = now->tm_mday;
	next->tm_hour = alrm->tm_hour;
	next->tm_min = alrm->tm_min;
	next->tm_sec = alrm->tm_sec;

	rtc_tm_to_time(now, &now_time);
	rtc_tm_to_time(next, &next_time);

	if (next_time < now_time) {
		/* Advance one day */
		next_time += 60 * 60 * 24;
		rtc_time_to_tm(next_time, next);
	}
}

static int rtc_update_alarm(struct rtc_time *alrm)
{
	struct rtc_time alarm_tm, now_tm;
	unsigned long now, time;
	int ret;

	do {
		now = RCNR;
		rtc_time_to_tm(now, &now_tm);
		rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
		ret = rtc_tm_to_time(&alarm_tm, &time);
		if (ret != 0)
			break;

		RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
		RTAR = time;
	} while (now != RCNR);

	return ret;
}

static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = to_platform_device(dev_id);
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned int rtsr;
	unsigned long events = 0;

	spin_lock(&sa1100_rtc_lock);

	rtsr = RTSR;
	/* clear interrupt sources */
	RTSR = 0;
	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	 * See also the comments in sa1100_rtc_probe(). */
	if (rtsr & (RTSR_ALE | RTSR_HZE)) {
		/* This is the original code, before there was the if test
		 * above. This code does not clear interrupts that were not
		 * enabled. */
		RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2);
	} else {
		/* For some reason, it is possible to enter this routine
		 * without interruptions enabled, it has been tested with
		 * several units (Bug in SA11xx chip?).
		 *
		 * This situation leads to an infinite "loop" of interrupt
		 * routine calling and as a result the processor seems to
		 * lock on its first call to open(). */
		RTSR = RTSR_AL | RTSR_HZ;
	}

	/* clear alarm interrupt if it has occurred */
	if (rtsr & RTSR_AL)
		rtsr &= ~RTSR_ALE;
	RTSR = rtsr & (RTSR_ALE | RTSR_HZE);

	/* update irq data & counter */
	if (rtsr & RTSR_AL)
		events |= RTC_AF | RTC_IRQF;
	if (rtsr & RTSR_HZ)
		events |= RTC_UF | RTC_IRQF;

	rtc_update_irq(rtc, 1, events);

	spin_unlock(&sa1100_rtc_lock);

	return IRQ_HANDLED;
}

static int sa1100_rtc_open(struct device *dev)
{
	int ret;
	struct platform_device *plat_dev = to_platform_device(dev);
	struct rtc_device *rtc = platform_get_drvdata(plat_dev);

	ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
		"rtc 1Hz", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
		goto fail_ui;
	}
	ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
		"rtc Alrm", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
		goto fail_ai;
	}
	rtc->max_user_freq = RTC_FREQ;
	rtc_irq_set_freq(rtc, NULL, RTC_FREQ);

	return 0;

 fail_ai:
	free_irq(IRQ_RTC1Hz, dev);
 fail_ui:
	return ret;
}

static void sa1100_rtc_release(struct device *dev)
{
	spin_lock_irq(&sa1100_rtc_lock);
	RTSR = 0;
	spin_unlock_irq(&sa1100_rtc_lock);

	free_irq(IRQ_RTCAlrm, dev);
	free_irq(IRQ_RTC1Hz, dev);
}

static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	spin_lock_irq(&sa1100_rtc_lock);
	if (enabled)
		RTSR |= RTSR_ALE;
	else
		RTSR &= ~RTSR_ALE;
	spin_unlock_irq(&sa1100_rtc_lock);
	return 0;
}

static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	rtc_time_to_tm(RCNR, tm);
	return 0;
}

static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned long time;
	int ret;

	ret = rtc_tm_to_time(tm, &time);
	if (ret == 0)
		RCNR = time;
	return ret;
}

static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	u32	rtsr;

	rtsr = RTSR;
	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
	return 0;
}

static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int ret;

	spin_lock_irq(&sa1100_rtc_lock);
	ret = rtc_update_alarm(&alrm->time);
	if (ret == 0) {
		if (alrm->enabled)
			RTSR |= RTSR_ALE;
		else
			RTSR &= ~RTSR_ALE;
	}
	spin_unlock_irq(&sa1100_rtc_lock);

	return ret;
}

static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
{
	seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR);
	seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR);

	return 0;
}

static const struct rtc_class_ops sa1100_rtc_ops = {
	.open = sa1100_rtc_open,
	.release = sa1100_rtc_release,
	.read_time = sa1100_rtc_read_time,
	.set_time = sa1100_rtc_set_time,
	.read_alarm = sa1100_rtc_read_alarm,
	.set_alarm = sa1100_rtc_set_alarm,
	.proc = sa1100_rtc_proc,
	.alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
};

static int sa1100_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;

	/*
	 * According to the manual we should be able to let RTTR be zero
	 * and then a default diviser for a 32.768KHz clock is used.
	 * Apparently this doesn't work, at least for my SA1110 rev 5.
	 * If the clock divider is uninitialized then reset it to the
	 * default value to get the 1Hz clock.
	 */
	if (RTTR == 0) {
		RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
		dev_warn(&pdev->dev, "warning: "
			"initializing default clock divider/trim value\n");
		/* The current RTC value probably doesn't make sense either */
		RCNR = 0;
	}

	device_init_wakeup(&pdev->dev, 1);

	rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
		THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	platform_set_drvdata(pdev, rtc);

	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	 * See also the comments in sa1100_rtc_interrupt().
	 *
	 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
	 * interrupt pending, even though interrupts were never enabled.
	 * In this case, this bit it must be reset before enabling
	 * interruptions to avoid a nonexistent interrupt to occur.
	 *
	 * In principle, the same problem would apply to bit 0, although it has
	 * never been observed to happen.
	 *
	 * This issue is addressed both here and in sa1100_rtc_interrupt().
	 * If the issue is not addressed here, in the times when the processor
	 * wakes up with the bit set there will be one spurious interrupt.
	 *
	 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
	 * safe side, once the condition that lead to this strange
	 * initialization is unknown and could in principle happen during
	 * normal processing.
	 *
	 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
	 * the corresponding bits in RTSR. */
	RTSR = RTSR_AL | RTSR_HZ;

	return 0;
}

static int sa1100_rtc_remove(struct platform_device *pdev)
{
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	if (rtc)
		rtc_device_unregister(rtc);

	return 0;
}

#ifdef CONFIG_PM
static int sa1100_rtc_suspend(struct device *dev)
{
	if (device_may_wakeup(dev))
		enable_irq_wake(IRQ_RTCAlrm);
	return 0;
}

static int sa1100_rtc_resume(struct device *dev)
{
	if (device_may_wakeup(dev))
		disable_irq_wake(IRQ_RTCAlrm);
	return 0;
}

static const struct dev_pm_ops sa1100_rtc_pm_ops = {
	.suspend	= sa1100_rtc_suspend,
	.resume		= sa1100_rtc_resume,
};
#endif

static struct platform_driver sa1100_rtc_driver = {
	.probe		= sa1100_rtc_probe,
	.remove		= sa1100_rtc_remove,
	.driver		= {
		.name	= "sa1100-rtc",
#ifdef CONFIG_PM
		.pm	= &sa1100_rtc_pm_ops,
#endif
	},
};

module_platform_driver(sa1100_rtc_driver);

MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sa1100-rtc");
Commit	Line	Data
e842f1c8 RP	1	/*
	2	* Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
	3	*
	4	* Copyright (c) 2000 Nils Faerber
	5	*
	6	* Based on rtc.c by Paul Gortmaker
	7	*
	8	* Original Driver by Nils Faerber <nils@kernelconcepts.de>
	9	*
	10	* Modifications from:
	11	* CIH <cih@coventive.com>
2f82af08	12	* Nicolas Pitre <nico@fluxnic.net>
e842f1c8 RP	13	* Andrew Christian <andrew.christian@hp.com>
	14	*
	15	* Converted to the RTC subsystem and Driver Model
	16	* by Richard Purdie <rpurdie@rpsys.net>
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*/
	23
	24	#include <linux/platform_device.h>
	25	#include <linux/module.h>
	26	#include <linux/rtc.h>
	27	#include <linux/init.h>
	28	#include <linux/fs.h>
	29	#include <linux/interrupt.h>
a0164a57	30	#include <linux/string.h>
e842f1c8	31	#include <linux/pm.h>
a0164a57	32	#include <linux/bitops.h>
e842f1c8	33
a09e64fb	34	#include <mach/hardware.h>
e842f1c8	35	#include <asm/irq.h>
e842f1c8	36
a0164a57 RK	37	#ifdef CONFIG_ARCH_PXA
	38	#include <mach/regs-rtc.h>
	39	#endif
	40
a404ad1f	41	#define RTC_DEF_DIVIDER (32768 - 1)
e842f1c8	42	#define RTC_DEF_TRIM 0
a0164a57 RK	43
a0164a57 RK	44	static const unsigned long RTC_FREQ = 1024;
a0164a57 RK	45	static DEFINE_SPINLOCK(sa1100_rtc_lock);
a0164a57 RK	46
797276ec RK	47	/*
	48	* Calculate the next alarm time given the requested alarm time mask
	49	* and the current time.
	50	*/
a404ad1f MRJ	51	static void rtc_next_alarm_time(struct rtc_time next, struct rtc_time now,
a404ad1f MRJ	52	struct rtc_time *alrm)
797276ec RK	53	{
	54	unsigned long next_time;
	55	unsigned long now_time;
	56
	57	next->tm_year = now->tm_year;
	58	next->tm_mon = now->tm_mon;
	59	next->tm_mday = now->tm_mday;
	60	next->tm_hour = alrm->tm_hour;
	61	next->tm_min = alrm->tm_min;
	62	next->tm_sec = alrm->tm_sec;
	63
	64	rtc_tm_to_time(now, &now_time);
	65	rtc_tm_to_time(next, &next_time);
	66
	67	if (next_time < now_time) {
	68	/* Advance one day */
	69	next_time += 60 * 60 * 24;
	70	rtc_time_to_tm(next_time, next);
	71	}
	72	}
	73
57270fcd RK	74	static int rtc_update_alarm(struct rtc_time *alrm)
	75	{
	76	struct rtc_time alarm_tm, now_tm;
	77	unsigned long now, time;
	78	int ret;
	79
	80	do {
	81	now = RCNR;
	82	rtc_time_to_tm(now, &now_tm);
	83	rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
	84	ret = rtc_tm_to_time(&alarm_tm, &time);
	85	if (ret != 0)
	86	break;
	87
	88	RTSR = RTSR & (RTSR_HZE\|RTSR_ALE\|RTSR_AL);
	89	RTAR = time;
	90	} while (now != RCNR);
	91
	92	return ret;
	93	}
	94
7d12e780	95	static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
e842f1c8 RP	96	{
e842f1c8 RP	97	struct platform_device *pdev = to_platform_device(dev_id);
a0164a57	98	struct rtc_device *rtc = platform_get_drvdata(pdev);
e842f1c8 RP	99	unsigned int rtsr;
	100	unsigned long events = 0;
	101
a0164a57	102	spin_lock(&sa1100_rtc_lock);
e842f1c8	103
a0164a57	104	rtsr = RTSR;
e842f1c8	105	/* clear interrupt sources */
a0164a57	106	RTSR = 0;
7decaa55 MRJ	107	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	108	* See also the comments in sa1100_rtc_probe(). */
	109	if (rtsr & (RTSR_ALE \| RTSR_HZE)) {
	110	/* This is the original code, before there was the if test
	111	* above. This code does not clear interrupts that were not
	112	* enabled. */
a0164a57	113	RTSR = (RTSR_AL \| RTSR_HZ) & (rtsr >> 2);
7decaa55 MRJ	114	} else {
	115	/* For some reason, it is possible to enter this routine
	116	* without interruptions enabled, it has been tested with
	117	* several units (Bug in SA11xx chip?).
	118	*
	119	* This situation leads to an infinite "loop" of interrupt
	120	* routine calling and as a result the processor seems to
	121	* lock on its first call to open(). */
a0164a57	122	RTSR = RTSR_AL \| RTSR_HZ;
7decaa55	123	}
e842f1c8 RP	124
	125	/* clear alarm interrupt if it has occurred */
	126	if (rtsr & RTSR_AL)
	127	rtsr &= ~RTSR_ALE;
a0164a57	128	RTSR = rtsr & (RTSR_ALE \| RTSR_HZE);
e842f1c8 RP	129
	130	/* update irq data & counter */
	131	if (rtsr & RTSR_AL)
	132	events \|= RTC_AF \| RTC_IRQF;
	133	if (rtsr & RTSR_HZ)
	134	events \|= RTC_UF \| RTC_IRQF;
	135
a0164a57	136	rtc_update_irq(rtc, 1, events);
e842f1c8	137
a0164a57	138	spin_unlock(&sa1100_rtc_lock);
e842f1c8 RP	139
	140	return IRQ_HANDLED;
	141	}
	142
e842f1c8 RP	143	static int sa1100_rtc_open(struct device *dev)
	144	{
	145	int ret;
a0164a57 RK	146	struct platform_device *plat_dev = to_platform_device(dev);
a0164a57 RK	147	struct rtc_device *rtc = platform_get_drvdata(plat_dev);
e842f1c8	148
a0164a57 RK	149	ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
a0164a57 RK	150	"rtc 1Hz", dev);
e842f1c8	151	if (ret) {
a0164a57	152	dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
e842f1c8 RP	153	goto fail_ui;
e842f1c8 RP	154	}
a0164a57 RK	155	ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
a0164a57 RK	156	"rtc Alrm", dev);
e842f1c8	157	if (ret) {
a0164a57	158	dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
e842f1c8 RP	159	goto fail_ai;
e842f1c8 RP	160	}
a0164a57 RK	161	rtc->max_user_freq = RTC_FREQ;
a0164a57 RK	162	rtc_irq_set_freq(rtc, NULL, RTC_FREQ);
d2ccb52d	163
e842f1c8 RP	164	return 0;
e842f1c8 RP	165
e842f1c8	166	fail_ai:
a0164a57	167	free_irq(IRQ_RTC1Hz, dev);
e842f1c8 RP	168	fail_ui:
	169	return ret;
	170	}
	171
	172	static void sa1100_rtc_release(struct device *dev)
	173	{
a0164a57 RK	174	spin_lock_irq(&sa1100_rtc_lock);
	175	RTSR = 0;
	176	spin_unlock_irq(&sa1100_rtc_lock);
e842f1c8	177
a0164a57 RK	178	free_irq(IRQ_RTCAlrm, dev);
a0164a57 RK	179	free_irq(IRQ_RTC1Hz, dev);
e842f1c8 RP	180	}
e842f1c8 RP	181
16380c15 JS	182	static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
16380c15 JS	183	{
a0164a57	184	spin_lock_irq(&sa1100_rtc_lock);
16380c15	185	if (enabled)
a0164a57	186	RTSR \|= RTSR_ALE;
16380c15	187	else
a0164a57 RK	188	RTSR &= ~RTSR_ALE;
a0164a57 RK	189	spin_unlock_irq(&sa1100_rtc_lock);
16380c15 JS	190	return 0;
	191	}
	192
e842f1c8 RP	193	static int sa1100_rtc_read_time(struct device dev, struct rtc_time tm)
e842f1c8 RP	194	{
a0164a57	195	rtc_time_to_tm(RCNR, tm);
e842f1c8 RP	196	return 0;
	197	}
	198
	199	static int sa1100_rtc_set_time(struct device dev, struct rtc_time tm)
	200	{
	201	unsigned long time;
	202	int ret;
	203
	204	ret = rtc_tm_to_time(tm, &time);
	205	if (ret == 0)
a0164a57	206	RCNR = time;
e842f1c8 RP	207	return ret;
	208	}
	209
	210	static int sa1100_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	211	{
a0164a57	212	u32 rtsr;
32b49da4	213
a0164a57	214	rtsr = RTSR;
32b49da4 DB	215	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
32b49da4 DB	216	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
e842f1c8 RP	217	return 0;
	218	}
	219
	220	static int sa1100_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	221	{
a0164a57	222	int ret;
e842f1c8	223
a0164a57	224	spin_lock_irq(&sa1100_rtc_lock);
57270fcd RK	225	ret = rtc_update_alarm(&alrm->time);
	226	if (ret == 0) {
	227	if (alrm->enabled)
	228	RTSR \|= RTSR_ALE;
	229	else
	230	RTSR &= ~RTSR_ALE;
	231	}
a0164a57	232	spin_unlock_irq(&sa1100_rtc_lock);
e842f1c8	233
a0164a57	234	return ret;
e842f1c8 RP	235	}
	236
	237	static int sa1100_rtc_proc(struct device dev, struct seq_file seq)
	238	{
a0164a57 RK	239	seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR);
a0164a57 RK	240	seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR);
e842f1c8 RP	241
	242	return 0;
	243	}
	244
ff8371ac	245	static const struct rtc_class_ops sa1100_rtc_ops = {
e842f1c8	246	.open = sa1100_rtc_open,
e842f1c8	247	.release = sa1100_rtc_release,
e842f1c8 RP	248	.read_time = sa1100_rtc_read_time,
	249	.set_time = sa1100_rtc_set_time,
	250	.read_alarm = sa1100_rtc_read_alarm,
	251	.set_alarm = sa1100_rtc_set_alarm,
	252	.proc = sa1100_rtc_proc,
16380c15	253	.alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
e842f1c8 RP	254	};
	255
	256	static int sa1100_rtc_probe(struct platform_device *pdev)
	257	{
a0164a57	258	struct rtc_device *rtc;
e842f1c8 RP	259
	260	/*
	261	* According to the manual we should be able to let RTTR be zero
	262	* and then a default diviser for a 32.768KHz clock is used.
	263	* Apparently this doesn't work, at least for my SA1110 rev 5.
	264	* If the clock divider is uninitialized then reset it to the
	265	* default value to get the 1Hz clock.
	266	*/
a0164a57 RK	267	if (RTTR == 0) {
	268	RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
	269	dev_warn(&pdev->dev, "warning: "
	270	"initializing default clock divider/trim value\n");
e842f1c8	271	/* The current RTC value probably doesn't make sense either */
a0164a57	272	RCNR = 0;
e842f1c8 RP	273	}
e842f1c8 RP	274
e5a2c9cc UL	275	device_init_wakeup(&pdev->dev, 1);
e5a2c9cc UL	276
a0164a57 RK	277	rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
	278	THIS_MODULE);
	279
	280	if (IS_ERR(rtc))
	281	return PTR_ERR(rtc);
	282
	283	platform_set_drvdata(pdev, rtc);
	284
7decaa55 MRJ	285	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	286	* See also the comments in sa1100_rtc_interrupt().
	287	*
	288	* Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
	289	* interrupt pending, even though interrupts were never enabled.
	290	* In this case, this bit it must be reset before enabling
	291	* interruptions to avoid a nonexistent interrupt to occur.
	292	*
	293	* In principle, the same problem would apply to bit 0, although it has
	294	* never been observed to happen.
	295	*
	296	* This issue is addressed both here and in sa1100_rtc_interrupt().
	297	* If the issue is not addressed here, in the times when the processor
	298	* wakes up with the bit set there will be one spurious interrupt.
	299	*
	300	* The issue is also dealt with in sa1100_rtc_interrupt() to be on the
	301	* safe side, once the condition that lead to this strange
	302	* initialization is unknown and could in principle happen during
	303	* normal processing.
	304	*
	305	* Notice that clearing bit 1 and 0 is accomplished by writting ONES to
	306	* the corresponding bits in RTSR. */
a0164a57	307	RTSR = RTSR_AL \| RTSR_HZ;
7decaa55	308
e842f1c8 RP	309	return 0;
	310	}
	311
	312	static int sa1100_rtc_remove(struct platform_device *pdev)
	313	{
a0164a57 RK	314	struct rtc_device *rtc = platform_get_drvdata(pdev);
	315
	316	if (rtc)
	317	rtc_device_unregister(rtc);
e842f1c8 RP	318
	319	return 0;
	320	}
	321
6bc54e69	322	#ifdef CONFIG_PM
5d027cd2	323	static int sa1100_rtc_suspend(struct device *dev)
6bc54e69	324	{
5d027cd2	325	if (device_may_wakeup(dev))
a0164a57	326	enable_irq_wake(IRQ_RTCAlrm);
6bc54e69 RK	327	return 0;
	328	}
	329
5d027cd2	330	static int sa1100_rtc_resume(struct device *dev)
6bc54e69	331	{
5d027cd2	332	if (device_may_wakeup(dev))
a0164a57	333	disable_irq_wake(IRQ_RTCAlrm);
6bc54e69 RK	334	return 0;
6bc54e69 RK	335	}
5d027cd2	336
47145210	337	static const struct dev_pm_ops sa1100_rtc_pm_ops = {
5d027cd2 HZ	338	.suspend = sa1100_rtc_suspend,
	339	.resume = sa1100_rtc_resume,
	340	};
6bc54e69 RK	341	#endif
6bc54e69 RK	342
e842f1c8 RP	343	static struct platform_driver sa1100_rtc_driver = {
	344	.probe = sa1100_rtc_probe,
	345	.remove = sa1100_rtc_remove,
	346	.driver = {
5d027cd2 HZ	347	.name = "sa1100-rtc",
	348	#ifdef CONFIG_PM
	349	.pm = &sa1100_rtc_pm_ops,
	350	#endif
e842f1c8 RP	351	},
	352	};
	353
0c4eae66	354	module_platform_driver(sa1100_rtc_driver);
e842f1c8 RP	355
	356	MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
	357	MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
	358	MODULE_LICENSE("GPL");
ad28a07b	359	MODULE_ALIAS("platform:sa1100-rtc");