Commit | Line | Data |
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e842f1c8 RP |
1 | /* |
2 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
3 | * | |
4 | * Copyright (c) 2000 Nils Faerber | |
5 | * | |
6 | * Based on rtc.c by Paul Gortmaker | |
7 | * | |
8 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
9 | * | |
10 | * Modifications from: | |
11 | * CIH <cih@coventive.com> | |
2f82af08 | 12 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
13 | * Andrew Christian <andrew.christian@hp.com> |
14 | * | |
15 | * Converted to the RTC subsystem and Driver Model | |
16 | * by Richard Purdie <rpurdie@rpsys.net> | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/module.h> | |
8e8bbcb3 | 26 | #include <linux/clk.h> |
e842f1c8 RP |
27 | #include <linux/rtc.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/fs.h> | |
30 | #include <linux/interrupt.h> | |
3888c090 | 31 | #include <linux/slab.h> |
a0164a57 | 32 | #include <linux/string.h> |
8bec2e9e | 33 | #include <linux/of.h> |
e842f1c8 | 34 | #include <linux/pm.h> |
a0164a57 | 35 | #include <linux/bitops.h> |
23019a73 | 36 | #include <linux/io.h> |
e842f1c8 | 37 | |
a09e64fb | 38 | #include <mach/hardware.h> |
905cdc88 | 39 | #include <mach/irqs.h> |
e842f1c8 | 40 | |
3888c090 | 41 | #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) |
a0164a57 RK |
42 | #include <mach/regs-rtc.h> |
43 | #endif | |
44 | ||
8c0961ba RH |
45 | #include "rtc-sa1100.h" |
46 | ||
a404ad1f | 47 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 | 48 | #define RTC_DEF_TRIM 0 |
3888c090 | 49 | #define RTC_FREQ 1024 |
a0164a57 | 50 | |
a0164a57 | 51 | |
7d12e780 | 52 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 | 53 | { |
3888c090 HZ |
54 | struct sa1100_rtc *info = dev_get_drvdata(dev_id); |
55 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
56 | unsigned int rtsr; |
57 | unsigned long events = 0; | |
58 | ||
3888c090 | 59 | spin_lock(&info->lock); |
e842f1c8 | 60 | |
a0164a57 | 61 | rtsr = RTSR; |
e842f1c8 | 62 | /* clear interrupt sources */ |
a0164a57 | 63 | RTSR = 0; |
7decaa55 MRJ |
64 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
65 | * See also the comments in sa1100_rtc_probe(). */ | |
66 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
67 | /* This is the original code, before there was the if test | |
68 | * above. This code does not clear interrupts that were not | |
69 | * enabled. */ | |
a0164a57 | 70 | RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2); |
7decaa55 MRJ |
71 | } else { |
72 | /* For some reason, it is possible to enter this routine | |
73 | * without interruptions enabled, it has been tested with | |
74 | * several units (Bug in SA11xx chip?). | |
75 | * | |
76 | * This situation leads to an infinite "loop" of interrupt | |
77 | * routine calling and as a result the processor seems to | |
78 | * lock on its first call to open(). */ | |
a0164a57 | 79 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 80 | } |
e842f1c8 RP |
81 | |
82 | /* clear alarm interrupt if it has occurred */ | |
83 | if (rtsr & RTSR_AL) | |
84 | rtsr &= ~RTSR_ALE; | |
a0164a57 | 85 | RTSR = rtsr & (RTSR_ALE | RTSR_HZE); |
e842f1c8 RP |
86 | |
87 | /* update irq data & counter */ | |
88 | if (rtsr & RTSR_AL) | |
89 | events |= RTC_AF | RTC_IRQF; | |
90 | if (rtsr & RTSR_HZ) | |
91 | events |= RTC_UF | RTC_IRQF; | |
92 | ||
a0164a57 | 93 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 94 | |
3888c090 | 95 | spin_unlock(&info->lock); |
e842f1c8 RP |
96 | |
97 | return IRQ_HANDLED; | |
98 | } | |
99 | ||
e842f1c8 RP |
100 | static int sa1100_rtc_open(struct device *dev) |
101 | { | |
3888c090 HZ |
102 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
103 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
104 | int ret; |
105 | ||
34800598 | 106 | ret = request_irq(info->irq_1hz, sa1100_rtc_interrupt, 0, "rtc 1Hz", dev); |
e842f1c8 | 107 | if (ret) { |
3888c090 | 108 | dev_err(dev, "IRQ %d already in use.\n", info->irq_1hz); |
e842f1c8 RP |
109 | goto fail_ui; |
110 | } | |
34800598 | 111 | ret = request_irq(info->irq_alarm, sa1100_rtc_interrupt, 0, "rtc Alrm", dev); |
e842f1c8 | 112 | if (ret) { |
3888c090 | 113 | dev_err(dev, "IRQ %d already in use.\n", info->irq_alarm); |
e842f1c8 RP |
114 | goto fail_ai; |
115 | } | |
a0164a57 RK |
116 | rtc->max_user_freq = RTC_FREQ; |
117 | rtc_irq_set_freq(rtc, NULL, RTC_FREQ); | |
d2ccb52d | 118 | |
e842f1c8 RP |
119 | return 0; |
120 | ||
e842f1c8 | 121 | fail_ai: |
3888c090 | 122 | free_irq(info->irq_1hz, dev); |
e842f1c8 | 123 | fail_ui: |
8e8bbcb3 | 124 | clk_disable_unprepare(info->clk); |
e842f1c8 RP |
125 | return ret; |
126 | } | |
127 | ||
128 | static void sa1100_rtc_release(struct device *dev) | |
129 | { | |
3888c090 HZ |
130 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
131 | ||
132 | spin_lock_irq(&info->lock); | |
a0164a57 | 133 | RTSR = 0; |
3888c090 | 134 | spin_unlock_irq(&info->lock); |
e842f1c8 | 135 | |
3888c090 HZ |
136 | free_irq(info->irq_alarm, dev); |
137 | free_irq(info->irq_1hz, dev); | |
e842f1c8 RP |
138 | } |
139 | ||
16380c15 JS |
140 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
141 | { | |
3888c090 HZ |
142 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
143 | ||
144 | spin_lock_irq(&info->lock); | |
16380c15 | 145 | if (enabled) |
a0164a57 | 146 | RTSR |= RTSR_ALE; |
16380c15 | 147 | else |
a0164a57 | 148 | RTSR &= ~RTSR_ALE; |
3888c090 | 149 | spin_unlock_irq(&info->lock); |
16380c15 JS |
150 | return 0; |
151 | } | |
152 | ||
e842f1c8 RP |
153 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
154 | { | |
a0164a57 | 155 | rtc_time_to_tm(RCNR, tm); |
e842f1c8 RP |
156 | return 0; |
157 | } | |
158 | ||
159 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
160 | { | |
161 | unsigned long time; | |
162 | int ret; | |
163 | ||
164 | ret = rtc_tm_to_time(tm, &time); | |
165 | if (ret == 0) | |
a0164a57 | 166 | RCNR = time; |
e842f1c8 RP |
167 | return ret; |
168 | } | |
169 | ||
170 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
171 | { | |
a0164a57 | 172 | u32 rtsr; |
32b49da4 | 173 | |
a0164a57 | 174 | rtsr = RTSR; |
32b49da4 DB |
175 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
176 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
177 | return 0; |
178 | } | |
179 | ||
180 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
181 | { | |
3888c090 | 182 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
1d8c38c3 | 183 | unsigned long time; |
a0164a57 | 184 | int ret; |
e842f1c8 | 185 | |
3888c090 | 186 | spin_lock_irq(&info->lock); |
1d8c38c3 HZ |
187 | ret = rtc_tm_to_time(&alrm->time, &time); |
188 | if (ret != 0) | |
189 | goto out; | |
190 | RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL); | |
191 | RTAR = time; | |
192 | if (alrm->enabled) | |
193 | RTSR |= RTSR_ALE; | |
194 | else | |
195 | RTSR &= ~RTSR_ALE; | |
196 | out: | |
3888c090 | 197 | spin_unlock_irq(&info->lock); |
e842f1c8 | 198 | |
a0164a57 | 199 | return ret; |
e842f1c8 RP |
200 | } |
201 | ||
202 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
203 | { | |
a0164a57 RK |
204 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR); |
205 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR); | |
e842f1c8 RP |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
ff8371ac | 210 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 | 211 | .open = sa1100_rtc_open, |
e842f1c8 | 212 | .release = sa1100_rtc_release, |
e842f1c8 RP |
213 | .read_time = sa1100_rtc_read_time, |
214 | .set_time = sa1100_rtc_set_time, | |
215 | .read_alarm = sa1100_rtc_read_alarm, | |
216 | .set_alarm = sa1100_rtc_set_alarm, | |
217 | .proc = sa1100_rtc_proc, | |
16380c15 | 218 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
219 | }; |
220 | ||
8c0961ba | 221 | int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info) |
e842f1c8 | 222 | { |
a0164a57 | 223 | struct rtc_device *rtc; |
8c0961ba | 224 | int ret; |
3888c090 | 225 | |
8c0961ba | 226 | spin_lock_init(&info->lock); |
3888c090 | 227 | |
55d735ef | 228 | info->clk = devm_clk_get(&pdev->dev, NULL); |
8e8bbcb3 HZ |
229 | if (IS_ERR(info->clk)) { |
230 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
55d735ef | 231 | return PTR_ERR(info->clk); |
8e8bbcb3 | 232 | } |
e842f1c8 | 233 | |
0cc0c38e CX |
234 | ret = clk_prepare_enable(info->clk); |
235 | if (ret) | |
66600bbe | 236 | return ret; |
e842f1c8 RP |
237 | /* |
238 | * According to the manual we should be able to let RTTR be zero | |
239 | * and then a default diviser for a 32.768KHz clock is used. | |
240 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
241 | * If the clock divider is uninitialized then reset it to the | |
242 | * default value to get the 1Hz clock. | |
243 | */ | |
a0164a57 RK |
244 | if (RTTR == 0) { |
245 | RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
246 | dev_warn(&pdev->dev, "warning: " | |
247 | "initializing default clock divider/trim value\n"); | |
e842f1c8 | 248 | /* The current RTC value probably doesn't make sense either */ |
a0164a57 | 249 | RCNR = 0; |
e842f1c8 RP |
250 | } |
251 | ||
55d735ef JH |
252 | rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &sa1100_rtc_ops, |
253 | THIS_MODULE); | |
3888c090 | 254 | if (IS_ERR(rtc)) { |
8c0961ba RH |
255 | clk_disable_unprepare(info->clk); |
256 | return PTR_ERR(rtc); | |
3888c090 HZ |
257 | } |
258 | info->rtc = rtc; | |
a0164a57 | 259 | |
7decaa55 MRJ |
260 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
261 | * See also the comments in sa1100_rtc_interrupt(). | |
262 | * | |
263 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
264 | * interrupt pending, even though interrupts were never enabled. | |
265 | * In this case, this bit it must be reset before enabling | |
266 | * interruptions to avoid a nonexistent interrupt to occur. | |
267 | * | |
268 | * In principle, the same problem would apply to bit 0, although it has | |
269 | * never been observed to happen. | |
270 | * | |
271 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
272 | * If the issue is not addressed here, in the times when the processor | |
273 | * wakes up with the bit set there will be one spurious interrupt. | |
274 | * | |
275 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
276 | * safe side, once the condition that lead to this strange | |
277 | * initialization is unknown and could in principle happen during | |
278 | * normal processing. | |
279 | * | |
280 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
281 | * the corresponding bits in RTSR. */ | |
a0164a57 | 282 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 283 | |
e842f1c8 | 284 | return 0; |
8c0961ba RH |
285 | } |
286 | EXPORT_SYMBOL_GPL(sa1100_rtc_init); | |
287 | ||
288 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
289 | { | |
290 | struct sa1100_rtc *info; | |
291 | int irq_1hz, irq_alarm; | |
292 | ||
293 | irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz"); | |
294 | irq_alarm = platform_get_irq_byname(pdev, "rtc alarm"); | |
295 | if (irq_1hz < 0 || irq_alarm < 0) | |
296 | return -ENODEV; | |
297 | ||
298 | info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL); | |
299 | if (!info) | |
300 | return -ENOMEM; | |
301 | info->irq_1hz = irq_1hz; | |
302 | info->irq_alarm = irq_alarm; | |
303 | ||
304 | platform_set_drvdata(pdev, info); | |
305 | device_init_wakeup(&pdev->dev, 1); | |
306 | ||
307 | return sa1100_rtc_init(pdev, info); | |
e842f1c8 RP |
308 | } |
309 | ||
310 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
311 | { | |
3888c090 | 312 | struct sa1100_rtc *info = platform_get_drvdata(pdev); |
a0164a57 | 313 | |
66600bbe | 314 | if (info) |
0cc0c38e | 315 | clk_disable_unprepare(info->clk); |
e842f1c8 RP |
316 | |
317 | return 0; | |
318 | } | |
319 | ||
aaa92fae | 320 | #ifdef CONFIG_PM_SLEEP |
5d027cd2 | 321 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 322 | { |
3888c090 | 323 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 324 | if (device_may_wakeup(dev)) |
3888c090 | 325 | enable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
326 | return 0; |
327 | } | |
328 | ||
5d027cd2 | 329 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 330 | { |
3888c090 | 331 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 332 | if (device_may_wakeup(dev)) |
3888c090 | 333 | disable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
334 | return 0; |
335 | } | |
6bc54e69 RK |
336 | #endif |
337 | ||
aaa92fae JH |
338 | static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend, |
339 | sa1100_rtc_resume); | |
340 | ||
c8a6046e | 341 | #ifdef CONFIG_OF |
dee21a6f | 342 | static const struct of_device_id sa1100_rtc_dt_ids[] = { |
8bec2e9e HZ |
343 | { .compatible = "mrvl,sa1100-rtc", }, |
344 | { .compatible = "mrvl,mmp-rtc", }, | |
345 | {} | |
346 | }; | |
347 | MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids); | |
c8a6046e | 348 | #endif |
8bec2e9e | 349 | |
e842f1c8 RP |
350 | static struct platform_driver sa1100_rtc_driver = { |
351 | .probe = sa1100_rtc_probe, | |
352 | .remove = sa1100_rtc_remove, | |
353 | .driver = { | |
5d027cd2 | 354 | .name = "sa1100-rtc", |
5d027cd2 | 355 | .pm = &sa1100_rtc_pm_ops, |
c8a6046e | 356 | .of_match_table = of_match_ptr(sa1100_rtc_dt_ids), |
e842f1c8 RP |
357 | }, |
358 | }; | |
359 | ||
0c4eae66 | 360 | module_platform_driver(sa1100_rtc_driver); |
e842f1c8 RP |
361 | |
362 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
363 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
364 | MODULE_LICENSE("GPL"); | |
ad28a07b | 365 | MODULE_ALIAS("platform:sa1100-rtc"); |