powerpc/mm: Drop the unnecessary region check
[linux-2.6-block.git] / drivers / rtc / rtc-sa1100.c
CommitLineData
e842f1c8
RP
1/*
2 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
3 *
4 * Copyright (c) 2000 Nils Faerber
5 *
6 * Based on rtc.c by Paul Gortmaker
7 *
8 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
9 *
10 * Modifications from:
11 * CIH <cih@coventive.com>
2f82af08 12 * Nicolas Pitre <nico@fluxnic.net>
e842f1c8
RP
13 * Andrew Christian <andrew.christian@hp.com>
14 *
15 * Converted to the RTC subsystem and Driver Model
16 * by Richard Purdie <rpurdie@rpsys.net>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24#include <linux/platform_device.h>
25#include <linux/module.h>
8e8bbcb3 26#include <linux/clk.h>
e842f1c8
RP
27#include <linux/rtc.h>
28#include <linux/init.h>
29#include <linux/fs.h>
30#include <linux/interrupt.h>
3888c090 31#include <linux/slab.h>
a0164a57 32#include <linux/string.h>
8bec2e9e 33#include <linux/of.h>
e842f1c8 34#include <linux/pm.h>
a0164a57 35#include <linux/bitops.h>
23019a73 36#include <linux/io.h>
e842f1c8 37
90d0ae8e
RH
38#define RTSR_HZE BIT(3) /* HZ interrupt enable */
39#define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */
40#define RTSR_HZ BIT(1) /* HZ rising-edge detected */
41#define RTSR_AL BIT(0) /* RTC alarm detected */
a0164a57 42
8c0961ba
RH
43#include "rtc-sa1100.h"
44
a404ad1f 45#define RTC_DEF_DIVIDER (32768 - 1)
e842f1c8 46#define RTC_DEF_TRIM 0
3888c090 47#define RTC_FREQ 1024
a0164a57 48
a0164a57 49
7d12e780 50static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
e842f1c8 51{
3888c090
HZ
52 struct sa1100_rtc *info = dev_get_drvdata(dev_id);
53 struct rtc_device *rtc = info->rtc;
e842f1c8
RP
54 unsigned int rtsr;
55 unsigned long events = 0;
56
3888c090 57 spin_lock(&info->lock);
e842f1c8 58
90d0ae8e 59 rtsr = readl_relaxed(info->rtsr);
e842f1c8 60 /* clear interrupt sources */
90d0ae8e 61 writel_relaxed(0, info->rtsr);
7decaa55
MRJ
62 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
63 * See also the comments in sa1100_rtc_probe(). */
64 if (rtsr & (RTSR_ALE | RTSR_HZE)) {
65 /* This is the original code, before there was the if test
66 * above. This code does not clear interrupts that were not
67 * enabled. */
90d0ae8e 68 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr);
7decaa55
MRJ
69 } else {
70 /* For some reason, it is possible to enter this routine
71 * without interruptions enabled, it has been tested with
72 * several units (Bug in SA11xx chip?).
73 *
74 * This situation leads to an infinite "loop" of interrupt
75 * routine calling and as a result the processor seems to
76 * lock on its first call to open(). */
90d0ae8e 77 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
7decaa55 78 }
e842f1c8
RP
79
80 /* clear alarm interrupt if it has occurred */
81 if (rtsr & RTSR_AL)
82 rtsr &= ~RTSR_ALE;
90d0ae8e 83 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr);
e842f1c8
RP
84
85 /* update irq data & counter */
86 if (rtsr & RTSR_AL)
87 events |= RTC_AF | RTC_IRQF;
88 if (rtsr & RTSR_HZ)
89 events |= RTC_UF | RTC_IRQF;
90
a0164a57 91 rtc_update_irq(rtc, 1, events);
e842f1c8 92
3888c090 93 spin_unlock(&info->lock);
e842f1c8
RP
94
95 return IRQ_HANDLED;
96}
97
16380c15
JS
98static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
99{
90d0ae8e 100 u32 rtsr;
3888c090
HZ
101 struct sa1100_rtc *info = dev_get_drvdata(dev);
102
103 spin_lock_irq(&info->lock);
90d0ae8e 104 rtsr = readl_relaxed(info->rtsr);
16380c15 105 if (enabled)
90d0ae8e 106 rtsr |= RTSR_ALE;
16380c15 107 else
90d0ae8e
RH
108 rtsr &= ~RTSR_ALE;
109 writel_relaxed(rtsr, info->rtsr);
3888c090 110 spin_unlock_irq(&info->lock);
16380c15
JS
111 return 0;
112}
113
e842f1c8
RP
114static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
115{
90d0ae8e
RH
116 struct sa1100_rtc *info = dev_get_drvdata(dev);
117
118 rtc_time_to_tm(readl_relaxed(info->rcnr), tm);
e842f1c8
RP
119 return 0;
120}
121
122static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
123{
90d0ae8e 124 struct sa1100_rtc *info = dev_get_drvdata(dev);
e842f1c8
RP
125 unsigned long time;
126 int ret;
127
128 ret = rtc_tm_to_time(tm, &time);
129 if (ret == 0)
90d0ae8e 130 writel_relaxed(time, info->rcnr);
e842f1c8
RP
131 return ret;
132}
133
134static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
135{
a0164a57 136 u32 rtsr;
90d0ae8e 137 struct sa1100_rtc *info = dev_get_drvdata(dev);
32b49da4 138
90d0ae8e 139 rtsr = readl_relaxed(info->rtsr);
32b49da4
DB
140 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
141 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
e842f1c8
RP
142 return 0;
143}
144
145static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
146{
3888c090 147 struct sa1100_rtc *info = dev_get_drvdata(dev);
1d8c38c3 148 unsigned long time;
a0164a57 149 int ret;
e842f1c8 150
3888c090 151 spin_lock_irq(&info->lock);
1d8c38c3
HZ
152 ret = rtc_tm_to_time(&alrm->time, &time);
153 if (ret != 0)
154 goto out;
90d0ae8e
RH
155 writel_relaxed(readl_relaxed(info->rtsr) &
156 (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr);
157 writel_relaxed(time, info->rtar);
1d8c38c3 158 if (alrm->enabled)
90d0ae8e 159 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr);
1d8c38c3 160 else
90d0ae8e 161 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr);
1d8c38c3 162out:
3888c090 163 spin_unlock_irq(&info->lock);
e842f1c8 164
a0164a57 165 return ret;
e842f1c8
RP
166}
167
168static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
169{
90d0ae8e
RH
170 struct sa1100_rtc *info = dev_get_drvdata(dev);
171
172 seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr));
173 seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr));
e842f1c8
RP
174
175 return 0;
176}
177
ff8371ac 178static const struct rtc_class_ops sa1100_rtc_ops = {
e842f1c8
RP
179 .read_time = sa1100_rtc_read_time,
180 .set_time = sa1100_rtc_set_time,
181 .read_alarm = sa1100_rtc_read_alarm,
182 .set_alarm = sa1100_rtc_set_alarm,
183 .proc = sa1100_rtc_proc,
16380c15 184 .alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
e842f1c8
RP
185};
186
8c0961ba 187int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info)
e842f1c8 188{
a0164a57 189 struct rtc_device *rtc;
8c0961ba 190 int ret;
3888c090 191
8c0961ba 192 spin_lock_init(&info->lock);
3888c090 193
55d735ef 194 info->clk = devm_clk_get(&pdev->dev, NULL);
8e8bbcb3
HZ
195 if (IS_ERR(info->clk)) {
196 dev_err(&pdev->dev, "failed to find rtc clock source\n");
55d735ef 197 return PTR_ERR(info->clk);
8e8bbcb3 198 }
e842f1c8 199
0cc0c38e
CX
200 ret = clk_prepare_enable(info->clk);
201 if (ret)
66600bbe 202 return ret;
e842f1c8
RP
203 /*
204 * According to the manual we should be able to let RTTR be zero
205 * and then a default diviser for a 32.768KHz clock is used.
206 * Apparently this doesn't work, at least for my SA1110 rev 5.
207 * If the clock divider is uninitialized then reset it to the
208 * default value to get the 1Hz clock.
209 */
90d0ae8e
RH
210 if (readl_relaxed(info->rttr) == 0) {
211 writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr);
a0164a57
RK
212 dev_warn(&pdev->dev, "warning: "
213 "initializing default clock divider/trim value\n");
e842f1c8 214 /* The current RTC value probably doesn't make sense either */
90d0ae8e 215 writel_relaxed(0, info->rcnr);
e842f1c8
RP
216 }
217
55d735ef
JH
218 rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &sa1100_rtc_ops,
219 THIS_MODULE);
3888c090 220 if (IS_ERR(rtc)) {
8c0961ba
RH
221 clk_disable_unprepare(info->clk);
222 return PTR_ERR(rtc);
3888c090
HZ
223 }
224 info->rtc = rtc;
a0164a57 225
512053a4 226 rtc->max_user_freq = RTC_FREQ;
512053a4 227
7decaa55
MRJ
228 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
229 * See also the comments in sa1100_rtc_interrupt().
230 *
231 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
232 * interrupt pending, even though interrupts were never enabled.
233 * In this case, this bit it must be reset before enabling
234 * interruptions to avoid a nonexistent interrupt to occur.
235 *
236 * In principle, the same problem would apply to bit 0, although it has
237 * never been observed to happen.
238 *
239 * This issue is addressed both here and in sa1100_rtc_interrupt().
240 * If the issue is not addressed here, in the times when the processor
241 * wakes up with the bit set there will be one spurious interrupt.
242 *
243 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
244 * safe side, once the condition that lead to this strange
245 * initialization is unknown and could in principle happen during
246 * normal processing.
247 *
248 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
249 * the corresponding bits in RTSR. */
90d0ae8e 250 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
7decaa55 251
e842f1c8 252 return 0;
8c0961ba
RH
253}
254EXPORT_SYMBOL_GPL(sa1100_rtc_init);
255
256static int sa1100_rtc_probe(struct platform_device *pdev)
257{
258 struct sa1100_rtc *info;
90d0ae8e
RH
259 struct resource *iores;
260 void __iomem *base;
8c0961ba 261 int irq_1hz, irq_alarm;
512053a4 262 int ret;
8c0961ba
RH
263
264 irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
265 irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
266 if (irq_1hz < 0 || irq_alarm < 0)
267 return -ENODEV;
268
269 info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL);
270 if (!info)
271 return -ENOMEM;
272 info->irq_1hz = irq_1hz;
273 info->irq_alarm = irq_alarm;
274
512053a4
AB
275 ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0,
276 "rtc 1Hz", &pdev->dev);
277 if (ret) {
278 dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz);
279 return ret;
280 }
281 ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0,
282 "rtc Alrm", &pdev->dev);
283 if (ret) {
284 dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm);
285 return ret;
286 }
287
90d0ae8e
RH
288 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289 base = devm_ioremap_resource(&pdev->dev, iores);
290 if (IS_ERR(base))
291 return PTR_ERR(base);
292
293 if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
294 of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
295 info->rcnr = base + 0x04;
296 info->rtsr = base + 0x10;
297 info->rtar = base + 0x00;
298 info->rttr = base + 0x08;
299 } else {
300 info->rcnr = base + 0x0;
301 info->rtsr = base + 0x8;
302 info->rtar = base + 0x4;
303 info->rttr = base + 0xc;
304 }
305
8c0961ba
RH
306 platform_set_drvdata(pdev, info);
307 device_init_wakeup(&pdev->dev, 1);
308
309 return sa1100_rtc_init(pdev, info);
e842f1c8
RP
310}
311
312static int sa1100_rtc_remove(struct platform_device *pdev)
313{
3888c090 314 struct sa1100_rtc *info = platform_get_drvdata(pdev);
a0164a57 315
512053a4
AB
316 if (info) {
317 spin_lock_irq(&info->lock);
318 writel_relaxed(0, info->rtsr);
319 spin_unlock_irq(&info->lock);
0cc0c38e 320 clk_disable_unprepare(info->clk);
512053a4 321 }
e842f1c8
RP
322
323 return 0;
324}
325
aaa92fae 326#ifdef CONFIG_PM_SLEEP
5d027cd2 327static int sa1100_rtc_suspend(struct device *dev)
6bc54e69 328{
3888c090 329 struct sa1100_rtc *info = dev_get_drvdata(dev);
5d027cd2 330 if (device_may_wakeup(dev))
3888c090 331 enable_irq_wake(info->irq_alarm);
6bc54e69
RK
332 return 0;
333}
334
5d027cd2 335static int sa1100_rtc_resume(struct device *dev)
6bc54e69 336{
3888c090 337 struct sa1100_rtc *info = dev_get_drvdata(dev);
5d027cd2 338 if (device_may_wakeup(dev))
3888c090 339 disable_irq_wake(info->irq_alarm);
6bc54e69
RK
340 return 0;
341}
6bc54e69
RK
342#endif
343
aaa92fae
JH
344static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend,
345 sa1100_rtc_resume);
346
c8a6046e 347#ifdef CONFIG_OF
dee21a6f 348static const struct of_device_id sa1100_rtc_dt_ids[] = {
8bec2e9e
HZ
349 { .compatible = "mrvl,sa1100-rtc", },
350 { .compatible = "mrvl,mmp-rtc", },
351 {}
352};
353MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
c8a6046e 354#endif
8bec2e9e 355
e842f1c8
RP
356static struct platform_driver sa1100_rtc_driver = {
357 .probe = sa1100_rtc_probe,
358 .remove = sa1100_rtc_remove,
359 .driver = {
5d027cd2 360 .name = "sa1100-rtc",
5d027cd2 361 .pm = &sa1100_rtc_pm_ops,
c8a6046e 362 .of_match_table = of_match_ptr(sa1100_rtc_dt_ids),
e842f1c8
RP
363 },
364};
365
0c4eae66 366module_platform_driver(sa1100_rtc_driver);
e842f1c8
RP
367
368MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
369MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
370MODULE_LICENSE("GPL");
ad28a07b 371MODULE_ALIAS("platform:sa1100-rtc");