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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e842f1c8 RP |
2 | /* |
3 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
4 | * | |
5 | * Copyright (c) 2000 Nils Faerber | |
6 | * | |
7 | * Based on rtc.c by Paul Gortmaker | |
8 | * | |
9 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
10 | * | |
11 | * Modifications from: | |
12 | * CIH <cih@coventive.com> | |
2f82af08 | 13 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
14 | * Andrew Christian <andrew.christian@hp.com> |
15 | * | |
16 | * Converted to the RTC subsystem and Driver Model | |
17 | * by Richard Purdie <rpurdie@rpsys.net> | |
e842f1c8 RP |
18 | */ |
19 | ||
20 | #include <linux/platform_device.h> | |
21 | #include <linux/module.h> | |
8e8bbcb3 | 22 | #include <linux/clk.h> |
e842f1c8 RP |
23 | #include <linux/rtc.h> |
24 | #include <linux/init.h> | |
25 | #include <linux/fs.h> | |
26 | #include <linux/interrupt.h> | |
3888c090 | 27 | #include <linux/slab.h> |
a0164a57 | 28 | #include <linux/string.h> |
8bec2e9e | 29 | #include <linux/of.h> |
e842f1c8 | 30 | #include <linux/pm.h> |
a0164a57 | 31 | #include <linux/bitops.h> |
23019a73 | 32 | #include <linux/io.h> |
e842f1c8 | 33 | |
90d0ae8e RH |
34 | #define RTSR_HZE BIT(3) /* HZ interrupt enable */ |
35 | #define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */ | |
36 | #define RTSR_HZ BIT(1) /* HZ rising-edge detected */ | |
37 | #define RTSR_AL BIT(0) /* RTC alarm detected */ | |
a0164a57 | 38 | |
8c0961ba RH |
39 | #include "rtc-sa1100.h" |
40 | ||
a404ad1f | 41 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 | 42 | #define RTC_DEF_TRIM 0 |
3888c090 | 43 | #define RTC_FREQ 1024 |
a0164a57 | 44 | |
a0164a57 | 45 | |
7d12e780 | 46 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 | 47 | { |
3888c090 HZ |
48 | struct sa1100_rtc *info = dev_get_drvdata(dev_id); |
49 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
50 | unsigned int rtsr; |
51 | unsigned long events = 0; | |
52 | ||
3888c090 | 53 | spin_lock(&info->lock); |
e842f1c8 | 54 | |
90d0ae8e | 55 | rtsr = readl_relaxed(info->rtsr); |
e842f1c8 | 56 | /* clear interrupt sources */ |
90d0ae8e | 57 | writel_relaxed(0, info->rtsr); |
7decaa55 MRJ |
58 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
59 | * See also the comments in sa1100_rtc_probe(). */ | |
60 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
61 | /* This is the original code, before there was the if test | |
62 | * above. This code does not clear interrupts that were not | |
63 | * enabled. */ | |
90d0ae8e | 64 | writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); |
7decaa55 MRJ |
65 | } else { |
66 | /* For some reason, it is possible to enter this routine | |
67 | * without interruptions enabled, it has been tested with | |
68 | * several units (Bug in SA11xx chip?). | |
69 | * | |
70 | * This situation leads to an infinite "loop" of interrupt | |
71 | * routine calling and as a result the processor seems to | |
72 | * lock on its first call to open(). */ | |
90d0ae8e | 73 | writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); |
7decaa55 | 74 | } |
e842f1c8 RP |
75 | |
76 | /* clear alarm interrupt if it has occurred */ | |
77 | if (rtsr & RTSR_AL) | |
78 | rtsr &= ~RTSR_ALE; | |
90d0ae8e | 79 | writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); |
e842f1c8 RP |
80 | |
81 | /* update irq data & counter */ | |
82 | if (rtsr & RTSR_AL) | |
83 | events |= RTC_AF | RTC_IRQF; | |
84 | if (rtsr & RTSR_HZ) | |
85 | events |= RTC_UF | RTC_IRQF; | |
86 | ||
a0164a57 | 87 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 88 | |
3888c090 | 89 | spin_unlock(&info->lock); |
e842f1c8 RP |
90 | |
91 | return IRQ_HANDLED; | |
92 | } | |
93 | ||
16380c15 JS |
94 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
95 | { | |
90d0ae8e | 96 | u32 rtsr; |
3888c090 HZ |
97 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
98 | ||
99 | spin_lock_irq(&info->lock); | |
90d0ae8e | 100 | rtsr = readl_relaxed(info->rtsr); |
16380c15 | 101 | if (enabled) |
90d0ae8e | 102 | rtsr |= RTSR_ALE; |
16380c15 | 103 | else |
90d0ae8e RH |
104 | rtsr &= ~RTSR_ALE; |
105 | writel_relaxed(rtsr, info->rtsr); | |
3888c090 | 106 | spin_unlock_irq(&info->lock); |
16380c15 JS |
107 | return 0; |
108 | } | |
109 | ||
e842f1c8 RP |
110 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
111 | { | |
90d0ae8e RH |
112 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
113 | ||
eb8d9420 | 114 | rtc_time64_to_tm(readl_relaxed(info->rcnr), tm); |
e842f1c8 RP |
115 | return 0; |
116 | } | |
117 | ||
118 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
119 | { | |
90d0ae8e | 120 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
e842f1c8 | 121 | |
eb8d9420 AB |
122 | writel_relaxed(rtc_tm_to_time64(tm), info->rcnr); |
123 | ||
124 | return 0; | |
e842f1c8 RP |
125 | } |
126 | ||
127 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
128 | { | |
a0164a57 | 129 | u32 rtsr; |
90d0ae8e | 130 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
32b49da4 | 131 | |
90d0ae8e | 132 | rtsr = readl_relaxed(info->rtsr); |
32b49da4 DB |
133 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
134 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
135 | return 0; |
136 | } | |
137 | ||
138 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
139 | { | |
3888c090 | 140 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
e842f1c8 | 141 | |
3888c090 | 142 | spin_lock_irq(&info->lock); |
90d0ae8e RH |
143 | writel_relaxed(readl_relaxed(info->rtsr) & |
144 | (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr); | |
eb8d9420 | 145 | writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar); |
1d8c38c3 | 146 | if (alrm->enabled) |
90d0ae8e | 147 | writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); |
1d8c38c3 | 148 | else |
90d0ae8e | 149 | writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); |
3888c090 | 150 | spin_unlock_irq(&info->lock); |
e842f1c8 | 151 | |
eb8d9420 | 152 | return 0; |
e842f1c8 RP |
153 | } |
154 | ||
155 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
156 | { | |
90d0ae8e RH |
157 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
158 | ||
159 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr)); | |
160 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr)); | |
e842f1c8 RP |
161 | |
162 | return 0; | |
163 | } | |
164 | ||
ff8371ac | 165 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 RP |
166 | .read_time = sa1100_rtc_read_time, |
167 | .set_time = sa1100_rtc_set_time, | |
168 | .read_alarm = sa1100_rtc_read_alarm, | |
169 | .set_alarm = sa1100_rtc_set_alarm, | |
170 | .proc = sa1100_rtc_proc, | |
16380c15 | 171 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
172 | }; |
173 | ||
8c0961ba | 174 | int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info) |
e842f1c8 | 175 | { |
8c0961ba | 176 | int ret; |
3888c090 | 177 | |
8c0961ba | 178 | spin_lock_init(&info->lock); |
3888c090 | 179 | |
55d735ef | 180 | info->clk = devm_clk_get(&pdev->dev, NULL); |
8e8bbcb3 HZ |
181 | if (IS_ERR(info->clk)) { |
182 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
55d735ef | 183 | return PTR_ERR(info->clk); |
8e8bbcb3 | 184 | } |
e842f1c8 | 185 | |
0cc0c38e CX |
186 | ret = clk_prepare_enable(info->clk); |
187 | if (ret) | |
66600bbe | 188 | return ret; |
e842f1c8 RP |
189 | /* |
190 | * According to the manual we should be able to let RTTR be zero | |
191 | * and then a default diviser for a 32.768KHz clock is used. | |
192 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
193 | * If the clock divider is uninitialized then reset it to the | |
194 | * default value to get the 1Hz clock. | |
195 | */ | |
90d0ae8e RH |
196 | if (readl_relaxed(info->rttr) == 0) { |
197 | writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr); | |
a0164a57 RK |
198 | dev_warn(&pdev->dev, "warning: " |
199 | "initializing default clock divider/trim value\n"); | |
e842f1c8 | 200 | /* The current RTC value probably doesn't make sense either */ |
90d0ae8e | 201 | writel_relaxed(0, info->rcnr); |
e842f1c8 RP |
202 | } |
203 | ||
f2997775 AB |
204 | info->rtc->ops = &sa1100_rtc_ops; |
205 | info->rtc->max_user_freq = RTC_FREQ; | |
e877ab73 | 206 | info->rtc->range_max = U32_MAX; |
f2997775 | 207 | |
fdcfd854 | 208 | ret = devm_rtc_register_device(info->rtc); |
f2997775 | 209 | if (ret) { |
8c0961ba | 210 | clk_disable_unprepare(info->clk); |
f2997775 | 211 | return ret; |
3888c090 | 212 | } |
512053a4 | 213 | |
7decaa55 MRJ |
214 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
215 | * See also the comments in sa1100_rtc_interrupt(). | |
216 | * | |
217 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
218 | * interrupt pending, even though interrupts were never enabled. | |
219 | * In this case, this bit it must be reset before enabling | |
220 | * interruptions to avoid a nonexistent interrupt to occur. | |
221 | * | |
222 | * In principle, the same problem would apply to bit 0, although it has | |
223 | * never been observed to happen. | |
224 | * | |
225 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
226 | * If the issue is not addressed here, in the times when the processor | |
227 | * wakes up with the bit set there will be one spurious interrupt. | |
228 | * | |
229 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
230 | * safe side, once the condition that lead to this strange | |
231 | * initialization is unknown and could in principle happen during | |
232 | * normal processing. | |
233 | * | |
234 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
235 | * the corresponding bits in RTSR. */ | |
90d0ae8e | 236 | writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); |
7decaa55 | 237 | |
e842f1c8 | 238 | return 0; |
8c0961ba RH |
239 | } |
240 | EXPORT_SYMBOL_GPL(sa1100_rtc_init); | |
241 | ||
242 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
243 | { | |
244 | struct sa1100_rtc *info; | |
90d0ae8e | 245 | void __iomem *base; |
8c0961ba | 246 | int irq_1hz, irq_alarm; |
512053a4 | 247 | int ret; |
8c0961ba RH |
248 | |
249 | irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz"); | |
250 | irq_alarm = platform_get_irq_byname(pdev, "rtc alarm"); | |
251 | if (irq_1hz < 0 || irq_alarm < 0) | |
252 | return -ENODEV; | |
253 | ||
254 | info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL); | |
255 | if (!info) | |
256 | return -ENOMEM; | |
257 | info->irq_1hz = irq_1hz; | |
258 | info->irq_alarm = irq_alarm; | |
259 | ||
f2997775 AB |
260 | info->rtc = devm_rtc_allocate_device(&pdev->dev); |
261 | if (IS_ERR(info->rtc)) | |
262 | return PTR_ERR(info->rtc); | |
263 | ||
512053a4 AB |
264 | ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0, |
265 | "rtc 1Hz", &pdev->dev); | |
266 | if (ret) { | |
267 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz); | |
268 | return ret; | |
269 | } | |
270 | ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0, | |
271 | "rtc Alrm", &pdev->dev); | |
272 | if (ret) { | |
273 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm); | |
274 | return ret; | |
275 | } | |
276 | ||
09ef18bc | 277 | base = devm_platform_ioremap_resource(pdev, 0); |
90d0ae8e RH |
278 | if (IS_ERR(base)) |
279 | return PTR_ERR(base); | |
280 | ||
281 | if (IS_ENABLED(CONFIG_ARCH_SA1100) || | |
282 | of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) { | |
283 | info->rcnr = base + 0x04; | |
284 | info->rtsr = base + 0x10; | |
285 | info->rtar = base + 0x00; | |
286 | info->rttr = base + 0x08; | |
287 | } else { | |
288 | info->rcnr = base + 0x0; | |
289 | info->rtsr = base + 0x8; | |
290 | info->rtar = base + 0x4; | |
291 | info->rttr = base + 0xc; | |
292 | } | |
293 | ||
8c0961ba RH |
294 | platform_set_drvdata(pdev, info); |
295 | device_init_wakeup(&pdev->dev, 1); | |
296 | ||
297 | return sa1100_rtc_init(pdev, info); | |
e842f1c8 RP |
298 | } |
299 | ||
cf407e9f | 300 | static void sa1100_rtc_remove(struct platform_device *pdev) |
e842f1c8 | 301 | { |
3888c090 | 302 | struct sa1100_rtc *info = platform_get_drvdata(pdev); |
a0164a57 | 303 | |
512053a4 AB |
304 | if (info) { |
305 | spin_lock_irq(&info->lock); | |
306 | writel_relaxed(0, info->rtsr); | |
307 | spin_unlock_irq(&info->lock); | |
0cc0c38e | 308 | clk_disable_unprepare(info->clk); |
512053a4 | 309 | } |
e842f1c8 RP |
310 | } |
311 | ||
aaa92fae | 312 | #ifdef CONFIG_PM_SLEEP |
5d027cd2 | 313 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 314 | { |
3888c090 | 315 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 316 | if (device_may_wakeup(dev)) |
3888c090 | 317 | enable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
318 | return 0; |
319 | } | |
320 | ||
5d027cd2 | 321 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 322 | { |
3888c090 | 323 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 324 | if (device_may_wakeup(dev)) |
3888c090 | 325 | disable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
326 | return 0; |
327 | } | |
6bc54e69 RK |
328 | #endif |
329 | ||
aaa92fae JH |
330 | static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend, |
331 | sa1100_rtc_resume); | |
332 | ||
c8a6046e | 333 | #ifdef CONFIG_OF |
dee21a6f | 334 | static const struct of_device_id sa1100_rtc_dt_ids[] = { |
8bec2e9e HZ |
335 | { .compatible = "mrvl,sa1100-rtc", }, |
336 | { .compatible = "mrvl,mmp-rtc", }, | |
337 | {} | |
338 | }; | |
339 | MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids); | |
c8a6046e | 340 | #endif |
8bec2e9e | 341 | |
e842f1c8 RP |
342 | static struct platform_driver sa1100_rtc_driver = { |
343 | .probe = sa1100_rtc_probe, | |
cf407e9f | 344 | .remove_new = sa1100_rtc_remove, |
e842f1c8 | 345 | .driver = { |
5d027cd2 | 346 | .name = "sa1100-rtc", |
5d027cd2 | 347 | .pm = &sa1100_rtc_pm_ops, |
c8a6046e | 348 | .of_match_table = of_match_ptr(sa1100_rtc_dt_ids), |
e842f1c8 RP |
349 | }, |
350 | }; | |
351 | ||
0c4eae66 | 352 | module_platform_driver(sa1100_rtc_driver); |
e842f1c8 RP |
353 | |
354 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
355 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
356 | MODULE_LICENSE("GPL"); | |
ad28a07b | 357 | MODULE_ALIAS("platform:sa1100-rtc"); |