Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1add6781 | 2 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
3 | * |
4 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com/ | |
1add6781 BD |
6 | * |
7 | * Copyright (c) 2004,2006 Simtec Electronics | |
8 | * Ben Dooks, <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
1add6781 BD |
11 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/fs.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/bcd.h> | |
22 | #include <linux/clk.h> | |
9974b6ea | 23 | #include <linux/log2.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
39ce4084 | 25 | #include <linux/of.h> |
64704c92 | 26 | #include <linux/of_device.h> |
dbd9acbe SK |
27 | #include <linux/uaccess.h> |
28 | #include <linux/io.h> | |
1add6781 | 29 | |
1add6781 | 30 | #include <asm/irq.h> |
b9d7c5d3 | 31 | #include "rtc-s3c.h" |
1add6781 | 32 | |
19be09f5 CC |
33 | struct s3c_rtc { |
34 | struct device *dev; | |
35 | struct rtc_device *rtc; | |
36 | ||
37 | void __iomem *base; | |
38 | struct clk *rtc_clk; | |
df9e26d0 | 39 | struct clk *rtc_src_clk; |
5a5b614b | 40 | bool alarm_enabled; |
19be09f5 | 41 | |
6b72086d | 42 | const struct s3c_rtc_data *data; |
1add6781 | 43 | |
19be09f5 CC |
44 | int irq_alarm; |
45 | int irq_tick; | |
1add6781 | 46 | |
19be09f5 | 47 | spinlock_t pie_lock; |
5a5b614b | 48 | spinlock_t alarm_lock; |
1add6781 | 49 | |
fc1afe60 KK |
50 | int ticnt_save; |
51 | int ticnt_en_save; | |
19be09f5 CC |
52 | bool wake_en; |
53 | }; | |
54 | ||
ae05c950 CC |
55 | struct s3c_rtc_data { |
56 | int max_user_freq; | |
df9e26d0 | 57 | bool needs_src_clk; |
ae05c950 CC |
58 | |
59 | void (*irq_handler) (struct s3c_rtc *info, int mask); | |
60 | void (*set_freq) (struct s3c_rtc *info, int freq); | |
61 | void (*enable_tick) (struct s3c_rtc *info, struct seq_file *seq); | |
62 | void (*select_tick_clk) (struct s3c_rtc *info); | |
63 | void (*save_tick_cnt) (struct s3c_rtc *info); | |
64 | void (*restore_tick_cnt) (struct s3c_rtc *info); | |
65 | void (*enable) (struct s3c_rtc *info); | |
66 | void (*disable) (struct s3c_rtc *info); | |
67 | }; | |
68 | ||
498bcf31 | 69 | static int s3c_rtc_enable_clk(struct s3c_rtc *info) |
88cee8fd | 70 | { |
5a5b614b | 71 | int ret; |
88cee8fd | 72 | |
5a5b614b MS |
73 | ret = clk_enable(info->rtc_clk); |
74 | if (ret) | |
75 | return ret; | |
498bcf31 | 76 | |
5a5b614b MS |
77 | if (info->data->needs_src_clk) { |
78 | ret = clk_enable(info->rtc_src_clk); | |
79 | if (ret) { | |
80 | clk_disable(info->rtc_clk); | |
81 | return ret; | |
498bcf31 | 82 | } |
1fb1c35f | 83 | } |
5a5b614b | 84 | return 0; |
24e14554 CC |
85 | } |
86 | ||
87 | static void s3c_rtc_disable_clk(struct s3c_rtc *info) | |
88 | { | |
5a5b614b MS |
89 | if (info->data->needs_src_clk) |
90 | clk_disable(info->rtc_src_clk); | |
91 | clk_disable(info->rtc_clk); | |
88cee8fd DK |
92 | } |
93 | ||
1add6781 | 94 | /* IRQ Handlers */ |
ae05c950 | 95 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 | 96 | { |
19be09f5 | 97 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 98 | |
ae05c950 CC |
99 | if (info->data->irq_handler) |
100 | info->data->irq_handler(info, S3C2410_INTP_TIC); | |
88cee8fd | 101 | |
1add6781 BD |
102 | return IRQ_HANDLED; |
103 | } | |
104 | ||
ae05c950 | 105 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 | 106 | { |
19be09f5 | 107 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 108 | |
ae05c950 CC |
109 | if (info->data->irq_handler) |
110 | info->data->irq_handler(info, S3C2410_INTP_ALM); | |
2f3478f6 | 111 | |
1add6781 BD |
112 | return IRQ_HANDLED; |
113 | } | |
114 | ||
115 | /* Update control registers */ | |
2ec38a03 | 116 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 | 117 | { |
19be09f5 | 118 | struct s3c_rtc *info = dev_get_drvdata(dev); |
5a5b614b | 119 | unsigned long flags; |
1add6781 | 120 | unsigned int tmp; |
498bcf31 | 121 | int ret; |
1add6781 | 122 | |
19be09f5 | 123 | dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled); |
1add6781 | 124 | |
498bcf31 KK |
125 | ret = s3c_rtc_enable_clk(info); |
126 | if (ret) | |
127 | return ret; | |
24e14554 | 128 | |
19be09f5 | 129 | tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 130 | |
2ec38a03 | 131 | if (enabled) |
1add6781 BD |
132 | tmp |= S3C2410_RTCALM_ALMEN; |
133 | ||
19be09f5 | 134 | writeb(tmp, info->base + S3C2410_RTCALM); |
2ec38a03 | 135 | |
5a5b614b | 136 | spin_lock_irqsave(&info->alarm_lock, flags); |
88cee8fd | 137 | |
5a5b614b | 138 | if (info->alarm_enabled && !enabled) |
1fb1c35f | 139 | s3c_rtc_disable_clk(info); |
5a5b614b MS |
140 | else if (!info->alarm_enabled && enabled) |
141 | ret = s3c_rtc_enable_clk(info); | |
1fb1c35f | 142 | |
5a5b614b MS |
143 | info->alarm_enabled = enabled; |
144 | spin_unlock_irqrestore(&info->alarm_lock, flags); | |
145 | ||
146 | s3c_rtc_disable_clk(info); | |
147 | ||
148 | return ret; | |
1add6781 BD |
149 | } |
150 | ||
ae05c950 | 151 | /* Set RTC frequency */ |
19be09f5 | 152 | static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq) |
1add6781 | 153 | { |
498bcf31 KK |
154 | int ret; |
155 | ||
5d2a5037 JC |
156 | if (!is_power_of_2(freq)) |
157 | return -EINVAL; | |
158 | ||
498bcf31 KK |
159 | ret = s3c_rtc_enable_clk(info); |
160 | if (ret) | |
161 | return ret; | |
19be09f5 | 162 | spin_lock_irq(&info->pie_lock); |
1add6781 | 163 | |
ae05c950 CC |
164 | if (info->data->set_freq) |
165 | info->data->set_freq(info, freq); | |
25c1a246 | 166 | |
19be09f5 | 167 | spin_unlock_irq(&info->pie_lock); |
70c96dfa | 168 | s3c_rtc_disable_clk(info); |
773be7ee BD |
169 | |
170 | return 0; | |
1add6781 BD |
171 | } |
172 | ||
173 | /* Time read/write */ | |
1add6781 BD |
174 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) |
175 | { | |
19be09f5 | 176 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 | 177 | unsigned int have_retried = 0; |
498bcf31 | 178 | int ret; |
1add6781 | 179 | |
498bcf31 KK |
180 | ret = s3c_rtc_enable_clk(info); |
181 | if (ret) | |
182 | return ret; | |
df9e26d0 | 183 | |
fc1afe60 | 184 | retry_get_time: |
19be09f5 CC |
185 | rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN); |
186 | rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR); | |
187 | rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE); | |
188 | rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON); | |
189 | rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR); | |
190 | rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC); | |
1add6781 | 191 | |
48fc7f7e | 192 | /* the only way to work out whether the system was mid-update |
1add6781 BD |
193 | * when we read it is to check the second counter, and if it |
194 | * is zero, then we re-try the entire read | |
195 | */ | |
196 | ||
197 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
198 | have_retried = 1; | |
199 | goto retry_get_time; | |
200 | } | |
201 | ||
fe20ba70 AB |
202 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
203 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
204 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
205 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
206 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
207 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 | 208 | |
24e14554 CC |
209 | s3c_rtc_disable_clk(info); |
210 | ||
1add6781 BD |
211 | rtc_tm->tm_year += 100; |
212 | rtc_tm->tm_mon -= 1; | |
213 | ||
9a1bacf4 | 214 | dev_dbg(dev, "read time %ptR\n", rtc_tm); |
22652ba7 | 215 | return 0; |
1add6781 BD |
216 | } |
217 | ||
218 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
219 | { | |
19be09f5 | 220 | struct s3c_rtc *info = dev_get_drvdata(dev); |
641741e0 | 221 | int year = tm->tm_year - 100; |
498bcf31 | 222 | int ret; |
9a654518 | 223 | |
9a1bacf4 | 224 | dev_dbg(dev, "set time %ptR\n", tm); |
641741e0 BD |
225 | |
226 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 227 | |
641741e0 | 228 | if (year < 0 || year >= 100) { |
9a654518 | 229 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 230 | return -EINVAL; |
9a654518 BD |
231 | } |
232 | ||
498bcf31 KK |
233 | ret = s3c_rtc_enable_clk(info); |
234 | if (ret) | |
235 | return ret; | |
19be09f5 CC |
236 | |
237 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC); | |
238 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN); | |
239 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR); | |
240 | writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE); | |
241 | writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON); | |
242 | writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR); | |
243 | ||
24e14554 | 244 | s3c_rtc_disable_clk(info); |
1add6781 BD |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
249 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
250 | { | |
19be09f5 | 251 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
252 | struct rtc_time *alm_tm = &alrm->time; |
253 | unsigned int alm_en; | |
498bcf31 | 254 | int ret; |
1add6781 | 255 | |
498bcf31 KK |
256 | ret = s3c_rtc_enable_clk(info); |
257 | if (ret) | |
258 | return ret; | |
df9e26d0 | 259 | |
19be09f5 CC |
260 | alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC); |
261 | alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN); | |
262 | alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR); | |
263 | alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON); | |
264 | alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE); | |
265 | alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR); | |
1add6781 | 266 | |
19be09f5 | 267 | alm_en = readb(info->base + S3C2410_RTCALM); |
1add6781 | 268 | |
24e14554 CC |
269 | s3c_rtc_disable_clk(info); |
270 | ||
a2db8dfc DB |
271 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
272 | ||
9a1bacf4 | 273 | dev_dbg(dev, "read alarm %d, %ptR\n", alm_en, alm_tm); |
1add6781 | 274 | |
1add6781 | 275 | /* decode the alarm enable field */ |
1add6781 | 276 | if (alm_en & S3C2410_RTCALM_SECEN) |
fe20ba70 | 277 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 BD |
278 | |
279 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 280 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 BD |
281 | |
282 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 283 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 BD |
284 | |
285 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 286 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 BD |
287 | |
288 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 289 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 | 290 | alm_tm->tm_mon -= 1; |
1add6781 BD |
291 | } |
292 | ||
293 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 294 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 BD |
295 | |
296 | return 0; | |
297 | } | |
298 | ||
299 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
300 | { | |
19be09f5 | 301 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
302 | struct rtc_time *tm = &alrm->time; |
303 | unsigned int alrm_en; | |
498bcf31 | 304 | int ret; |
1add6781 | 305 | |
9a1bacf4 | 306 | dev_dbg(dev, "s3c_rtc_setalarm: %d, %ptR\n", alrm->enabled, tm); |
1add6781 | 307 | |
498bcf31 KK |
308 | ret = s3c_rtc_enable_clk(info); |
309 | if (ret) | |
310 | return ret; | |
24e14554 | 311 | |
19be09f5 CC |
312 | alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
313 | writeb(0x00, info->base + S3C2410_RTCALM); | |
1add6781 BD |
314 | |
315 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
316 | alrm_en |= S3C2410_RTCALM_SECEN; | |
19be09f5 | 317 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC); |
1add6781 BD |
318 | } |
319 | ||
320 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
321 | alrm_en |= S3C2410_RTCALM_MINEN; | |
19be09f5 | 322 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN); |
1add6781 BD |
323 | } |
324 | ||
325 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
326 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
19be09f5 | 327 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR); |
1add6781 BD |
328 | } |
329 | ||
fb4ac3c1 KK |
330 | if (tm->tm_mon < 12 && tm->tm_mon >= 0) { |
331 | alrm_en |= S3C2410_RTCALM_MONEN; | |
332 | writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_ALMMON); | |
333 | } | |
334 | ||
335 | if (tm->tm_mday <= 31 && tm->tm_mday >= 1) { | |
336 | alrm_en |= S3C2410_RTCALM_DAYEN; | |
337 | writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_ALMDATE); | |
338 | } | |
339 | ||
d4a48c2a | 340 | dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en); |
1add6781 | 341 | |
19be09f5 | 342 | writeb(alrm_en, info->base + S3C2410_RTCALM); |
1add6781 | 343 | |
24e14554 | 344 | s3c_rtc_setaie(dev, alrm->enabled); |
19be09f5 | 345 | |
5a5b614b MS |
346 | s3c_rtc_disable_clk(info); |
347 | ||
1add6781 BD |
348 | return 0; |
349 | } | |
350 | ||
1add6781 BD |
351 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
352 | { | |
19be09f5 | 353 | struct s3c_rtc *info = dev_get_drvdata(dev); |
498bcf31 | 354 | int ret; |
1add6781 | 355 | |
498bcf31 KK |
356 | ret = s3c_rtc_enable_clk(info); |
357 | if (ret) | |
358 | return ret; | |
9f4123b7 | 359 | |
ae05c950 CC |
360 | if (info->data->enable_tick) |
361 | info->data->enable_tick(info, seq); | |
362 | ||
24e14554 | 363 | s3c_rtc_disable_clk(info); |
ae05c950 | 364 | |
1add6781 BD |
365 | return 0; |
366 | } | |
367 | ||
ff8371ac | 368 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
369 | .read_time = s3c_rtc_gettime, |
370 | .set_time = s3c_rtc_settime, | |
371 | .read_alarm = s3c_rtc_getalarm, | |
372 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
373 | .proc = s3c_rtc_proc, |
374 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
375 | }; |
376 | ||
ae05c950 | 377 | static void s3c24xx_rtc_enable(struct s3c_rtc *info) |
1add6781 | 378 | { |
d67288da | 379 | unsigned int con, tmp; |
1add6781 | 380 | |
d67288da | 381 | con = readw(info->base + S3C2410_RTCCON); |
ae05c950 CC |
382 | /* re-enable the device, and check it is ok */ |
383 | if ((con & S3C2410_RTCCON_RTCEN) == 0) { | |
384 | dev_info(info->dev, "rtc disabled, re-enabling\n"); | |
1add6781 | 385 | |
ae05c950 | 386 | tmp = readw(info->base + S3C2410_RTCCON); |
fc1afe60 | 387 | writew(tmp | S3C2410_RTCCON_RTCEN, info->base + S3C2410_RTCCON); |
ae05c950 | 388 | } |
1add6781 | 389 | |
ae05c950 CC |
390 | if (con & S3C2410_RTCCON_CNTSEL) { |
391 | dev_info(info->dev, "removing RTCCON_CNTSEL\n"); | |
1add6781 | 392 | |
ae05c950 CC |
393 | tmp = readw(info->base + S3C2410_RTCCON); |
394 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
fc1afe60 | 395 | info->base + S3C2410_RTCCON); |
ae05c950 | 396 | } |
1add6781 | 397 | |
ae05c950 CC |
398 | if (con & S3C2410_RTCCON_CLKRST) { |
399 | dev_info(info->dev, "removing RTCCON_CLKRST\n"); | |
1add6781 | 400 | |
ae05c950 CC |
401 | tmp = readw(info->base + S3C2410_RTCCON); |
402 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
fc1afe60 | 403 | info->base + S3C2410_RTCCON); |
1add6781 | 404 | } |
ae05c950 CC |
405 | } |
406 | ||
407 | static void s3c24xx_rtc_disable(struct s3c_rtc *info) | |
408 | { | |
409 | unsigned int con; | |
410 | ||
ae05c950 CC |
411 | con = readw(info->base + S3C2410_RTCCON); |
412 | con &= ~S3C2410_RTCCON_RTCEN; | |
413 | writew(con, info->base + S3C2410_RTCCON); | |
414 | ||
415 | con = readb(info->base + S3C2410_TICNT); | |
416 | con &= ~S3C2410_TICNT_ENABLE; | |
417 | writeb(con, info->base + S3C2410_TICNT); | |
ae05c950 CC |
418 | } |
419 | ||
420 | static void s3c6410_rtc_disable(struct s3c_rtc *info) | |
421 | { | |
422 | unsigned int con; | |
423 | ||
ae05c950 CC |
424 | con = readw(info->base + S3C2410_RTCCON); |
425 | con &= ~S3C64XX_RTCCON_TICEN; | |
426 | con &= ~S3C2410_RTCCON_RTCEN; | |
427 | writew(con, info->base + S3C2410_RTCCON); | |
1add6781 BD |
428 | } |
429 | ||
19be09f5 | 430 | static int s3c_rtc_remove(struct platform_device *pdev) |
1add6781 | 431 | { |
19be09f5 CC |
432 | struct s3c_rtc *info = platform_get_drvdata(pdev); |
433 | ||
434 | s3c_rtc_setaie(info->dev, 0); | |
1add6781 | 435 | |
7f23a936 JS |
436 | if (info->data->needs_src_clk) |
437 | clk_unprepare(info->rtc_src_clk); | |
19be09f5 | 438 | clk_unprepare(info->rtc_clk); |
e48add8c | 439 | |
1add6781 BD |
440 | return 0; |
441 | } | |
442 | ||
5a167f45 | 443 | static int s3c_rtc_probe(struct platform_device *pdev) |
1add6781 | 444 | { |
19be09f5 | 445 | struct s3c_rtc *info = NULL; |
e1df962e | 446 | struct rtc_time rtc_tm; |
1add6781 BD |
447 | struct resource *res; |
448 | int ret; | |
449 | ||
19be09f5 CC |
450 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
451 | if (!info) | |
452 | return -ENOMEM; | |
1add6781 BD |
453 | |
454 | /* find the IRQs */ | |
19be09f5 CC |
455 | info->irq_tick = platform_get_irq(pdev, 1); |
456 | if (info->irq_tick < 0) { | |
1add6781 | 457 | dev_err(&pdev->dev, "no irq for rtc tick\n"); |
19be09f5 | 458 | return info->irq_tick; |
1add6781 BD |
459 | } |
460 | ||
19be09f5 | 461 | info->dev = &pdev->dev; |
64704c92 | 462 | info->data = of_device_get_match_data(&pdev->dev); |
ae05c950 CC |
463 | if (!info->data) { |
464 | dev_err(&pdev->dev, "failed getting s3c_rtc_data\n"); | |
465 | return -EINVAL; | |
466 | } | |
19be09f5 | 467 | spin_lock_init(&info->pie_lock); |
5a5b614b | 468 | spin_lock_init(&info->alarm_lock); |
19be09f5 CC |
469 | |
470 | platform_set_drvdata(pdev, info); | |
471 | ||
472 | info->irq_alarm = platform_get_irq(pdev, 0); | |
473 | if (info->irq_alarm < 0) { | |
1add6781 | 474 | dev_err(&pdev->dev, "no irq for alarm\n"); |
19be09f5 | 475 | return info->irq_alarm; |
1add6781 BD |
476 | } |
477 | ||
d4a48c2a | 478 | dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", |
fc1afe60 | 479 | info->irq_tick, info->irq_alarm); |
1add6781 BD |
480 | |
481 | /* get the memory region */ | |
1add6781 | 482 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
19be09f5 CC |
483 | info->base = devm_ioremap_resource(&pdev->dev, res); |
484 | if (IS_ERR(info->base)) | |
485 | return PTR_ERR(info->base); | |
1add6781 | 486 | |
19be09f5 CC |
487 | info->rtc_clk = devm_clk_get(&pdev->dev, "rtc"); |
488 | if (IS_ERR(info->rtc_clk)) { | |
ae6e00b4 JMC |
489 | ret = PTR_ERR(info->rtc_clk); |
490 | if (ret != -EPROBE_DEFER) | |
491 | dev_err(&pdev->dev, "failed to find rtc clock\n"); | |
492 | else | |
493 | dev_dbg(&pdev->dev, "probe deferred due to missing rtc clk\n"); | |
494 | return ret; | |
e48add8c | 495 | } |
9903f68a KK |
496 | ret = clk_prepare_enable(info->rtc_clk); |
497 | if (ret) | |
498 | return ret; | |
e48add8c | 499 | |
eaf3a659 MS |
500 | if (info->data->needs_src_clk) { |
501 | info->rtc_src_clk = devm_clk_get(&pdev->dev, "rtc_src"); | |
502 | if (IS_ERR(info->rtc_src_clk)) { | |
ae6e00b4 JMC |
503 | ret = PTR_ERR(info->rtc_src_clk); |
504 | if (ret != -EPROBE_DEFER) | |
505 | dev_err(&pdev->dev, | |
506 | "failed to find rtc source clock\n"); | |
507 | else | |
508 | dev_dbg(&pdev->dev, | |
509 | "probe deferred due to missing rtc src clk\n"); | |
8768e7b3 | 510 | goto err_src_clk; |
eaf3a659 | 511 | } |
9903f68a KK |
512 | ret = clk_prepare_enable(info->rtc_src_clk); |
513 | if (ret) | |
514 | goto err_src_clk; | |
df9e26d0 | 515 | } |
df9e26d0 | 516 | |
1add6781 | 517 | /* check to see if everything is setup correctly */ |
ae05c950 CC |
518 | if (info->data->enable) |
519 | info->data->enable(info); | |
1add6781 | 520 | |
d4a48c2a | 521 | dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", |
fc1afe60 | 522 | readw(info->base + S3C2410_RTCCON)); |
1add6781 | 523 | |
51b7616e YK |
524 | device_init_wakeup(&pdev->dev, 1); |
525 | ||
202fe4c2 | 526 | /* Check RTC Time */ |
492da68c | 527 | if (s3c_rtc_gettime(&pdev->dev, &rtc_tm)) { |
202fe4c2 KK |
528 | rtc_tm.tm_year = 100; |
529 | rtc_tm.tm_mon = 0; | |
530 | rtc_tm.tm_mday = 1; | |
531 | rtc_tm.tm_hour = 0; | |
532 | rtc_tm.tm_min = 0; | |
533 | rtc_tm.tm_sec = 0; | |
534 | ||
535 | s3c_rtc_settime(&pdev->dev, &rtc_tm); | |
536 | ||
537 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
538 | } | |
539 | ||
1add6781 | 540 | /* register RTC and exit */ |
19be09f5 | 541 | info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, |
fc1afe60 | 542 | THIS_MODULE); |
19be09f5 | 543 | if (IS_ERR(info->rtc)) { |
1add6781 | 544 | dev_err(&pdev->dev, "cannot attach rtc\n"); |
19be09f5 | 545 | ret = PTR_ERR(info->rtc); |
1add6781 BD |
546 | goto err_nortc; |
547 | } | |
548 | ||
19be09f5 | 549 | ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq, |
fc1afe60 | 550 | 0, "s3c2410-rtc alarm", info); |
19be09f5 CC |
551 | if (ret) { |
552 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret); | |
553 | goto err_nortc; | |
554 | } | |
eaa6e4dd | 555 | |
19be09f5 | 556 | ret = devm_request_irq(&pdev->dev, info->irq_tick, s3c_rtc_tickirq, |
fc1afe60 | 557 | 0, "s3c2410-rtc tick", info); |
19be09f5 CC |
558 | if (ret) { |
559 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_tick, ret); | |
560 | goto err_nortc; | |
561 | } | |
051fe54e | 562 | |
ae05c950 CC |
563 | if (info->data->select_tick_clk) |
564 | info->data->select_tick_clk(info); | |
62d17601 | 565 | |
19be09f5 | 566 | s3c_rtc_setfreq(info, 1); |
62d17601 | 567 | |
5a5b614b MS |
568 | s3c_rtc_disable_clk(info); |
569 | ||
1add6781 BD |
570 | return 0; |
571 | ||
fc1afe60 | 572 | err_nortc: |
ae05c950 CC |
573 | if (info->data->disable) |
574 | info->data->disable(info); | |
24e14554 CC |
575 | |
576 | if (info->data->needs_src_clk) | |
577 | clk_disable_unprepare(info->rtc_src_clk); | |
8768e7b3 | 578 | err_src_clk: |
19be09f5 | 579 | clk_disable_unprepare(info->rtc_clk); |
1add6781 | 580 | |
1add6781 BD |
581 | return ret; |
582 | } | |
583 | ||
32e445aa | 584 | #ifdef CONFIG_PM_SLEEP |
1add6781 | 585 | |
32e445aa | 586 | static int s3c_rtc_suspend(struct device *dev) |
1add6781 | 587 | { |
19be09f5 | 588 | struct s3c_rtc *info = dev_get_drvdata(dev); |
498bcf31 | 589 | int ret; |
32e445aa | 590 | |
498bcf31 KK |
591 | ret = s3c_rtc_enable_clk(info); |
592 | if (ret) | |
593 | return ret; | |
ae05c950 | 594 | |
1add6781 | 595 | /* save TICNT for anyone using periodic interrupts */ |
ae05c950 CC |
596 | if (info->data->save_tick_cnt) |
597 | info->data->save_tick_cnt(info); | |
598 | ||
599 | if (info->data->disable) | |
600 | info->data->disable(info); | |
f501ed52 | 601 | |
19be09f5 CC |
602 | if (device_may_wakeup(dev) && !info->wake_en) { |
603 | if (enable_irq_wake(info->irq_alarm) == 0) | |
604 | info->wake_en = true; | |
52cd4e5c | 605 | else |
32e445aa | 606 | dev_err(dev, "enable_irq_wake failed\n"); |
52cd4e5c | 607 | } |
ae05c950 | 608 | |
1add6781 BD |
609 | return 0; |
610 | } | |
611 | ||
32e445aa | 612 | static int s3c_rtc_resume(struct device *dev) |
1add6781 | 613 | { |
19be09f5 | 614 | struct s3c_rtc *info = dev_get_drvdata(dev); |
9f4123b7 | 615 | |
ae05c950 CC |
616 | if (info->data->enable) |
617 | info->data->enable(info); | |
618 | ||
619 | if (info->data->restore_tick_cnt) | |
620 | info->data->restore_tick_cnt(info); | |
f501ed52 | 621 | |
24e14554 CC |
622 | s3c_rtc_disable_clk(info); |
623 | ||
19be09f5 CC |
624 | if (device_may_wakeup(dev) && info->wake_en) { |
625 | disable_irq_wake(info->irq_alarm); | |
626 | info->wake_en = false; | |
52cd4e5c | 627 | } |
ae05c950 | 628 | |
1add6781 BD |
629 | return 0; |
630 | } | |
1add6781 | 631 | #endif |
32e445aa JH |
632 | static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume); |
633 | ||
ae05c950 CC |
634 | static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask) |
635 | { | |
ae05c950 | 636 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
ae05c950 CC |
637 | } |
638 | ||
639 | static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask) | |
640 | { | |
ae05c950 CC |
641 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
642 | writeb(mask, info->base + S3C2410_INTP); | |
ae05c950 CC |
643 | } |
644 | ||
645 | static void s3c2410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
646 | { | |
647 | unsigned int tmp = 0; | |
648 | int val; | |
649 | ||
650 | tmp = readb(info->base + S3C2410_TICNT); | |
651 | tmp &= S3C2410_TICNT_ENABLE; | |
652 | ||
653 | val = (info->rtc->max_user_freq / freq) - 1; | |
654 | tmp |= val; | |
655 | ||
656 | writel(tmp, info->base + S3C2410_TICNT); | |
657 | } | |
658 | ||
659 | static void s3c2416_rtc_setfreq(struct s3c_rtc *info, int freq) | |
660 | { | |
661 | unsigned int tmp = 0; | |
662 | int val; | |
663 | ||
664 | tmp = readb(info->base + S3C2410_TICNT); | |
665 | tmp &= S3C2410_TICNT_ENABLE; | |
666 | ||
667 | val = (info->rtc->max_user_freq / freq) - 1; | |
668 | ||
669 | tmp |= S3C2443_TICNT_PART(val); | |
670 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
671 | ||
672 | writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2); | |
673 | ||
674 | writel(tmp, info->base + S3C2410_TICNT); | |
675 | } | |
676 | ||
677 | static void s3c2443_rtc_setfreq(struct s3c_rtc *info, int freq) | |
678 | { | |
679 | unsigned int tmp = 0; | |
680 | int val; | |
681 | ||
682 | tmp = readb(info->base + S3C2410_TICNT); | |
683 | tmp &= S3C2410_TICNT_ENABLE; | |
684 | ||
685 | val = (info->rtc->max_user_freq / freq) - 1; | |
686 | ||
687 | tmp |= S3C2443_TICNT_PART(val); | |
688 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
689 | ||
690 | writel(tmp, info->base + S3C2410_TICNT); | |
691 | } | |
692 | ||
693 | static void s3c6410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
694 | { | |
695 | int val; | |
696 | ||
697 | val = (info->rtc->max_user_freq / freq) - 1; | |
698 | writel(val, info->base + S3C2410_TICNT); | |
699 | } | |
700 | ||
701 | static void s3c24xx_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
702 | { | |
703 | unsigned int ticnt; | |
704 | ||
705 | ticnt = readb(info->base + S3C2410_TICNT); | |
706 | ticnt &= S3C2410_TICNT_ENABLE; | |
707 | ||
708 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
709 | } | |
710 | ||
711 | static void s3c2416_rtc_select_tick_clk(struct s3c_rtc *info) | |
712 | { | |
713 | unsigned int con; | |
714 | ||
715 | con = readw(info->base + S3C2410_RTCCON); | |
716 | con |= S3C2443_RTCCON_TICSEL; | |
717 | writew(con, info->base + S3C2410_RTCCON); | |
718 | } | |
719 | ||
720 | static void s3c6410_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
721 | { | |
722 | unsigned int ticnt; | |
723 | ||
724 | ticnt = readw(info->base + S3C2410_RTCCON); | |
725 | ticnt &= S3C64XX_RTCCON_TICEN; | |
726 | ||
727 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
728 | } | |
729 | ||
730 | static void s3c24xx_rtc_save_tick_cnt(struct s3c_rtc *info) | |
731 | { | |
732 | info->ticnt_save = readb(info->base + S3C2410_TICNT); | |
733 | } | |
734 | ||
735 | static void s3c24xx_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
736 | { | |
737 | writeb(info->ticnt_save, info->base + S3C2410_TICNT); | |
738 | } | |
739 | ||
740 | static void s3c6410_rtc_save_tick_cnt(struct s3c_rtc *info) | |
741 | { | |
742 | info->ticnt_en_save = readw(info->base + S3C2410_RTCCON); | |
743 | info->ticnt_en_save &= S3C64XX_RTCCON_TICEN; | |
744 | info->ticnt_save = readl(info->base + S3C2410_TICNT); | |
745 | } | |
746 | ||
747 | static void s3c6410_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
748 | { | |
749 | unsigned int con; | |
750 | ||
751 | writel(info->ticnt_save, info->base + S3C2410_TICNT); | |
752 | if (info->ticnt_en_save) { | |
753 | con = readw(info->base + S3C2410_RTCCON); | |
fc1afe60 | 754 | writew(con | info->ticnt_en_save, info->base + S3C2410_RTCCON); |
ae05c950 CC |
755 | } |
756 | } | |
757 | ||
758 | static struct s3c_rtc_data const s3c2410_rtc_data = { | |
759 | .max_user_freq = 128, | |
760 | .irq_handler = s3c24xx_rtc_irq, | |
761 | .set_freq = s3c2410_rtc_setfreq, | |
762 | .enable_tick = s3c24xx_rtc_enable_tick, | |
763 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
764 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
765 | .enable = s3c24xx_rtc_enable, | |
766 | .disable = s3c24xx_rtc_disable, | |
767 | }; | |
768 | ||
769 | static struct s3c_rtc_data const s3c2416_rtc_data = { | |
770 | .max_user_freq = 32768, | |
771 | .irq_handler = s3c24xx_rtc_irq, | |
772 | .set_freq = s3c2416_rtc_setfreq, | |
773 | .enable_tick = s3c24xx_rtc_enable_tick, | |
774 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
775 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
776 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
777 | .enable = s3c24xx_rtc_enable, | |
778 | .disable = s3c24xx_rtc_disable, | |
779 | }; | |
780 | ||
781 | static struct s3c_rtc_data const s3c2443_rtc_data = { | |
782 | .max_user_freq = 32768, | |
783 | .irq_handler = s3c24xx_rtc_irq, | |
784 | .set_freq = s3c2443_rtc_setfreq, | |
785 | .enable_tick = s3c24xx_rtc_enable_tick, | |
786 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
787 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
788 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
789 | .enable = s3c24xx_rtc_enable, | |
790 | .disable = s3c24xx_rtc_disable, | |
791 | }; | |
792 | ||
793 | static struct s3c_rtc_data const s3c6410_rtc_data = { | |
794 | .max_user_freq = 32768, | |
8792f777 | 795 | .needs_src_clk = true, |
ae05c950 CC |
796 | .irq_handler = s3c6410_rtc_irq, |
797 | .set_freq = s3c6410_rtc_setfreq, | |
798 | .enable_tick = s3c6410_rtc_enable_tick, | |
799 | .save_tick_cnt = s3c6410_rtc_save_tick_cnt, | |
800 | .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt, | |
801 | .enable = s3c24xx_rtc_enable, | |
802 | .disable = s3c6410_rtc_disable, | |
c3cba928 TB |
803 | }; |
804 | ||
39ce4084 | 805 | static const struct of_device_id s3c_rtc_dt_match[] = { |
d2524caa | 806 | { |
cd1e6f9e | 807 | .compatible = "samsung,s3c2410-rtc", |
21df6fed | 808 | .data = &s3c2410_rtc_data, |
25c1a246 | 809 | }, { |
cd1e6f9e | 810 | .compatible = "samsung,s3c2416-rtc", |
21df6fed | 811 | .data = &s3c2416_rtc_data, |
25c1a246 | 812 | }, { |
cd1e6f9e | 813 | .compatible = "samsung,s3c2443-rtc", |
21df6fed | 814 | .data = &s3c2443_rtc_data, |
d2524caa | 815 | }, { |
cd1e6f9e | 816 | .compatible = "samsung,s3c6410-rtc", |
21df6fed | 817 | .data = &s3c6410_rtc_data, |
df9e26d0 CC |
818 | }, { |
819 | .compatible = "samsung,exynos3250-rtc", | |
21df6fed | 820 | .data = &s3c6410_rtc_data, |
d2524caa | 821 | }, |
ae05c950 | 822 | { /* sentinel */ }, |
39ce4084 TA |
823 | }; |
824 | MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match); | |
9f4123b7 MC |
825 | |
826 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 827 | .probe = s3c_rtc_probe, |
5a167f45 | 828 | .remove = s3c_rtc_remove, |
1add6781 | 829 | .driver = { |
9f4123b7 | 830 | .name = "s3c-rtc", |
32e445aa | 831 | .pm = &s3c_rtc_pm_ops, |
04a373fd | 832 | .of_match_table = of_match_ptr(s3c_rtc_dt_match), |
1add6781 BD |
833 | }, |
834 | }; | |
0c4eae66 | 835 | module_platform_driver(s3c_rtc_driver); |
1add6781 BD |
836 | |
837 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
838 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
839 | MODULE_LICENSE("GPL"); | |
ad28a07b | 840 | MODULE_ALIAS("platform:s3c2410-rtc"); |