Commit | Line | Data |
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2eeaa532 AB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * RTC driver for the Micro Crystal RV3032 | |
4 | * | |
5 | * Copyright (C) 2020 Micro Crystal SA | |
6 | * | |
7 | * Alexandre Belloni <alexandre.belloni@bootlin.com> | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/bcd.h> | |
14 | #include <linux/bitfield.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/hwmon.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/log2.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/regmap.h> | |
24 | #include <linux/rtc.h> | |
25 | ||
26 | #define RV3032_SEC 0x01 | |
27 | #define RV3032_MIN 0x02 | |
28 | #define RV3032_HOUR 0x03 | |
29 | #define RV3032_WDAY 0x04 | |
30 | #define RV3032_DAY 0x05 | |
31 | #define RV3032_MONTH 0x06 | |
32 | #define RV3032_YEAR 0x07 | |
33 | #define RV3032_ALARM_MIN 0x08 | |
34 | #define RV3032_ALARM_HOUR 0x09 | |
35 | #define RV3032_ALARM_DAY 0x0A | |
36 | #define RV3032_STATUS 0x0D | |
37 | #define RV3032_TLSB 0x0E | |
38 | #define RV3032_TMSB 0x0F | |
39 | #define RV3032_CTRL1 0x10 | |
40 | #define RV3032_CTRL2 0x11 | |
41 | #define RV3032_CTRL3 0x12 | |
42 | #define RV3032_TS_CTRL 0x13 | |
43 | #define RV3032_CLK_IRQ 0x14 | |
44 | #define RV3032_EEPROM_ADDR 0x3D | |
45 | #define RV3032_EEPROM_DATA 0x3E | |
46 | #define RV3032_EEPROM_CMD 0x3F | |
47 | #define RV3032_RAM1 0x40 | |
48 | #define RV3032_PMU 0xC0 | |
49 | #define RV3032_OFFSET 0xC1 | |
50 | #define RV3032_CLKOUT1 0xC2 | |
51 | #define RV3032_CLKOUT2 0xC3 | |
52 | #define RV3032_TREF0 0xC4 | |
53 | #define RV3032_TREF1 0xC5 | |
54 | ||
55 | #define RV3032_STATUS_VLF BIT(0) | |
56 | #define RV3032_STATUS_PORF BIT(1) | |
57 | #define RV3032_STATUS_EVF BIT(2) | |
58 | #define RV3032_STATUS_AF BIT(3) | |
59 | #define RV3032_STATUS_TF BIT(4) | |
60 | #define RV3032_STATUS_UF BIT(5) | |
61 | #define RV3032_STATUS_TLF BIT(6) | |
62 | #define RV3032_STATUS_THF BIT(7) | |
63 | ||
64 | #define RV3032_TLSB_CLKF BIT(1) | |
65 | #define RV3032_TLSB_EEBUSY BIT(2) | |
66 | #define RV3032_TLSB_TEMP GENMASK(7, 4) | |
67 | ||
68 | #define RV3032_CLKOUT2_HFD_MSK GENMASK(4, 0) | |
69 | #define RV3032_CLKOUT2_FD_MSK GENMASK(6, 5) | |
70 | #define RV3032_CLKOUT2_OS BIT(7) | |
71 | ||
72 | #define RV3032_CTRL1_EERD BIT(3) | |
73 | #define RV3032_CTRL1_WADA BIT(5) | |
74 | ||
75 | #define RV3032_CTRL2_STOP BIT(0) | |
76 | #define RV3032_CTRL2_EIE BIT(2) | |
77 | #define RV3032_CTRL2_AIE BIT(3) | |
78 | #define RV3032_CTRL2_TIE BIT(4) | |
79 | #define RV3032_CTRL2_UIE BIT(5) | |
80 | #define RV3032_CTRL2_CLKIE BIT(6) | |
81 | #define RV3032_CTRL2_TSE BIT(7) | |
82 | ||
83 | #define RV3032_PMU_TCM GENMASK(1, 0) | |
84 | #define RV3032_PMU_TCR GENMASK(3, 2) | |
85 | #define RV3032_PMU_BSM GENMASK(5, 4) | |
86 | #define RV3032_PMU_NCLKE BIT(6) | |
87 | ||
88 | #define RV3032_PMU_BSM_DSM 1 | |
89 | #define RV3032_PMU_BSM_LSM 2 | |
90 | ||
91 | #define RV3032_OFFSET_MSK GENMASK(5, 0) | |
92 | ||
93 | #define RV3032_EVT_CTRL_TSR BIT(2) | |
94 | ||
95 | #define RV3032_EEPROM_CMD_UPDATE 0x11 | |
96 | #define RV3032_EEPROM_CMD_WRITE 0x21 | |
97 | #define RV3032_EEPROM_CMD_READ 0x22 | |
98 | ||
99 | #define RV3032_EEPROM_USER 0xCB | |
100 | ||
101 | #define RV3032_EEBUSY_POLL 10000 | |
102 | #define RV3032_EEBUSY_TIMEOUT 100000 | |
103 | ||
104 | #define OFFSET_STEP_PPT 238419 | |
105 | ||
106 | struct rv3032_data { | |
107 | struct regmap *regmap; | |
108 | struct rtc_device *rtc; | |
109 | #ifdef CONFIG_COMMON_CLK | |
110 | struct clk_hw clkout_hw; | |
111 | #endif | |
112 | }; | |
113 | ||
114 | static u16 rv3032_trickle_resistors[] = {1000, 2000, 7000, 11000}; | |
115 | static u16 rv3032_trickle_voltages[] = {0, 1750, 3000, 4400}; | |
116 | ||
117 | static int rv3032_exit_eerd(struct rv3032_data *rv3032, u32 eerd) | |
118 | { | |
119 | if (eerd) | |
120 | return 0; | |
121 | ||
122 | return regmap_update_bits(rv3032->regmap, RV3032_CTRL1, RV3032_CTRL1_EERD, 0); | |
123 | } | |
124 | ||
125 | static int rv3032_enter_eerd(struct rv3032_data *rv3032, u32 *eerd) | |
126 | { | |
127 | u32 ctrl1, status; | |
128 | int ret; | |
129 | ||
130 | ret = regmap_read(rv3032->regmap, RV3032_CTRL1, &ctrl1); | |
131 | if (ret) | |
132 | return ret; | |
133 | ||
134 | *eerd = ctrl1 & RV3032_CTRL1_EERD; | |
135 | if (*eerd) | |
136 | return 0; | |
137 | ||
138 | ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1, | |
139 | RV3032_CTRL1_EERD, RV3032_CTRL1_EERD); | |
140 | if (ret) | |
141 | return ret; | |
142 | ||
143 | ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status, | |
144 | !(status & RV3032_TLSB_EEBUSY), | |
145 | RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT); | |
146 | if (ret) { | |
147 | rv3032_exit_eerd(rv3032, *eerd); | |
148 | ||
149 | return ret; | |
150 | } | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | static int rv3032_update_cfg(struct rv3032_data *rv3032, unsigned int reg, | |
156 | unsigned int mask, unsigned int val) | |
157 | { | |
158 | u32 status, eerd; | |
159 | int ret; | |
160 | ||
161 | ret = rv3032_enter_eerd(rv3032, &eerd); | |
162 | if (ret) | |
163 | return ret; | |
164 | ||
165 | ret = regmap_update_bits(rv3032->regmap, reg, mask, val); | |
166 | if (ret) | |
167 | goto exit_eerd; | |
168 | ||
169 | ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE); | |
170 | if (ret) | |
171 | goto exit_eerd; | |
172 | ||
173 | usleep_range(46000, RV3032_EEBUSY_TIMEOUT); | |
174 | ||
175 | ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status, | |
176 | !(status & RV3032_TLSB_EEBUSY), | |
177 | RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT); | |
178 | ||
179 | exit_eerd: | |
180 | rv3032_exit_eerd(rv3032, eerd); | |
181 | ||
182 | return ret; | |
183 | } | |
184 | ||
185 | static irqreturn_t rv3032_handle_irq(int irq, void *dev_id) | |
186 | { | |
187 | struct rv3032_data *rv3032 = dev_id; | |
188 | unsigned long events = 0; | |
189 | u32 status = 0, ctrl = 0; | |
190 | ||
191 | if (regmap_read(rv3032->regmap, RV3032_STATUS, &status) < 0 || | |
192 | status == 0) { | |
193 | return IRQ_NONE; | |
194 | } | |
195 | ||
196 | if (status & RV3032_STATUS_TF) { | |
197 | status |= RV3032_STATUS_TF; | |
198 | ctrl |= RV3032_CTRL2_TIE; | |
199 | events |= RTC_PF; | |
200 | } | |
201 | ||
202 | if (status & RV3032_STATUS_AF) { | |
203 | status |= RV3032_STATUS_AF; | |
204 | ctrl |= RV3032_CTRL2_AIE; | |
205 | events |= RTC_AF; | |
206 | } | |
207 | ||
208 | if (status & RV3032_STATUS_UF) { | |
209 | status |= RV3032_STATUS_UF; | |
210 | ctrl |= RV3032_CTRL2_UIE; | |
211 | events |= RTC_UF; | |
212 | } | |
213 | ||
214 | if (events) { | |
215 | rtc_update_irq(rv3032->rtc, 1, events); | |
216 | regmap_update_bits(rv3032->regmap, RV3032_STATUS, status, 0); | |
217 | regmap_update_bits(rv3032->regmap, RV3032_CTRL2, ctrl, 0); | |
218 | } | |
219 | ||
220 | return IRQ_HANDLED; | |
221 | } | |
222 | ||
223 | static int rv3032_get_time(struct device *dev, struct rtc_time *tm) | |
224 | { | |
225 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
226 | u8 date[7]; | |
227 | int ret, status; | |
228 | ||
229 | ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status); | |
230 | if (ret < 0) | |
231 | return ret; | |
232 | ||
233 | if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF)) | |
234 | return -EINVAL; | |
235 | ||
236 | ret = regmap_bulk_read(rv3032->regmap, RV3032_SEC, date, sizeof(date)); | |
237 | if (ret) | |
238 | return ret; | |
239 | ||
240 | tm->tm_sec = bcd2bin(date[0] & 0x7f); | |
241 | tm->tm_min = bcd2bin(date[1] & 0x7f); | |
242 | tm->tm_hour = bcd2bin(date[2] & 0x3f); | |
243 | tm->tm_wday = date[3] & 0x7; | |
244 | tm->tm_mday = bcd2bin(date[4] & 0x3f); | |
245 | tm->tm_mon = bcd2bin(date[5] & 0x1f) - 1; | |
246 | tm->tm_year = bcd2bin(date[6]) + 100; | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
251 | static int rv3032_set_time(struct device *dev, struct rtc_time *tm) | |
252 | { | |
253 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
254 | u8 date[7]; | |
255 | int ret; | |
256 | ||
257 | date[0] = bin2bcd(tm->tm_sec); | |
258 | date[1] = bin2bcd(tm->tm_min); | |
259 | date[2] = bin2bcd(tm->tm_hour); | |
260 | date[3] = tm->tm_wday; | |
261 | date[4] = bin2bcd(tm->tm_mday); | |
262 | date[5] = bin2bcd(tm->tm_mon + 1); | |
263 | date[6] = bin2bcd(tm->tm_year - 100); | |
264 | ||
265 | ret = regmap_bulk_write(rv3032->regmap, RV3032_SEC, date, | |
266 | sizeof(date)); | |
267 | if (ret) | |
268 | return ret; | |
269 | ||
270 | ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS, | |
271 | RV3032_STATUS_PORF | RV3032_STATUS_VLF, 0); | |
272 | ||
273 | return ret; | |
274 | } | |
275 | ||
276 | static int rv3032_get_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
277 | { | |
278 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
279 | u8 alarmvals[3]; | |
280 | int status, ctrl, ret; | |
281 | ||
282 | ret = regmap_bulk_read(rv3032->regmap, RV3032_ALARM_MIN, alarmvals, | |
283 | sizeof(alarmvals)); | |
284 | if (ret) | |
285 | return ret; | |
286 | ||
287 | ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status); | |
288 | if (ret < 0) | |
289 | return ret; | |
290 | ||
291 | ret = regmap_read(rv3032->regmap, RV3032_CTRL2, &ctrl); | |
292 | if (ret < 0) | |
293 | return ret; | |
294 | ||
295 | alrm->time.tm_sec = 0; | |
296 | alrm->time.tm_min = bcd2bin(alarmvals[0] & 0x7f); | |
297 | alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f); | |
298 | alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f); | |
299 | ||
300 | alrm->enabled = !!(ctrl & RV3032_CTRL2_AIE); | |
301 | alrm->pending = (status & RV3032_STATUS_AF) && alrm->enabled; | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | static int rv3032_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
307 | { | |
308 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
309 | u8 alarmvals[3]; | |
310 | u8 ctrl = 0; | |
311 | int ret; | |
312 | ||
313 | /* The alarm has no seconds, round up to nearest minute */ | |
314 | if (alrm->time.tm_sec) { | |
315 | time64_t alarm_time = rtc_tm_to_time64(&alrm->time); | |
316 | ||
317 | alarm_time += 60 - alrm->time.tm_sec; | |
318 | rtc_time64_to_tm(alarm_time, &alrm->time); | |
319 | } | |
320 | ||
321 | ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, | |
322 | RV3032_CTRL2_AIE | RV3032_CTRL2_UIE, 0); | |
323 | if (ret) | |
324 | return ret; | |
325 | ||
326 | alarmvals[0] = bin2bcd(alrm->time.tm_min); | |
327 | alarmvals[1] = bin2bcd(alrm->time.tm_hour); | |
328 | alarmvals[2] = bin2bcd(alrm->time.tm_mday); | |
329 | ||
330 | ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS, | |
331 | RV3032_STATUS_AF, 0); | |
332 | if (ret) | |
333 | return ret; | |
334 | ||
335 | ret = regmap_bulk_write(rv3032->regmap, RV3032_ALARM_MIN, alarmvals, | |
336 | sizeof(alarmvals)); | |
337 | if (ret) | |
338 | return ret; | |
339 | ||
340 | if (alrm->enabled) { | |
341 | if (rv3032->rtc->uie_rtctimer.enabled) | |
342 | ctrl |= RV3032_CTRL2_UIE; | |
343 | if (rv3032->rtc->aie_timer.enabled) | |
344 | ctrl |= RV3032_CTRL2_AIE; | |
345 | } | |
346 | ||
347 | ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, | |
348 | RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl); | |
349 | ||
350 | return ret; | |
351 | } | |
352 | ||
353 | static int rv3032_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
354 | { | |
355 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
356 | int ctrl = 0, ret; | |
357 | ||
358 | if (enabled) { | |
359 | if (rv3032->rtc->uie_rtctimer.enabled) | |
360 | ctrl |= RV3032_CTRL2_UIE; | |
361 | if (rv3032->rtc->aie_timer.enabled) | |
362 | ctrl |= RV3032_CTRL2_AIE; | |
363 | } | |
364 | ||
365 | ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS, | |
366 | RV3032_STATUS_AF | RV3032_STATUS_UF, 0); | |
367 | if (ret) | |
368 | return ret; | |
369 | ||
370 | ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, | |
371 | RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl); | |
372 | if (ret) | |
373 | return ret; | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | static int rv3032_read_offset(struct device *dev, long *offset) | |
379 | { | |
380 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
381 | int ret, value, steps; | |
382 | ||
383 | ret = regmap_read(rv3032->regmap, RV3032_OFFSET, &value); | |
384 | if (ret < 0) | |
385 | return ret; | |
386 | ||
387 | steps = sign_extend32(FIELD_GET(RV3032_OFFSET_MSK, value), 5); | |
388 | ||
389 | *offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000); | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | static int rv3032_set_offset(struct device *dev, long offset) | |
395 | { | |
396 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
397 | ||
398 | offset = clamp(offset, -7629L, 7391L) * 1000; | |
399 | offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT); | |
400 | ||
401 | return rv3032_update_cfg(rv3032, RV3032_OFFSET, RV3032_OFFSET_MSK, | |
402 | FIELD_PREP(RV3032_OFFSET_MSK, offset)); | |
403 | } | |
404 | ||
405 | static int rv3032_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
406 | { | |
407 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
408 | int status, val = 0, ret = 0; | |
409 | ||
410 | switch (cmd) { | |
411 | case RTC_VL_READ: | |
412 | ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status); | |
413 | if (ret < 0) | |
414 | return ret; | |
415 | ||
416 | if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF)) | |
417 | val = RTC_VL_DATA_INVALID; | |
418 | return put_user(val, (unsigned int __user *)arg); | |
419 | ||
420 | default: | |
421 | return -ENOIOCTLCMD; | |
422 | } | |
423 | } | |
424 | ||
425 | static int rv3032_nvram_write(void *priv, unsigned int offset, void *val, size_t bytes) | |
426 | { | |
427 | return regmap_bulk_write(priv, RV3032_RAM1 + offset, val, bytes); | |
428 | } | |
429 | ||
430 | static int rv3032_nvram_read(void *priv, unsigned int offset, void *val, size_t bytes) | |
431 | { | |
432 | return regmap_bulk_read(priv, RV3032_RAM1 + offset, val, bytes); | |
433 | } | |
434 | ||
435 | static int rv3032_eeprom_write(void *priv, unsigned int offset, void *val, size_t bytes) | |
436 | { | |
437 | struct rv3032_data *rv3032 = priv; | |
438 | u32 status, eerd; | |
439 | int i, ret; | |
440 | u8 *buf = val; | |
441 | ||
442 | ret = rv3032_enter_eerd(rv3032, &eerd); | |
443 | if (ret) | |
444 | return ret; | |
445 | ||
446 | for (i = 0; i < bytes; i++) { | |
447 | ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR, | |
448 | RV3032_EEPROM_USER + offset + i); | |
449 | if (ret) | |
450 | goto exit_eerd; | |
451 | ||
452 | ret = regmap_write(rv3032->regmap, RV3032_EEPROM_DATA, buf[i]); | |
453 | if (ret) | |
454 | goto exit_eerd; | |
455 | ||
456 | ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, | |
457 | RV3032_EEPROM_CMD_WRITE); | |
458 | if (ret) | |
459 | goto exit_eerd; | |
460 | ||
461 | usleep_range(RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT); | |
462 | ||
463 | ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status, | |
464 | !(status & RV3032_TLSB_EEBUSY), | |
465 | RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT); | |
466 | if (ret) | |
467 | goto exit_eerd; | |
468 | } | |
469 | ||
470 | exit_eerd: | |
471 | rv3032_exit_eerd(rv3032, eerd); | |
472 | ||
473 | return ret; | |
474 | } | |
475 | ||
476 | static int rv3032_eeprom_read(void *priv, unsigned int offset, void *val, size_t bytes) | |
477 | { | |
478 | struct rv3032_data *rv3032 = priv; | |
479 | u32 status, eerd, data; | |
480 | int i, ret; | |
481 | u8 *buf = val; | |
482 | ||
483 | ret = rv3032_enter_eerd(rv3032, &eerd); | |
484 | if (ret) | |
485 | return ret; | |
486 | ||
487 | for (i = 0; i < bytes; i++) { | |
488 | ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR, | |
489 | RV3032_EEPROM_USER + offset + i); | |
490 | if (ret) | |
491 | goto exit_eerd; | |
492 | ||
493 | ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, | |
494 | RV3032_EEPROM_CMD_READ); | |
495 | if (ret) | |
496 | goto exit_eerd; | |
497 | ||
498 | ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status, | |
499 | !(status & RV3032_TLSB_EEBUSY), | |
500 | RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT); | |
501 | if (ret) | |
502 | goto exit_eerd; | |
503 | ||
504 | ret = regmap_read(rv3032->regmap, RV3032_EEPROM_DATA, &data); | |
505 | if (ret) | |
506 | goto exit_eerd; | |
507 | buf[i] = data; | |
508 | } | |
509 | ||
510 | exit_eerd: | |
511 | rv3032_exit_eerd(rv3032, eerd); | |
512 | ||
513 | return ret; | |
514 | } | |
515 | ||
516 | static int rv3032_trickle_charger_setup(struct device *dev, struct rv3032_data *rv3032) | |
517 | { | |
518 | u32 val, ohms, voltage; | |
519 | int i; | |
520 | ||
521 | val = FIELD_PREP(RV3032_PMU_TCM, 1) | FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_DSM); | |
522 | if (!device_property_read_u32(dev, "trickle-voltage-millivolt", &voltage)) { | |
523 | for (i = 0; i < ARRAY_SIZE(rv3032_trickle_voltages); i++) | |
524 | if (voltage == rv3032_trickle_voltages[i]) | |
525 | break; | |
526 | if (i < ARRAY_SIZE(rv3032_trickle_voltages)) | |
527 | val = FIELD_PREP(RV3032_PMU_TCM, i) | | |
528 | FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_LSM); | |
529 | } | |
530 | ||
531 | if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms)) | |
532 | return 0; | |
533 | ||
534 | for (i = 0; i < ARRAY_SIZE(rv3032_trickle_resistors); i++) | |
535 | if (ohms == rv3032_trickle_resistors[i]) | |
536 | break; | |
537 | ||
538 | if (i >= ARRAY_SIZE(rv3032_trickle_resistors)) { | |
539 | dev_warn(dev, "invalid trickle resistor value\n"); | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | return rv3032_update_cfg(rv3032, RV3032_PMU, | |
545 | RV3032_PMU_TCR | RV3032_PMU_TCM | RV3032_PMU_BSM, | |
546 | val | FIELD_PREP(RV3032_PMU_TCR, i)); | |
547 | } | |
548 | ||
549 | #ifdef CONFIG_COMMON_CLK | |
550 | #define clkout_hw_to_rv3032(hw) container_of(hw, struct rv3032_data, clkout_hw) | |
551 | ||
552 | static int clkout_xtal_rates[] = { | |
553 | 32768, | |
554 | 1024, | |
555 | 64, | |
556 | 1, | |
557 | }; | |
558 | ||
559 | #define RV3032_HFD_STEP 8192 | |
560 | ||
561 | static unsigned long rv3032_clkout_recalc_rate(struct clk_hw *hw, | |
562 | unsigned long parent_rate) | |
563 | { | |
564 | int clkout, ret; | |
565 | struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw); | |
566 | ||
567 | ret = regmap_read(rv3032->regmap, RV3032_CLKOUT2, &clkout); | |
568 | if (ret < 0) | |
569 | return 0; | |
570 | ||
571 | if (clkout & RV3032_CLKOUT2_OS) { | |
572 | unsigned long rate = FIELD_GET(RV3032_CLKOUT2_HFD_MSK, clkout) << 8; | |
573 | ||
574 | ret = regmap_read(rv3032->regmap, RV3032_CLKOUT1, &clkout); | |
575 | if (ret < 0) | |
576 | return 0; | |
577 | ||
578 | rate += clkout + 1; | |
579 | ||
580 | return rate * RV3032_HFD_STEP; | |
581 | } | |
582 | ||
583 | return clkout_xtal_rates[FIELD_GET(RV3032_CLKOUT2_FD_MSK, clkout)]; | |
584 | } | |
585 | ||
586 | static long rv3032_clkout_round_rate(struct clk_hw *hw, unsigned long rate, | |
587 | unsigned long *prate) | |
588 | { | |
589 | int i, hfd; | |
590 | ||
591 | if (rate < RV3032_HFD_STEP) | |
592 | for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++) | |
593 | if (clkout_xtal_rates[i] <= rate) | |
594 | return clkout_xtal_rates[i]; | |
595 | ||
596 | hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP); | |
597 | ||
598 | return RV3032_HFD_STEP * clamp(hfd, 0, 8192); | |
599 | } | |
600 | ||
601 | static int rv3032_clkout_set_rate(struct clk_hw *hw, unsigned long rate, | |
602 | unsigned long parent_rate) | |
603 | { | |
604 | struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw); | |
605 | u32 status, eerd; | |
606 | int i, hfd, ret; | |
607 | ||
608 | for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++) { | |
609 | if (clkout_xtal_rates[i] == rate) { | |
610 | return rv3032_update_cfg(rv3032, RV3032_CLKOUT2, 0xff, | |
611 | FIELD_PREP(RV3032_CLKOUT2_FD_MSK, i)); | |
612 | } | |
613 | } | |
614 | ||
615 | hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP); | |
616 | hfd = clamp(hfd, 1, 8192) - 1; | |
617 | ||
618 | ret = rv3032_enter_eerd(rv3032, &eerd); | |
619 | if (ret) | |
620 | goto exit_eerd; | |
621 | ||
622 | ret = regmap_write(rv3032->regmap, RV3032_CLKOUT1, hfd & 0xff); | |
623 | if (ret) | |
624 | return ret; | |
625 | ||
626 | ret = regmap_write(rv3032->regmap, RV3032_CLKOUT2, RV3032_CLKOUT2_OS | | |
627 | FIELD_PREP(RV3032_CLKOUT2_HFD_MSK, hfd >> 8)); | |
628 | if (ret) | |
629 | goto exit_eerd; | |
630 | ||
631 | ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE); | |
632 | if (ret) | |
633 | goto exit_eerd; | |
634 | ||
635 | usleep_range(46000, RV3032_EEBUSY_TIMEOUT); | |
636 | ||
637 | ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status, | |
638 | !(status & RV3032_TLSB_EEBUSY), | |
639 | RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT); | |
640 | ||
641 | exit_eerd: | |
642 | rv3032_exit_eerd(rv3032, eerd); | |
643 | ||
644 | return ret; | |
645 | } | |
646 | ||
647 | static int rv3032_clkout_prepare(struct clk_hw *hw) | |
648 | { | |
649 | struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw); | |
650 | ||
651 | return rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, 0); | |
652 | } | |
653 | ||
654 | static void rv3032_clkout_unprepare(struct clk_hw *hw) | |
655 | { | |
656 | struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw); | |
657 | ||
658 | rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, RV3032_PMU_NCLKE); | |
659 | } | |
660 | ||
661 | static int rv3032_clkout_is_prepared(struct clk_hw *hw) | |
662 | { | |
663 | int val, ret; | |
664 | struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw); | |
665 | ||
666 | ret = regmap_read(rv3032->regmap, RV3032_PMU, &val); | |
667 | if (ret < 0) | |
668 | return ret; | |
669 | ||
670 | return !(val & RV3032_PMU_NCLKE); | |
671 | } | |
672 | ||
673 | static const struct clk_ops rv3032_clkout_ops = { | |
674 | .prepare = rv3032_clkout_prepare, | |
675 | .unprepare = rv3032_clkout_unprepare, | |
676 | .is_prepared = rv3032_clkout_is_prepared, | |
677 | .recalc_rate = rv3032_clkout_recalc_rate, | |
678 | .round_rate = rv3032_clkout_round_rate, | |
679 | .set_rate = rv3032_clkout_set_rate, | |
680 | }; | |
681 | ||
682 | static int rv3032_clkout_register_clk(struct rv3032_data *rv3032, | |
683 | struct i2c_client *client) | |
684 | { | |
685 | int ret; | |
686 | struct clk *clk; | |
687 | struct clk_init_data init; | |
688 | struct device_node *node = client->dev.of_node; | |
689 | ||
690 | ret = regmap_update_bits(rv3032->regmap, RV3032_TLSB, RV3032_TLSB_CLKF, 0); | |
691 | if (ret < 0) | |
692 | return ret; | |
693 | ||
694 | ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, RV3032_CTRL2_CLKIE, 0); | |
695 | if (ret < 0) | |
696 | return ret; | |
697 | ||
698 | ret = regmap_write(rv3032->regmap, RV3032_CLK_IRQ, 0); | |
699 | if (ret < 0) | |
700 | return ret; | |
701 | ||
702 | init.name = "rv3032-clkout"; | |
703 | init.ops = &rv3032_clkout_ops; | |
704 | init.flags = 0; | |
705 | init.parent_names = NULL; | |
706 | init.num_parents = 0; | |
707 | rv3032->clkout_hw.init = &init; | |
708 | ||
709 | of_property_read_string(node, "clock-output-names", &init.name); | |
710 | ||
711 | clk = devm_clk_register(&client->dev, &rv3032->clkout_hw); | |
712 | if (!IS_ERR(clk)) | |
713 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
714 | ||
715 | return 0; | |
716 | } | |
717 | #endif | |
718 | ||
719 | static int rv3032_hwmon_read_temp(struct device *dev, long *mC) | |
720 | { | |
721 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
722 | u8 buf[2]; | |
723 | int temp, prev = 0; | |
724 | int ret; | |
725 | ||
726 | ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf)); | |
727 | if (ret) | |
728 | return ret; | |
729 | ||
730 | temp = sign_extend32(buf[1], 7) << 4; | |
731 | temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]); | |
732 | ||
733 | /* No blocking or shadowing on RV3032_TLSB and RV3032_TMSB */ | |
734 | do { | |
735 | prev = temp; | |
736 | ||
737 | ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf)); | |
738 | if (ret) | |
739 | return ret; | |
740 | ||
741 | temp = sign_extend32(buf[1], 7) << 4; | |
742 | temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]); | |
743 | } while (temp != prev); | |
744 | ||
745 | *mC = (temp * 1000) / 16; | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | static umode_t rv3032_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, | |
751 | u32 attr, int channel) | |
752 | { | |
753 | if (type != hwmon_temp) | |
754 | return 0; | |
755 | ||
756 | switch (attr) { | |
757 | case hwmon_temp_input: | |
758 | return 0444; | |
759 | default: | |
760 | return 0; | |
761 | } | |
762 | } | |
763 | ||
764 | static int rv3032_hwmon_read(struct device *dev, enum hwmon_sensor_types type, | |
765 | u32 attr, int channel, long *temp) | |
766 | { | |
767 | int err; | |
768 | ||
769 | switch (attr) { | |
770 | case hwmon_temp_input: | |
771 | err = rv3032_hwmon_read_temp(dev, temp); | |
772 | break; | |
773 | default: | |
774 | err = -EOPNOTSUPP; | |
775 | break; | |
776 | } | |
777 | ||
778 | return err; | |
779 | } | |
780 | ||
781 | static const struct hwmon_channel_info *rv3032_hwmon_info[] = { | |
782 | HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ), | |
783 | HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST), | |
784 | NULL | |
785 | }; | |
786 | ||
787 | static const struct hwmon_ops rv3032_hwmon_hwmon_ops = { | |
788 | .is_visible = rv3032_hwmon_is_visible, | |
789 | .read = rv3032_hwmon_read, | |
790 | }; | |
791 | ||
792 | static const struct hwmon_chip_info rv3032_hwmon_chip_info = { | |
793 | .ops = &rv3032_hwmon_hwmon_ops, | |
794 | .info = rv3032_hwmon_info, | |
795 | }; | |
796 | ||
797 | static void rv3032_hwmon_register(struct device *dev) | |
798 | { | |
799 | struct rv3032_data *rv3032 = dev_get_drvdata(dev); | |
800 | ||
801 | if (!IS_REACHABLE(CONFIG_HWMON)) | |
802 | return; | |
803 | ||
804 | devm_hwmon_device_register_with_info(dev, "rv3032", rv3032, &rv3032_hwmon_chip_info, NULL); | |
805 | } | |
806 | ||
19588d50 | 807 | static const struct rtc_class_ops rv3032_rtc_ops = { |
2eeaa532 AB |
808 | .read_time = rv3032_get_time, |
809 | .set_time = rv3032_set_time, | |
810 | .read_offset = rv3032_read_offset, | |
811 | .set_offset = rv3032_set_offset, | |
812 | .ioctl = rv3032_ioctl, | |
19588d50 AB |
813 | .read_alarm = rv3032_get_alarm, |
814 | .set_alarm = rv3032_set_alarm, | |
815 | .alarm_irq_enable = rv3032_alarm_irq_enable, | |
2eeaa532 AB |
816 | }; |
817 | ||
818 | static const struct regmap_config regmap_config = { | |
819 | .reg_bits = 8, | |
820 | .val_bits = 8, | |
821 | .max_register = 0xCA, | |
822 | }; | |
823 | ||
824 | static int rv3032_probe(struct i2c_client *client) | |
825 | { | |
826 | struct rv3032_data *rv3032; | |
827 | int ret, status; | |
828 | struct nvmem_config nvmem_cfg = { | |
829 | .name = "rv3032_nvram", | |
830 | .word_size = 1, | |
831 | .stride = 1, | |
832 | .size = 16, | |
833 | .type = NVMEM_TYPE_BATTERY_BACKED, | |
834 | .reg_read = rv3032_nvram_read, | |
835 | .reg_write = rv3032_nvram_write, | |
836 | }; | |
837 | struct nvmem_config eeprom_cfg = { | |
838 | .name = "rv3032_eeprom", | |
839 | .word_size = 1, | |
840 | .stride = 1, | |
841 | .size = 32, | |
842 | .type = NVMEM_TYPE_EEPROM, | |
843 | .reg_read = rv3032_eeprom_read, | |
844 | .reg_write = rv3032_eeprom_write, | |
845 | }; | |
846 | ||
847 | rv3032 = devm_kzalloc(&client->dev, sizeof(struct rv3032_data), | |
848 | GFP_KERNEL); | |
849 | if (!rv3032) | |
850 | return -ENOMEM; | |
851 | ||
852 | rv3032->regmap = devm_regmap_init_i2c(client, ®map_config); | |
853 | if (IS_ERR(rv3032->regmap)) | |
854 | return PTR_ERR(rv3032->regmap); | |
855 | ||
856 | i2c_set_clientdata(client, rv3032); | |
857 | ||
858 | ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status); | |
859 | if (ret < 0) | |
860 | return ret; | |
861 | ||
862 | rv3032->rtc = devm_rtc_allocate_device(&client->dev); | |
863 | if (IS_ERR(rv3032->rtc)) | |
864 | return PTR_ERR(rv3032->rtc); | |
865 | ||
866 | if (client->irq > 0) { | |
867 | ret = devm_request_threaded_irq(&client->dev, client->irq, | |
868 | NULL, rv3032_handle_irq, | |
869 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
870 | "rv3032", rv3032); | |
871 | if (ret) { | |
872 | dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); | |
873 | client->irq = 0; | |
2eeaa532 AB |
874 | } |
875 | } | |
19588d50 AB |
876 | if (!client->irq) |
877 | clear_bit(RTC_FEATURE_ALARM, rv3032->rtc->features); | |
2eeaa532 AB |
878 | |
879 | ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1, | |
880 | RV3032_CTRL1_WADA, RV3032_CTRL1_WADA); | |
881 | if (ret) | |
882 | return ret; | |
883 | ||
884 | rv3032_trickle_charger_setup(&client->dev, rv3032); | |
885 | ||
886 | rv3032->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; | |
887 | rv3032->rtc->range_max = RTC_TIMESTAMP_END_2099; | |
888 | rv3032->rtc->ops = &rv3032_rtc_ops; | |
fdcfd854 | 889 | ret = devm_rtc_register_device(rv3032->rtc); |
2eeaa532 AB |
890 | if (ret) |
891 | return ret; | |
892 | ||
767fbb71 | 893 | nvmem_cfg.priv = rv3032->regmap; |
3a905c2d | 894 | devm_rtc_nvmem_register(rv3032->rtc, &nvmem_cfg); |
2eeaa532 | 895 | eeprom_cfg.priv = rv3032; |
3a905c2d | 896 | devm_rtc_nvmem_register(rv3032->rtc, &eeprom_cfg); |
2eeaa532 AB |
897 | |
898 | rv3032->rtc->max_user_freq = 1; | |
899 | ||
900 | #ifdef CONFIG_COMMON_CLK | |
901 | rv3032_clkout_register_clk(rv3032, client); | |
902 | #endif | |
903 | ||
904 | rv3032_hwmon_register(&client->dev); | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
94428ac9 | 909 | static const __maybe_unused struct of_device_id rv3032_of_match[] = { |
2eeaa532 AB |
910 | { .compatible = "microcrystal,rv3032", }, |
911 | { } | |
912 | }; | |
913 | MODULE_DEVICE_TABLE(of, rv3032_of_match); | |
914 | ||
915 | static struct i2c_driver rv3032_driver = { | |
916 | .driver = { | |
917 | .name = "rtc-rv3032", | |
918 | .of_match_table = of_match_ptr(rv3032_of_match), | |
919 | }, | |
920 | .probe_new = rv3032_probe, | |
921 | }; | |
922 | module_i2c_driver(rv3032_driver); | |
923 | ||
924 | MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); | |
925 | MODULE_DESCRIPTION("Micro Crystal RV3032 RTC driver"); | |
926 | MODULE_LICENSE("GPL v2"); |