Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7520b94d | 2 | /* |
37fc5e2c | 3 | * An I2C driver for Ricoh RS5C372, R2025S/D and RV5C38[67] RTCs |
7520b94d AZ |
4 | * |
5 | * Copyright (C) 2005 Pavel Mironchik <pmironchik@optifacio.net> | |
6 | * Copyright (C) 2006 Tower Technologies | |
0053dc0d | 7 | * Copyright (C) 2008 Paul Mundt |
7520b94d AZ |
8 | */ |
9 | ||
10 | #include <linux/i2c.h> | |
11 | #include <linux/rtc.h> | |
12 | #include <linux/bcd.h> | |
5a0e3ad6 | 13 | #include <linux/slab.h> |
2113852b | 14 | #include <linux/module.h> |
ff764b88 | 15 | #include <linux/of_device.h> |
7520b94d | 16 | |
cb26b572 DB |
17 | /* |
18 | * Ricoh has a family of I2C based RTCs, which differ only slightly from | |
19 | * each other. Differences center on pinout (e.g. how many interrupts, | |
20 | * output clock, etc) and how the control registers are used. The '372 | |
21 | * is significant only because that's the one this driver first supported. | |
22 | */ | |
7520b94d AZ |
23 | #define RS5C372_REG_SECS 0 |
24 | #define RS5C372_REG_MINS 1 | |
25 | #define RS5C372_REG_HOURS 2 | |
26 | #define RS5C372_REG_WDAY 3 | |
27 | #define RS5C372_REG_DAY 4 | |
28 | #define RS5C372_REG_MONTH 5 | |
29 | #define RS5C372_REG_YEAR 6 | |
30 | #define RS5C372_REG_TRIM 7 | |
cb26b572 DB |
31 | # define RS5C372_TRIM_XSL 0x80 |
32 | # define RS5C372_TRIM_MASK 0x7F | |
33 | ||
34 | #define RS5C_REG_ALARM_A_MIN 8 /* or ALARM_W */ | |
35 | #define RS5C_REG_ALARM_A_HOURS 9 | |
36 | #define RS5C_REG_ALARM_A_WDAY 10 | |
37 | ||
38 | #define RS5C_REG_ALARM_B_MIN 11 /* or ALARM_D */ | |
39 | #define RS5C_REG_ALARM_B_HOURS 12 | |
40 | #define RS5C_REG_ALARM_B_WDAY 13 /* (ALARM_B only) */ | |
41 | ||
42 | #define RS5C_REG_CTRL1 14 | |
43 | # define RS5C_CTRL1_AALE (1 << 7) /* or WALE */ | |
44 | # define RS5C_CTRL1_BALE (1 << 6) /* or DALE */ | |
45 | # define RV5C387_CTRL1_24 (1 << 5) | |
46 | # define RS5C372A_CTRL1_SL1 (1 << 5) | |
47 | # define RS5C_CTRL1_CT_MASK (7 << 0) | |
48 | # define RS5C_CTRL1_CT0 (0 << 0) /* no periodic irq */ | |
49 | # define RS5C_CTRL1_CT4 (4 << 0) /* 1 Hz level irq */ | |
50 | #define RS5C_REG_CTRL2 15 | |
51 | # define RS5C372_CTRL2_24 (1 << 5) | |
761acdda | 52 | # define RS5C_CTRL2_XSTP (1 << 4) /* only if !R2x2x */ |
09832dc0 OR |
53 | # define R2x2x_CTRL2_VDET (1 << 6) /* only if R2x2x */ |
54 | # define R2x2x_CTRL2_XSTP (1 << 5) /* only if R2x2x */ | |
55 | # define R2x2x_CTRL2_PON (1 << 4) /* only if R2x2x */ | |
cb26b572 DB |
56 | # define RS5C_CTRL2_CTFG (1 << 2) |
57 | # define RS5C_CTRL2_AAFG (1 << 1) /* or WAFG */ | |
58 | # define RS5C_CTRL2_BAFG (1 << 0) /* or DAFG */ | |
59 | ||
60 | ||
61 | /* to read (style 1) or write registers starting at R */ | |
62 | #define RS5C_ADDR(R) (((R) << 4) | 0) | |
63 | ||
64 | ||
65 | enum rtc_type { | |
66 | rtc_undef = 0, | |
37fc5e2c | 67 | rtc_r2025sd, |
550fcb8f | 68 | rtc_r2221tl, |
cb26b572 DB |
69 | rtc_rs5c372a, |
70 | rtc_rs5c372b, | |
71 | rtc_rv5c386, | |
72 | rtc_rv5c387a, | |
73 | }; | |
7520b94d | 74 | |
3760f736 | 75 | static const struct i2c_device_id rs5c372_id[] = { |
37fc5e2c | 76 | { "r2025sd", rtc_r2025sd }, |
550fcb8f | 77 | { "r2221tl", rtc_r2221tl }, |
3760f736 JD |
78 | { "rs5c372a", rtc_rs5c372a }, |
79 | { "rs5c372b", rtc_rs5c372b }, | |
80 | { "rv5c386", rtc_rv5c386 }, | |
81 | { "rv5c387a", rtc_rv5c387a }, | |
82 | { } | |
83 | }; | |
84 | MODULE_DEVICE_TABLE(i2c, rs5c372_id); | |
85 | ||
ff764b88 JMC |
86 | static const struct of_device_id rs5c372_of_match[] = { |
87 | { | |
88 | .compatible = "ricoh,r2025sd", | |
89 | .data = (void *)rtc_r2025sd | |
90 | }, | |
91 | { | |
92 | .compatible = "ricoh,r2221tl", | |
93 | .data = (void *)rtc_r2221tl | |
94 | }, | |
95 | { | |
96 | .compatible = "ricoh,rs5c372a", | |
97 | .data = (void *)rtc_rs5c372a | |
98 | }, | |
99 | { | |
100 | .compatible = "ricoh,rs5c372b", | |
101 | .data = (void *)rtc_rs5c372b | |
102 | }, | |
103 | { | |
104 | .compatible = "ricoh,rv5c386", | |
105 | .data = (void *)rtc_rv5c386 | |
106 | }, | |
107 | { | |
108 | .compatible = "ricoh,rv5c387a", | |
109 | .data = (void *)rtc_rv5c387a | |
110 | }, | |
111 | { } | |
112 | }; | |
113 | MODULE_DEVICE_TABLE(of, rs5c372_of_match); | |
114 | ||
cb26b572 DB |
115 | /* REVISIT: this assumes that: |
116 | * - we're in the 21st century, so it's safe to ignore the century | |
117 | * bit for rv5c38[67] (REG_MONTH bit 7); | |
118 | * - we should use ALARM_A not ALARM_B (may be wrong on some boards) | |
119 | */ | |
120 | struct rs5c372 { | |
121 | struct i2c_client *client; | |
122 | struct rtc_device *rtc; | |
123 | enum rtc_type type; | |
124 | unsigned time24:1; | |
125 | unsigned has_irq:1; | |
0053dc0d | 126 | unsigned smbus:1; |
cb26b572 DB |
127 | char buf[17]; |
128 | char *regs; | |
cb26b572 | 129 | }; |
7520b94d | 130 | |
cb26b572 DB |
131 | static int rs5c_get_regs(struct rs5c372 *rs5c) |
132 | { | |
133 | struct i2c_client *client = rs5c->client; | |
134 | struct i2c_msg msgs[] = { | |
a606757f S |
135 | { |
136 | .addr = client->addr, | |
137 | .flags = I2C_M_RD, | |
138 | .len = sizeof(rs5c->buf), | |
139 | .buf = rs5c->buf | |
140 | }, | |
cb26b572 DB |
141 | }; |
142 | ||
143 | /* This implements the third reading method from the datasheet, using | |
144 | * an internal address that's reset after each transaction (by STOP) | |
145 | * to 0x0f ... so we read extra registers, and skip the first one. | |
146 | * | |
147 | * The first method doesn't work with the iop3xx adapter driver, on at | |
148 | * least 80219 chips; this works around that bug. | |
0053dc0d PM |
149 | * |
150 | * The third method on the other hand doesn't work for the SMBus-only | |
151 | * configurations, so we use the the first method there, stripping off | |
152 | * the extra register in the process. | |
cb26b572 | 153 | */ |
0053dc0d PM |
154 | if (rs5c->smbus) { |
155 | int addr = RS5C_ADDR(RS5C372_REG_SECS); | |
156 | int size = sizeof(rs5c->buf) - 1; | |
157 | ||
158 | if (i2c_smbus_read_i2c_block_data(client, addr, size, | |
159 | rs5c->buf + 1) != size) { | |
160 | dev_warn(&client->dev, "can't read registers\n"); | |
161 | return -EIO; | |
162 | } | |
163 | } else { | |
164 | if ((i2c_transfer(client->adapter, msgs, 1)) != 1) { | |
165 | dev_warn(&client->dev, "can't read registers\n"); | |
166 | return -EIO; | |
167 | } | |
cb26b572 | 168 | } |
7520b94d | 169 | |
cb26b572 | 170 | dev_dbg(&client->dev, |
b513e522 AS |
171 | "%3ph (%02x) %3ph (%02x), %3ph, %3ph; %02x %02x\n", |
172 | rs5c->regs + 0, rs5c->regs[3], | |
173 | rs5c->regs + 4, rs5c->regs[7], | |
174 | rs5c->regs + 8, rs5c->regs + 11, | |
175 | rs5c->regs[14], rs5c->regs[15]); | |
7520b94d | 176 | |
cb26b572 DB |
177 | return 0; |
178 | } | |
c6f24f99 | 179 | |
cb26b572 DB |
180 | static unsigned rs5c_reg2hr(struct rs5c372 *rs5c, unsigned reg) |
181 | { | |
182 | unsigned hour; | |
7520b94d | 183 | |
cb26b572 | 184 | if (rs5c->time24) |
fe20ba70 | 185 | return bcd2bin(reg & 0x3f); |
cb26b572 | 186 | |
fe20ba70 | 187 | hour = bcd2bin(reg & 0x1f); |
cb26b572 DB |
188 | if (hour == 12) |
189 | hour = 0; | |
190 | if (reg & 0x20) | |
191 | hour += 12; | |
192 | return hour; | |
193 | } | |
194 | ||
195 | static unsigned rs5c_hr2reg(struct rs5c372 *rs5c, unsigned hour) | |
7520b94d | 196 | { |
cb26b572 | 197 | if (rs5c->time24) |
fe20ba70 | 198 | return bin2bcd(hour); |
cb26b572 DB |
199 | |
200 | if (hour > 12) | |
fe20ba70 | 201 | return 0x20 | bin2bcd(hour - 12); |
cb26b572 | 202 | if (hour == 12) |
fe20ba70 | 203 | return 0x20 | bin2bcd(12); |
cb26b572 | 204 | if (hour == 0) |
fe20ba70 AB |
205 | return bin2bcd(12); |
206 | return bin2bcd(hour); | |
cb26b572 | 207 | } |
7520b94d | 208 | |
44db5c92 | 209 | static int rs5c372_rtc_read_time(struct device *dev, struct rtc_time *tm) |
cb26b572 | 210 | { |
44db5c92 | 211 | struct i2c_client *client = to_i2c_client(dev); |
cb26b572 DB |
212 | struct rs5c372 *rs5c = i2c_get_clientdata(client); |
213 | int status = rs5c_get_regs(rs5c); | |
09832dc0 | 214 | unsigned char ctrl2 = rs5c->regs[RS5C_REG_CTRL2]; |
c6f24f99 | 215 | |
cb26b572 DB |
216 | if (status < 0) |
217 | return status; | |
7520b94d | 218 | |
09832dc0 OR |
219 | switch (rs5c->type) { |
220 | case rtc_r2025sd: | |
221 | case rtc_r2221tl: | |
222 | if ((rs5c->type == rtc_r2025sd && !(ctrl2 & R2x2x_CTRL2_XSTP)) || | |
223 | (rs5c->type == rtc_r2221tl && (ctrl2 & R2x2x_CTRL2_XSTP))) { | |
224 | dev_warn(&client->dev, "rtc oscillator interruption detected. Please reset the rtc clock.\n"); | |
225 | return -EINVAL; | |
226 | } | |
227 | break; | |
228 | default: | |
229 | if (ctrl2 & RS5C_CTRL2_XSTP) { | |
230 | dev_warn(&client->dev, "rtc oscillator interruption detected. Please reset the rtc clock.\n"); | |
231 | return -EINVAL; | |
232 | } | |
233 | } | |
234 | ||
fe20ba70 AB |
235 | tm->tm_sec = bcd2bin(rs5c->regs[RS5C372_REG_SECS] & 0x7f); |
236 | tm->tm_min = bcd2bin(rs5c->regs[RS5C372_REG_MINS] & 0x7f); | |
cb26b572 | 237 | tm->tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C372_REG_HOURS]); |
7520b94d | 238 | |
fe20ba70 AB |
239 | tm->tm_wday = bcd2bin(rs5c->regs[RS5C372_REG_WDAY] & 0x07); |
240 | tm->tm_mday = bcd2bin(rs5c->regs[RS5C372_REG_DAY] & 0x3f); | |
7520b94d AZ |
241 | |
242 | /* tm->tm_mon is zero-based */ | |
fe20ba70 | 243 | tm->tm_mon = bcd2bin(rs5c->regs[RS5C372_REG_MONTH] & 0x1f) - 1; |
7520b94d AZ |
244 | |
245 | /* year is 1900 + tm->tm_year */ | |
fe20ba70 | 246 | tm->tm_year = bcd2bin(rs5c->regs[RS5C372_REG_YEAR]) + 100; |
7520b94d AZ |
247 | |
248 | dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, " | |
249 | "mday=%d, mon=%d, year=%d, wday=%d\n", | |
2a4e2b87 | 250 | __func__, |
7520b94d AZ |
251 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
252 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); | |
253 | ||
57f454fb | 254 | return 0; |
7520b94d AZ |
255 | } |
256 | ||
44db5c92 | 257 | static int rs5c372_rtc_set_time(struct device *dev, struct rtc_time *tm) |
7520b94d | 258 | { |
44db5c92 | 259 | struct i2c_client *client = to_i2c_client(dev); |
cb26b572 | 260 | struct rs5c372 *rs5c = i2c_get_clientdata(client); |
11836494 | 261 | unsigned char buf[7]; |
09832dc0 | 262 | unsigned char ctrl2; |
0053dc0d | 263 | int addr; |
7520b94d | 264 | |
cb26b572 | 265 | dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d " |
7520b94d | 266 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 267 | __func__, |
cb26b572 | 268 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
7520b94d AZ |
269 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); |
270 | ||
0053dc0d | 271 | addr = RS5C_ADDR(RS5C372_REG_SECS); |
fe20ba70 AB |
272 | buf[0] = bin2bcd(tm->tm_sec); |
273 | buf[1] = bin2bcd(tm->tm_min); | |
0053dc0d | 274 | buf[2] = rs5c_hr2reg(rs5c, tm->tm_hour); |
fe20ba70 AB |
275 | buf[3] = bin2bcd(tm->tm_wday); |
276 | buf[4] = bin2bcd(tm->tm_mday); | |
277 | buf[5] = bin2bcd(tm->tm_mon + 1); | |
278 | buf[6] = bin2bcd(tm->tm_year - 100); | |
7520b94d | 279 | |
0053dc0d | 280 | if (i2c_smbus_write_i2c_block_data(client, addr, sizeof(buf), buf) < 0) { |
09832dc0 OR |
281 | dev_dbg(&client->dev, "%s: write error in line %i\n", |
282 | __func__, __LINE__); | |
283 | return -EIO; | |
284 | } | |
285 | ||
286 | addr = RS5C_ADDR(RS5C_REG_CTRL2); | |
287 | ctrl2 = i2c_smbus_read_byte_data(client, addr); | |
288 | ||
289 | /* clear rtc warning bits */ | |
290 | switch (rs5c->type) { | |
291 | case rtc_r2025sd: | |
292 | case rtc_r2221tl: | |
293 | ctrl2 &= ~(R2x2x_CTRL2_VDET | R2x2x_CTRL2_PON); | |
294 | if (rs5c->type == rtc_r2025sd) | |
295 | ctrl2 |= R2x2x_CTRL2_XSTP; | |
296 | else | |
297 | ctrl2 &= ~R2x2x_CTRL2_XSTP; | |
298 | break; | |
299 | default: | |
300 | ctrl2 &= ~RS5C_CTRL2_XSTP; | |
301 | break; | |
302 | } | |
303 | ||
304 | if (i2c_smbus_write_byte_data(client, addr, ctrl2) < 0) { | |
305 | dev_dbg(&client->dev, "%s: write error in line %i\n", | |
306 | __func__, __LINE__); | |
7520b94d AZ |
307 | return -EIO; |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
6fca3fc5 | 313 | #if IS_ENABLED(CONFIG_RTC_INTF_PROC) |
cb26b572 DB |
314 | #define NEED_TRIM |
315 | #endif | |
316 | ||
6fca3fc5 | 317 | #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS) |
cb26b572 DB |
318 | #define NEED_TRIM |
319 | #endif | |
320 | ||
321 | #ifdef NEED_TRIM | |
7520b94d AZ |
322 | static int rs5c372_get_trim(struct i2c_client *client, int *osc, int *trim) |
323 | { | |
c6f24f99 | 324 | struct rs5c372 *rs5c372 = i2c_get_clientdata(client); |
cb26b572 | 325 | u8 tmp = rs5c372->regs[RS5C372_REG_TRIM]; |
7520b94d | 326 | |
7520b94d | 327 | if (osc) |
c6f24f99 | 328 | *osc = (tmp & RS5C372_TRIM_XSL) ? 32000 : 32768; |
7520b94d | 329 | |
17ad78e5 | 330 | if (trim) { |
2a4e2b87 | 331 | dev_dbg(&client->dev, "%s: raw trim=%x\n", __func__, tmp); |
cb26b572 DB |
332 | tmp &= RS5C372_TRIM_MASK; |
333 | if (tmp & 0x3e) { | |
334 | int t = tmp & 0x3f; | |
335 | ||
336 | if (tmp & 0x40) | |
337 | t = (~t | (s8)0xc0) + 1; | |
338 | else | |
339 | t = t - 1; | |
340 | ||
341 | tmp = t * 2; | |
342 | } else | |
343 | tmp = 0; | |
344 | *trim = tmp; | |
17ad78e5 | 345 | } |
7520b94d AZ |
346 | |
347 | return 0; | |
348 | } | |
cb26b572 | 349 | #endif |
7520b94d | 350 | |
16380c15 JS |
351 | static int rs5c_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
352 | { | |
353 | struct i2c_client *client = to_i2c_client(dev); | |
354 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
355 | unsigned char buf; | |
356 | int status, addr; | |
357 | ||
358 | buf = rs5c->regs[RS5C_REG_CTRL1]; | |
359 | ||
360 | if (!rs5c->has_irq) | |
361 | return -EINVAL; | |
362 | ||
363 | status = rs5c_get_regs(rs5c); | |
364 | if (status < 0) | |
365 | return status; | |
366 | ||
367 | addr = RS5C_ADDR(RS5C_REG_CTRL1); | |
368 | if (enabled) | |
369 | buf |= RS5C_CTRL1_AALE; | |
370 | else | |
371 | buf &= ~RS5C_CTRL1_AALE; | |
372 | ||
373 | if (i2c_smbus_write_byte_data(client, addr, buf) < 0) { | |
0c6516ea | 374 | dev_warn(dev, "can't update alarm\n"); |
16380c15 JS |
375 | status = -EIO; |
376 | } else | |
377 | rs5c->regs[RS5C_REG_CTRL1] = buf; | |
378 | ||
379 | return status; | |
380 | } | |
381 | ||
382 | ||
cb26b572 DB |
383 | /* NOTE: Since RTC_WKALM_{RD,SET} were originally defined for EFI, |
384 | * which only exposes a polled programming interface; and since | |
385 | * these calls map directly to those EFI requests; we don't demand | |
386 | * we have an IRQ for this chip when we go through this API. | |
387 | * | |
388 | * The older x86_pc derived RTC_ALM_{READ,SET} calls require irqs | |
389 | * though, managed through RTC_AIE_{ON,OFF} requests. | |
390 | */ | |
391 | ||
392 | static int rs5c_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
393 | { | |
394 | struct i2c_client *client = to_i2c_client(dev); | |
395 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
396 | int status; | |
397 | ||
398 | status = rs5c_get_regs(rs5c); | |
399 | if (status < 0) | |
400 | return status; | |
401 | ||
402 | /* report alarm time */ | |
403 | t->time.tm_sec = 0; | |
fe20ba70 | 404 | t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f); |
cb26b572 | 405 | t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]); |
cb26b572 DB |
406 | |
407 | /* ... and status */ | |
408 | t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE); | |
409 | t->pending = !!(rs5c->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_AAFG); | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static int rs5c_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |
415 | { | |
416 | struct i2c_client *client = to_i2c_client(dev); | |
417 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
0053dc0d PM |
418 | int status, addr, i; |
419 | unsigned char buf[3]; | |
cb26b572 DB |
420 | |
421 | /* only handle up to 24 hours in the future, like RTC_ALM_SET */ | |
422 | if (t->time.tm_mday != -1 | |
423 | || t->time.tm_mon != -1 | |
424 | || t->time.tm_year != -1) | |
425 | return -EINVAL; | |
426 | ||
427 | /* REVISIT: round up tm_sec */ | |
428 | ||
429 | /* if needed, disable irq (clears pending status) */ | |
430 | status = rs5c_get_regs(rs5c); | |
431 | if (status < 0) | |
432 | return status; | |
433 | if (rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE) { | |
0053dc0d PM |
434 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
435 | buf[0] = rs5c->regs[RS5C_REG_CTRL1] & ~RS5C_CTRL1_AALE; | |
436 | if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) { | |
0c6516ea | 437 | dev_dbg(dev, "can't disable alarm\n"); |
cb26b572 DB |
438 | return -EIO; |
439 | } | |
0053dc0d | 440 | rs5c->regs[RS5C_REG_CTRL1] = buf[0]; |
cb26b572 DB |
441 | } |
442 | ||
443 | /* set alarm */ | |
fe20ba70 | 444 | buf[0] = bin2bcd(t->time.tm_min); |
0053dc0d PM |
445 | buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour); |
446 | buf[2] = 0x7f; /* any/all days */ | |
447 | ||
448 | for (i = 0; i < sizeof(buf); i++) { | |
449 | addr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i); | |
450 | if (i2c_smbus_write_byte_data(client, addr, buf[i]) < 0) { | |
0c6516ea | 451 | dev_dbg(dev, "can't set alarm time\n"); |
0053dc0d PM |
452 | return -EIO; |
453 | } | |
cb26b572 DB |
454 | } |
455 | ||
456 | /* ... and maybe enable its irq */ | |
457 | if (t->enabled) { | |
0053dc0d PM |
458 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
459 | buf[0] = rs5c->regs[RS5C_REG_CTRL1] | RS5C_CTRL1_AALE; | |
460 | if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) | |
0c6516ea | 461 | dev_warn(dev, "can't enable alarm\n"); |
0053dc0d | 462 | rs5c->regs[RS5C_REG_CTRL1] = buf[0]; |
cb26b572 DB |
463 | } |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
6fca3fc5 | 468 | #if IS_ENABLED(CONFIG_RTC_INTF_PROC) |
cb26b572 | 469 | |
7520b94d AZ |
470 | static int rs5c372_rtc_proc(struct device *dev, struct seq_file *seq) |
471 | { | |
472 | int err, osc, trim; | |
473 | ||
adfb4341 AZ |
474 | err = rs5c372_get_trim(to_i2c_client(dev), &osc, &trim); |
475 | if (err == 0) { | |
cb26b572 DB |
476 | seq_printf(seq, "crystal\t\t: %d.%03d KHz\n", |
477 | osc / 1000, osc % 1000); | |
478 | seq_printf(seq, "trim\t\t: %d\n", trim); | |
7520b94d AZ |
479 | } |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
cb26b572 DB |
484 | #else |
485 | #define rs5c372_rtc_proc NULL | |
486 | #endif | |
487 | ||
ff8371ac | 488 | static const struct rtc_class_ops rs5c372_rtc_ops = { |
7520b94d AZ |
489 | .proc = rs5c372_rtc_proc, |
490 | .read_time = rs5c372_rtc_read_time, | |
491 | .set_time = rs5c372_rtc_set_time, | |
cb26b572 DB |
492 | .read_alarm = rs5c_read_alarm, |
493 | .set_alarm = rs5c_set_alarm, | |
16380c15 | 494 | .alarm_irq_enable = rs5c_rtc_alarm_irq_enable, |
7520b94d AZ |
495 | }; |
496 | ||
6fca3fc5 | 497 | #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS) |
cb26b572 | 498 | |
7520b94d AZ |
499 | static ssize_t rs5c372_sysfs_show_trim(struct device *dev, |
500 | struct device_attribute *attr, char *buf) | |
501 | { | |
82896072 | 502 | int err, trim; |
7520b94d | 503 | |
82896072 AZ |
504 | err = rs5c372_get_trim(to_i2c_client(dev), NULL, &trim); |
505 | if (err) | |
506 | return err; | |
7520b94d | 507 | |
cb26b572 | 508 | return sprintf(buf, "%d\n", trim); |
7520b94d AZ |
509 | } |
510 | static DEVICE_ATTR(trim, S_IRUGO, rs5c372_sysfs_show_trim, NULL); | |
511 | ||
512 | static ssize_t rs5c372_sysfs_show_osc(struct device *dev, | |
513 | struct device_attribute *attr, char *buf) | |
514 | { | |
82896072 | 515 | int err, osc; |
7520b94d | 516 | |
82896072 AZ |
517 | err = rs5c372_get_trim(to_i2c_client(dev), &osc, NULL); |
518 | if (err) | |
519 | return err; | |
7520b94d | 520 | |
82896072 | 521 | return sprintf(buf, "%d.%03d KHz\n", osc / 1000, osc % 1000); |
7520b94d AZ |
522 | } |
523 | static DEVICE_ATTR(osc, S_IRUGO, rs5c372_sysfs_show_osc, NULL); | |
524 | ||
cb26b572 | 525 | static int rs5c_sysfs_register(struct device *dev) |
7520b94d | 526 | { |
cb26b572 DB |
527 | int err; |
528 | ||
529 | err = device_create_file(dev, &dev_attr_trim); | |
530 | if (err) | |
531 | return err; | |
532 | err = device_create_file(dev, &dev_attr_osc); | |
533 | if (err) | |
534 | device_remove_file(dev, &dev_attr_trim); | |
535 | ||
536 | return err; | |
537 | } | |
538 | ||
d815461c DB |
539 | static void rs5c_sysfs_unregister(struct device *dev) |
540 | { | |
541 | device_remove_file(dev, &dev_attr_trim); | |
542 | device_remove_file(dev, &dev_attr_osc); | |
543 | } | |
544 | ||
cb26b572 DB |
545 | #else |
546 | static int rs5c_sysfs_register(struct device *dev) | |
547 | { | |
548 | return 0; | |
7520b94d | 549 | } |
d815461c DB |
550 | |
551 | static void rs5c_sysfs_unregister(struct device *dev) | |
552 | { | |
553 | /* nothing */ | |
554 | } | |
cb26b572 DB |
555 | #endif /* SYSFS */ |
556 | ||
557 | static struct i2c_driver rs5c372_driver; | |
7520b94d | 558 | |
0053dc0d PM |
559 | static int rs5c_oscillator_setup(struct rs5c372 *rs5c372) |
560 | { | |
561 | unsigned char buf[2]; | |
562 | int addr, i, ret = 0; | |
563 | ||
761acdda OR |
564 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
565 | buf[0] = rs5c372->regs[RS5C_REG_CTRL1]; | |
566 | buf[1] = rs5c372->regs[RS5C_REG_CTRL2]; | |
567 | ||
761acdda OR |
568 | switch (rs5c372->type) { |
569 | case rtc_r2025sd: | |
570 | if (buf[1] & R2x2x_CTRL2_XSTP) | |
37fc5e2c | 571 | return ret; |
761acdda OR |
572 | break; |
573 | case rtc_r2221tl: | |
574 | if (!(buf[1] & R2x2x_CTRL2_XSTP)) | |
575 | return ret; | |
761acdda | 576 | break; |
761acdda OR |
577 | default: |
578 | if (!(buf[1] & RS5C_CTRL2_XSTP)) | |
37fc5e2c | 579 | return ret; |
761acdda | 580 | break; |
37fc5e2c | 581 | } |
0053dc0d | 582 | |
0053dc0d PM |
583 | /* use 24hr mode */ |
584 | switch (rs5c372->type) { | |
585 | case rtc_rs5c372a: | |
586 | case rtc_rs5c372b: | |
587 | buf[1] |= RS5C372_CTRL2_24; | |
588 | rs5c372->time24 = 1; | |
589 | break; | |
37fc5e2c | 590 | case rtc_r2025sd: |
550fcb8f | 591 | case rtc_r2221tl: |
0053dc0d PM |
592 | case rtc_rv5c386: |
593 | case rtc_rv5c387a: | |
594 | buf[0] |= RV5C387_CTRL1_24; | |
595 | rs5c372->time24 = 1; | |
596 | break; | |
597 | default: | |
598 | /* impossible */ | |
599 | break; | |
600 | } | |
601 | ||
602 | for (i = 0; i < sizeof(buf); i++) { | |
603 | addr = RS5C_ADDR(RS5C_REG_CTRL1 + i); | |
604 | ret = i2c_smbus_write_byte_data(rs5c372->client, addr, buf[i]); | |
605 | if (unlikely(ret < 0)) | |
606 | return ret; | |
607 | } | |
608 | ||
609 | rs5c372->regs[RS5C_REG_CTRL1] = buf[0]; | |
610 | rs5c372->regs[RS5C_REG_CTRL2] = buf[1]; | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
d2653e92 JD |
615 | static int rs5c372_probe(struct i2c_client *client, |
616 | const struct i2c_device_id *id) | |
7520b94d AZ |
617 | { |
618 | int err = 0; | |
0053dc0d | 619 | int smbus_mode = 0; |
c6f24f99 | 620 | struct rs5c372 *rs5c372; |
7520b94d | 621 | |
2a4e2b87 | 622 | dev_dbg(&client->dev, "%s\n", __func__); |
7520b94d | 623 | |
0053dc0d PM |
624 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | |
625 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) { | |
626 | /* | |
627 | * If we don't have any master mode adapter, try breaking | |
628 | * it down in to the barest of capabilities. | |
629 | */ | |
630 | if (i2c_check_functionality(client->adapter, | |
631 | I2C_FUNC_SMBUS_BYTE_DATA | | |
632 | I2C_FUNC_SMBUS_I2C_BLOCK)) | |
633 | smbus_mode = 1; | |
634 | else { | |
635 | /* Still no good, give up */ | |
636 | err = -ENODEV; | |
637 | goto exit; | |
638 | } | |
7520b94d AZ |
639 | } |
640 | ||
b8a4b4e2 JH |
641 | rs5c372 = devm_kzalloc(&client->dev, sizeof(struct rs5c372), |
642 | GFP_KERNEL); | |
643 | if (!rs5c372) { | |
7520b94d AZ |
644 | err = -ENOMEM; |
645 | goto exit; | |
646 | } | |
cb26b572 | 647 | |
cb26b572 | 648 | rs5c372->client = client; |
c6f24f99 | 649 | i2c_set_clientdata(client, rs5c372); |
ff764b88 JMC |
650 | if (client->dev.of_node) |
651 | rs5c372->type = (enum rtc_type) | |
652 | of_device_get_match_data(&client->dev); | |
653 | else | |
654 | rs5c372->type = id->driver_data; | |
c6f24f99 | 655 | |
e2bfe342 PM |
656 | /* we read registers 0x0f then 0x00-0x0f; skip the first one */ |
657 | rs5c372->regs = &rs5c372->buf[1]; | |
0053dc0d | 658 | rs5c372->smbus = smbus_mode; |
e2bfe342 | 659 | |
cb26b572 DB |
660 | err = rs5c_get_regs(rs5c372); |
661 | if (err < 0) | |
b8a4b4e2 | 662 | goto exit; |
cb26b572 | 663 | |
cb26b572 DB |
664 | /* clock may be set for am/pm or 24 hr time */ |
665 | switch (rs5c372->type) { | |
666 | case rtc_rs5c372a: | |
667 | case rtc_rs5c372b: | |
668 | /* alarm uses ALARM_A; and nINTRA on 372a, nINTR on 372b. | |
669 | * so does periodic irq, except some 327a modes. | |
670 | */ | |
671 | if (rs5c372->regs[RS5C_REG_CTRL2] & RS5C372_CTRL2_24) | |
672 | rs5c372->time24 = 1; | |
673 | break; | |
37fc5e2c | 674 | case rtc_r2025sd: |
550fcb8f | 675 | case rtc_r2221tl: |
cb26b572 DB |
676 | case rtc_rv5c386: |
677 | case rtc_rv5c387a: | |
678 | if (rs5c372->regs[RS5C_REG_CTRL1] & RV5C387_CTRL1_24) | |
679 | rs5c372->time24 = 1; | |
680 | /* alarm uses ALARM_W; and nINTRB for alarm and periodic | |
681 | * irq, on both 386 and 387 | |
682 | */ | |
683 | break; | |
684 | default: | |
685 | dev_err(&client->dev, "unknown RTC type\n"); | |
b8a4b4e2 | 686 | goto exit; |
cb26b572 DB |
687 | } |
688 | ||
689 | /* if the oscillator lost power and no other software (like | |
690 | * the bootloader) set it up, do it here. | |
37fc5e2c PM |
691 | * |
692 | * The R2025S/D does this a little differently than the other | |
693 | * parts, so we special case that.. | |
cb26b572 | 694 | */ |
0053dc0d PM |
695 | err = rs5c_oscillator_setup(rs5c372); |
696 | if (unlikely(err < 0)) { | |
697 | dev_err(&client->dev, "setup error\n"); | |
b8a4b4e2 | 698 | goto exit; |
cb26b572 DB |
699 | } |
700 | ||
fa569113 | 701 | dev_info(&client->dev, "%s found, %s\n", |
cb26b572 | 702 | ({ char *s; switch (rs5c372->type) { |
37fc5e2c | 703 | case rtc_r2025sd: s = "r2025sd"; break; |
550fcb8f | 704 | case rtc_r2221tl: s = "r2221tl"; break; |
cb26b572 DB |
705 | case rtc_rs5c372a: s = "rs5c372a"; break; |
706 | case rtc_rs5c372b: s = "rs5c372b"; break; | |
707 | case rtc_rv5c386: s = "rv5c386"; break; | |
708 | case rtc_rv5c387a: s = "rv5c387a"; break; | |
709 | default: s = "chip"; break; | |
710 | }; s;}), | |
711 | rs5c372->time24 ? "24hr" : "am/pm" | |
712 | ); | |
713 | ||
d815461c | 714 | /* REVISIT use client->irq to register alarm irq ... */ |
b8a4b4e2 JH |
715 | rs5c372->rtc = devm_rtc_device_register(&client->dev, |
716 | rs5c372_driver.driver.name, | |
717 | &rs5c372_rtc_ops, THIS_MODULE); | |
7520b94d | 718 | |
c6f24f99 RV |
719 | if (IS_ERR(rs5c372->rtc)) { |
720 | err = PTR_ERR(rs5c372->rtc); | |
b8a4b4e2 | 721 | goto exit; |
7520b94d AZ |
722 | } |
723 | ||
cb26b572 | 724 | err = rs5c_sysfs_register(&client->dev); |
c6f24f99 | 725 | if (err) |
b8a4b4e2 | 726 | goto exit; |
7520b94d AZ |
727 | |
728 | return 0; | |
729 | ||
7520b94d AZ |
730 | exit: |
731 | return err; | |
732 | } | |
733 | ||
d815461c | 734 | static int rs5c372_remove(struct i2c_client *client) |
cb26b572 | 735 | { |
d815461c | 736 | rs5c_sysfs_unregister(&client->dev); |
7520b94d AZ |
737 | return 0; |
738 | } | |
739 | ||
cb26b572 DB |
740 | static struct i2c_driver rs5c372_driver = { |
741 | .driver = { | |
742 | .name = "rtc-rs5c372", | |
ff764b88 | 743 | .of_match_table = of_match_ptr(rs5c372_of_match), |
cb26b572 | 744 | }, |
d815461c DB |
745 | .probe = rs5c372_probe, |
746 | .remove = rs5c372_remove, | |
3760f736 | 747 | .id_table = rs5c372_id, |
cb26b572 DB |
748 | }; |
749 | ||
0abc9201 | 750 | module_i2c_driver(rs5c372_driver); |
7520b94d AZ |
751 | |
752 | MODULE_AUTHOR( | |
753 | "Pavel Mironchik <pmironchik@optifacio.net>, " | |
0053dc0d PM |
754 | "Alessandro Zummo <a.zummo@towertech.it>, " |
755 | "Paul Mundt <lethal@linux-sh.org>"); | |
7520b94d AZ |
756 | MODULE_DESCRIPTION("Ricoh RS5C372 RTC driver"); |
757 | MODULE_LICENSE("GPL"); |