[linux-2.6-block.git] / drivers / rtc / rtc-pxa.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Real Time Clock interface for XScale PXA27x and PXA3xx
 *
 * Copyright (C) 2008 Robert Jarzmik
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include <mach/hardware.h>

#include "rtc-sa1100.h"

#define RTC_DEF_DIVIDER		(32768 - 1)
#define RTC_DEF_TRIM		0
#define MAXFREQ_PERIODIC	1000

/*
 * PXA Registers and bits definitions
 */
#define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
#define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
#define RTSR_PIAL	(1 << 13)	/* Periodic interrupt detected */
#define RTSR_SWALE2	(1 << 11)	/* RTC stopwatch alarm2 enable */
#define RTSR_SWAL2	(1 << 10)	/* RTC stopwatch alarm2 detected */
#define RTSR_SWALE1	(1 << 9)	/* RTC stopwatch alarm1 enable */
#define RTSR_SWAL1	(1 << 8)	/* RTC stopwatch alarm1 detected */
#define RTSR_RDALE2	(1 << 7)	/* RTC alarm2 enable */
#define RTSR_RDAL2	(1 << 6)	/* RTC alarm2 detected */
#define RTSR_RDALE1	(1 << 5)	/* RTC alarm1 enable */
#define RTSR_RDAL1	(1 << 4)	/* RTC alarm1 detected */
#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
#define RTSR_TRIG_MASK	(RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
			 | RTSR_SWAL1 | RTSR_SWAL2)
#define RYxR_YEAR_S	9
#define RYxR_YEAR_MASK	(0xfff << RYxR_YEAR_S)
#define RYxR_MONTH_S	5
#define RYxR_MONTH_MASK	(0xf << RYxR_MONTH_S)
#define RYxR_DAY_MASK	0x1f
#define RDxR_WOM_S     20
#define RDxR_WOM_MASK  (0x7 << RDxR_WOM_S)
#define RDxR_DOW_S     17
#define RDxR_DOW_MASK  (0x7 << RDxR_DOW_S)
#define RDxR_HOUR_S	12
#define RDxR_HOUR_MASK	(0x1f << RDxR_HOUR_S)
#define RDxR_MIN_S	6
#define RDxR_MIN_MASK	(0x3f << RDxR_MIN_S)
#define RDxR_SEC_MASK	0x3f

#define RTSR		0x08
#define RTTR		0x0c
#define RDCR		0x10
#define RYCR		0x14
#define RDAR1		0x18
#define RYAR1		0x1c
#define RTCPICR		0x34
#define PIAR		0x38

#define rtc_readl(pxa_rtc, reg)	\
	__raw_readl((pxa_rtc)->base + (reg))
#define rtc_writel(pxa_rtc, reg, value)	\
	__raw_writel((value), (pxa_rtc)->base + (reg))

struct pxa_rtc {
	struct sa1100_rtc sa1100_rtc;
	struct resource	*ress;
	void __iomem		*base;
	struct rtc_device	*rtc;
	spinlock_t		lock;		/* Protects this structure */
};


static u32 ryxr_calc(struct rtc_time *tm)
{
	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
		| ((tm->tm_mon + 1) << RYxR_MONTH_S)
		| tm->tm_mday;
}

static u32 rdxr_calc(struct rtc_time *tm)
{
	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
		| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
		| (tm->tm_hour << RDxR_HOUR_S)
		| (tm->tm_min << RDxR_MIN_S)
		| tm->tm_sec;
}

static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
{
	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
	tm->tm_mday = (rycr & RYxR_DAY_MASK);
	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
	tm->tm_sec = rdcr & RDxR_SEC_MASK;
}

static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
	u32 rtsr;

	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtsr &= ~RTSR_TRIG_MASK;
	rtsr &= ~mask;
	rtc_writel(pxa_rtc, RTSR, rtsr);
}

static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
	u32 rtsr;

	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtsr &= ~RTSR_TRIG_MASK;
	rtsr |= mask;
	rtc_writel(pxa_rtc, RTSR, rtsr);
}

static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
	u32 rtsr;
	unsigned long events = 0;

	spin_lock(&pxa_rtc->lock);

	/* clear interrupt sources */
	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtc_writel(pxa_rtc, RTSR, rtsr);

	/* temporary disable rtc interrupts */
	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);

	/* clear alarm interrupt if it has occurred */
	if (rtsr & RTSR_RDAL1)
		rtsr &= ~RTSR_RDALE1;

	/* update irq data & counter */
	if (rtsr & RTSR_RDAL1)
		events |= RTC_AF | RTC_IRQF;
	if (rtsr & RTSR_HZ)
		events |= RTC_UF | RTC_IRQF;
	if (rtsr & RTSR_PIAL)
		events |= RTC_PF | RTC_IRQF;

	rtc_update_irq(pxa_rtc->rtc, 1, events);

	/* enable back rtc interrupts */
	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);

	spin_unlock(&pxa_rtc->lock);
	return IRQ_HANDLED;
}

static int pxa_rtc_open(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	int ret;

	ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
			  "rtc 1Hz", dev);
	if (ret < 0) {
		dev_err(dev, "can't get irq %i, err %d\n",
			pxa_rtc->sa1100_rtc.irq_1hz, ret);
		goto err_irq_1Hz;
	}
	ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
			  "rtc Alrm", dev);
	if (ret < 0) {
		dev_err(dev, "can't get irq %i, err %d\n",
			pxa_rtc->sa1100_rtc.irq_alarm, ret);
		goto err_irq_Alrm;
	}

	return 0;

err_irq_Alrm:
	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
err_irq_1Hz:
	return ret;
}

static void pxa_rtc_release(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	spin_lock_irq(&pxa_rtc->lock);
	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
	spin_unlock_irq(&pxa_rtc->lock);

	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
	free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
}

static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	spin_lock_irq(&pxa_rtc->lock);

	if (enabled)
		rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
	else
		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);

	spin_unlock_irq(&pxa_rtc->lock);
	return 0;
}

static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rycr, rdcr;

	rycr = rtc_readl(pxa_rtc, RYCR);
	rdcr = rtc_readl(pxa_rtc, RDCR);

	tm_calc(rycr, rdcr, tm);
	return 0;
}

static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));

	return 0;
}

static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rtsr, ryar, rdar;

	ryar = rtc_readl(pxa_rtc, RYAR1);
	rdar = rtc_readl(pxa_rtc, RDAR1);
	tm_calc(ryar, rdar, &alrm->time);

	rtsr = rtc_readl(pxa_rtc, RTSR);
	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
	return 0;
}

static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rtsr;

	spin_lock_irq(&pxa_rtc->lock);

	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));

	rtsr = rtc_readl(pxa_rtc, RTSR);
	if (alrm->enabled)
		rtsr |= RTSR_RDALE1;
	else
		rtsr &= ~RTSR_RDALE1;
	rtc_writel(pxa_rtc, RTSR, rtsr);

	spin_unlock_irq(&pxa_rtc->lock);

	return 0;
}

static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
	seq_printf(seq, "update_IRQ\t: %s\n",
		   (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
	seq_printf(seq, "periodic_IRQ\t: %s\n",
		   (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));

	return 0;
}

static const struct rtc_class_ops pxa_rtc_ops = {
	.read_time = pxa_rtc_read_time,
	.set_time = pxa_rtc_set_time,
	.read_alarm = pxa_rtc_read_alarm,
	.set_alarm = pxa_rtc_set_alarm,
	.alarm_irq_enable = pxa_alarm_irq_enable,
	.proc = pxa_rtc_proc,
};

static int __init pxa_rtc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct pxa_rtc *pxa_rtc;
	struct sa1100_rtc *sa1100_rtc;
	int ret;

	pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
	if (!pxa_rtc)
		return -ENOMEM;
	sa1100_rtc = &pxa_rtc->sa1100_rtc;

	spin_lock_init(&pxa_rtc->lock);
	platform_set_drvdata(pdev, pxa_rtc);

	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!pxa_rtc->ress) {
		dev_err(dev, "No I/O memory resource defined\n");
		return -ENXIO;
	}

	sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
	if (sa1100_rtc->irq_1hz < 0)
		return -ENXIO;
	sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
	if (sa1100_rtc->irq_alarm < 0)
		return -ENXIO;

	sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(sa1100_rtc->rtc))
		return PTR_ERR(sa1100_rtc->rtc);

	pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
				resource_size(pxa_rtc->ress));
	if (!pxa_rtc->base) {
		dev_err(dev, "Unable to map pxa RTC I/O memory\n");
		return -ENOMEM;
	}

	pxa_rtc_open(dev);

	sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
	sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
	sa1100_rtc->rtar = pxa_rtc->base + 0x4;
	sa1100_rtc->rttr = pxa_rtc->base + 0xc;
	ret = sa1100_rtc_init(pdev, sa1100_rtc);
	if (ret) {
		dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
		return ret;
	}

	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);

	pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
						&pxa_rtc_ops, THIS_MODULE);
	if (IS_ERR(pxa_rtc->rtc)) {
		ret = PTR_ERR(pxa_rtc->rtc);
		dev_err(dev, "Failed to register RTC device -> %d\n", ret);
		return ret;
	}

	device_init_wakeup(dev, 1);

	return 0;
}

static int __exit pxa_rtc_remove(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;

	pxa_rtc_release(dev);
	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id pxa_rtc_dt_ids[] = {
	{ .compatible = "marvell,pxa-rtc" },
	{}
};
MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
#endif

#ifdef CONFIG_PM_SLEEP
static int pxa_rtc_suspend(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
	return 0;
}

static int pxa_rtc_resume(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);

static struct platform_driver pxa_rtc_driver = {
	.remove		= __exit_p(pxa_rtc_remove),
	.driver		= {
		.name	= "pxa-rtc",
		.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
		.pm	= &pxa_rtc_pm_ops,
	},
};

module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);

MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa-rtc");
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
dc944368 RJ	2	/*
	3	* Real Time Clock interface for XScale PXA27x and PXA3xx
	4	*
	5	* Copyright (C) 2008 Robert Jarzmik
dc944368 RJ	6	*/
dc944368 RJ	7
0417ce2a	8	#include <linux/init.h>
dc944368 RJ	9	#include <linux/platform_device.h>
	10	#include <linux/module.h>
	11	#include <linux/rtc.h>
	12	#include <linux/seq_file.h>
	13	#include <linux/interrupt.h>
0417ce2a	14	#include <linux/io.h>
5a0e3ad6	15	#include <linux/slab.h>
9020b7cc DM	16	#include <linux/of.h>
9020b7cc DM	17	#include <linux/of_device.h>
dc944368	18
4216d0bd AO	19	#include <mach/hardware.h>
4216d0bd AO	20
3cdf4ad9 RH	21	#include "rtc-sa1100.h"
3cdf4ad9 RH	22
dc944368 RJ	23	#define RTC_DEF_DIVIDER (32768 - 1)
	24	#define RTC_DEF_TRIM 0
	25	#define MAXFREQ_PERIODIC 1000
	26
	27	/*
	28	* PXA Registers and bits definitions
	29	*/
	30	#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
	31	#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
	32	#define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
	33	#define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
	34	#define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
	35	#define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
	36	#define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
	37	#define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
	38	#define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
	39	#define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
	40	#define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
	41	#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
	42	#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
	43	#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
	44	#define RTSR_AL (1 << 0) /* RTC alarm detected */
	45	#define RTSR_TRIG_MASK (RTSR_AL \| RTSR_HZ \| RTSR_RDAL1 \| RTSR_RDAL2\
	46	\| RTSR_SWAL1 \| RTSR_SWAL2)
	47	#define RYxR_YEAR_S 9
	48	#define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
	49	#define RYxR_MONTH_S 5
	50	#define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
	51	#define RYxR_DAY_MASK 0x1f
c4243de7 LS	52	#define RDxR_WOM_S 20
	53	#define RDxR_WOM_MASK (0x7 << RDxR_WOM_S)
	54	#define RDxR_DOW_S 17
	55	#define RDxR_DOW_MASK (0x7 << RDxR_DOW_S)
dc944368 RJ	56	#define RDxR_HOUR_S 12
	57	#define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
	58	#define RDxR_MIN_S 6
	59	#define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
	60	#define RDxR_SEC_MASK 0x3f
	61
	62	#define RTSR 0x08
	63	#define RTTR 0x0c
	64	#define RDCR 0x10
	65	#define RYCR 0x14
	66	#define RDAR1 0x18
	67	#define RYAR1 0x1c
	68	#define RTCPICR 0x34
	69	#define PIAR 0x38
	70
	71	#define rtc_readl(pxa_rtc, reg) \
	72	__raw_readl((pxa_rtc)->base + (reg))
	73	#define rtc_writel(pxa_rtc, reg, value) \
	74	__raw_writel((value), (pxa_rtc)->base + (reg))
	75
	76	struct pxa_rtc {
3cdf4ad9	77	struct sa1100_rtc sa1100_rtc;
dc944368 RJ	78	struct resource *ress;
dc944368 RJ	79	void __iomem *base;
dc944368 RJ	80	struct rtc_device *rtc;
dc944368 RJ	81	spinlock_t lock; /* Protects this structure */
dc944368 RJ	82	};
dc944368 RJ	83
c4243de7	84
dc944368 RJ	85	static u32 ryxr_calc(struct rtc_time *tm)
	86	{
	87	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
	88	\| ((tm->tm_mon + 1) << RYxR_MONTH_S)
	89	\| tm->tm_mday;
	90	}
	91
	92	static u32 rdxr_calc(struct rtc_time *tm)
	93	{
c4243de7 LS	94	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
	95	\| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
	96	\| (tm->tm_hour << RDxR_HOUR_S)
	97	\| (tm->tm_min << RDxR_MIN_S)
dc944368 RJ	98	\| tm->tm_sec;
	99	}
	100
	101	static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
	102	{
	103	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
	104	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
	105	tm->tm_mday = (rycr & RYxR_DAY_MASK);
c4243de7	106	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
dc944368 RJ	107	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
	108	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
	109	tm->tm_sec = rdcr & RDxR_SEC_MASK;
	110	}
	111
	112	static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
	113	{
	114	u32 rtsr;
	115
	116	rtsr = rtc_readl(pxa_rtc, RTSR);
	117	rtsr &= ~RTSR_TRIG_MASK;
	118	rtsr &= ~mask;
	119	rtc_writel(pxa_rtc, RTSR, rtsr);
	120	}
	121
	122	static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
	123	{
	124	u32 rtsr;
	125
	126	rtsr = rtc_readl(pxa_rtc, RTSR);
	127	rtsr &= ~RTSR_TRIG_MASK;
	128	rtsr \|= mask;
	129	rtc_writel(pxa_rtc, RTSR, rtsr);
	130	}
	131
	132	static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
	133	{
527bd754	134	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
dc944368 RJ	135	u32 rtsr;
	136	unsigned long events = 0;
	137
	138	spin_lock(&pxa_rtc->lock);
	139
	140	/* clear interrupt sources */
	141	rtsr = rtc_readl(pxa_rtc, RTSR);
	142	rtc_writel(pxa_rtc, RTSR, rtsr);
	143
	144	/* temporary disable rtc interrupts */
	145	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 \| RTSR_PIALE \| RTSR_HZE);
	146
	147	/* clear alarm interrupt if it has occurred */
	148	if (rtsr & RTSR_RDAL1)
	149	rtsr &= ~RTSR_RDALE1;
	150
	151	/* update irq data & counter */
	152	if (rtsr & RTSR_RDAL1)
	153	events \|= RTC_AF \| RTC_IRQF;
	154	if (rtsr & RTSR_HZ)
	155	events \|= RTC_UF \| RTC_IRQF;
	156	if (rtsr & RTSR_PIAL)
	157	events \|= RTC_PF \| RTC_IRQF;
	158
	159	rtc_update_irq(pxa_rtc->rtc, 1, events);
	160
	161	/* enable back rtc interrupts */
	162	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
	163
	164	spin_unlock(&pxa_rtc->lock);
	165	return IRQ_HANDLED;
	166	}
	167
	168	static int pxa_rtc_open(struct device *dev)
	169	{
	170	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	171	int ret;
	172
3cdf4ad9	173	ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
dc944368 RJ	174	"rtc 1Hz", dev);
dc944368 RJ	175	if (ret < 0) {
3cdf4ad9 RH	176	dev_err(dev, "can't get irq %i, err %d\n",
3cdf4ad9 RH	177	pxa_rtc->sa1100_rtc.irq_1hz, ret);
dc944368 RJ	178	goto err_irq_1Hz;
dc944368 RJ	179	}
3cdf4ad9	180	ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
dc944368 RJ	181	"rtc Alrm", dev);
dc944368 RJ	182	if (ret < 0) {
3cdf4ad9 RH	183	dev_err(dev, "can't get irq %i, err %d\n",
3cdf4ad9 RH	184	pxa_rtc->sa1100_rtc.irq_alarm, ret);
dc944368 RJ	185	goto err_irq_Alrm;
	186	}
	187
	188	return 0;
	189
	190	err_irq_Alrm:
3cdf4ad9	191	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
dc944368 RJ	192	err_irq_1Hz:
	193	return ret;
	194	}
	195
	196	static void pxa_rtc_release(struct device *dev)
	197	{
	198	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	199
	200	spin_lock_irq(&pxa_rtc->lock);
	201	rtsr_clear_bits(pxa_rtc, RTSR_PIALE \| RTSR_RDALE1 \| RTSR_HZE);
	202	spin_unlock_irq(&pxa_rtc->lock);
	203
3cdf4ad9 RH	204	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
3cdf4ad9 RH	205	free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
dc944368 RJ	206	}
dc944368 RJ	207
93b1384f	208	static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
dc944368 RJ	209	{
dc944368 RJ	210	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368 RJ	211
dc944368 RJ	212	spin_lock_irq(&pxa_rtc->lock);
93b1384f WZ	213
93b1384f WZ	214	if (enabled)
dc944368	215	rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
93b1384f WZ	216	else
	217	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
	218
	219	spin_unlock_irq(&pxa_rtc->lock);
	220	return 0;
	221	}
	222
dc944368 RJ	223	static int pxa_rtc_read_time(struct device dev, struct rtc_time tm)
	224	{
	225	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	226	u32 rycr, rdcr;
	227
	228	rycr = rtc_readl(pxa_rtc, RYCR);
	229	rdcr = rtc_readl(pxa_rtc, RDCR);
	230
	231	tm_calc(rycr, rdcr, tm);
	232	return 0;
	233	}
	234
	235	static int pxa_rtc_set_time(struct device dev, struct rtc_time tm)
	236	{
	237	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	238
	239	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
	240	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
	241
	242	return 0;
	243	}
	244
	245	static int pxa_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	246	{
	247	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	248	u32 rtsr, ryar, rdar;
	249
	250	ryar = rtc_readl(pxa_rtc, RYAR1);
	251	rdar = rtc_readl(pxa_rtc, RDAR1);
	252	tm_calc(ryar, rdar, &alrm->time);
	253
	254	rtsr = rtc_readl(pxa_rtc, RTSR);
	255	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
	256	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
	257	return 0;
	258	}
	259
	260	static int pxa_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	261	{
	262	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	263	u32 rtsr;
	264
	265	spin_lock_irq(&pxa_rtc->lock);
	266
	267	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
	268	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
	269
	270	rtsr = rtc_readl(pxa_rtc, RTSR);
	271	if (alrm->enabled)
	272	rtsr \|= RTSR_RDALE1;
	273	else
	274	rtsr &= ~RTSR_RDALE1;
	275	rtc_writel(pxa_rtc, RTSR, rtsr);
	276
	277	spin_unlock_irq(&pxa_rtc->lock);
	278
	279	return 0;
	280	}
	281
	282	static int pxa_rtc_proc(struct device dev, struct seq_file seq)
	283	{
	284	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	285
	286	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
287	seq_printf(seq, "update_IRQ\t: %s\n",
288	(rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
289	seq_printf(seq, "periodic_IRQ\t: %s\n",
290	(rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
291	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
292
293	return 0;
294	}
295
296	static const struct rtc_class_ops pxa_rtc_ops = {
dc944368 RJ	297	.read_time = pxa_rtc_read_time,
	298	.set_time = pxa_rtc_set_time,
	299	.read_alarm = pxa_rtc_read_alarm,
	300	.set_alarm = pxa_rtc_set_alarm,
93b1384f	301	.alarm_irq_enable = pxa_alarm_irq_enable,
dc944368	302	.proc = pxa_rtc_proc,
dc944368 RJ	303	};
dc944368 RJ	304
0417ce2a	305	static int __init pxa_rtc_probe(struct platform_device *pdev)
dc944368 RJ	306	{
	307	struct device *dev = &pdev->dev;
	308	struct pxa_rtc *pxa_rtc;
3cdf4ad9	309	struct sa1100_rtc *sa1100_rtc;
dc944368	310	int ret;
dc944368	311
618c3003	312	pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
dc944368	313	if (!pxa_rtc)
0417ce2a	314	return -ENOMEM;
3cdf4ad9	315	sa1100_rtc = &pxa_rtc->sa1100_rtc;
0417ce2a AZ	316
	317	spin_lock_init(&pxa_rtc->lock);
	318	platform_set_drvdata(pdev, pxa_rtc);
dc944368	319
dc944368 RJ	320	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	321	if (!pxa_rtc->ress) {
	322	dev_err(dev, "No I/O memory resource defined\n");
618c3003	323	return -ENXIO;
dc944368 RJ	324	}
dc944368 RJ	325
3cdf4ad9	326	sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
faac9102	327	if (sa1100_rtc->irq_1hz < 0)
618c3003	328	return -ENXIO;
3cdf4ad9	329	sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
faac9102	330	if (sa1100_rtc->irq_alarm < 0)
618c3003	331	return -ENXIO;
56c0c529	332
34127b36 LB	333	sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
	334	if (IS_ERR(sa1100_rtc->rtc))
	335	return PTR_ERR(sa1100_rtc->rtc);
	336
618c3003	337	pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
0417ce2a	338	resource_size(pxa_rtc->ress));
dc944368	339	if (!pxa_rtc->base) {
618c3003 JH	340	dev_err(dev, "Unable to map pxa RTC I/O memory\n");
618c3003 JH	341	return -ENOMEM;
dc944368 RJ	342	}
dc944368 RJ	343
56c0c529 AB	344	pxa_rtc_open(dev);
56c0c529 AB	345
90d0ae8e RH	346	sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
	347	sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
	348	sa1100_rtc->rtar = pxa_rtc->base + 0x4;
	349	sa1100_rtc->rttr = pxa_rtc->base + 0xc;
3cdf4ad9	350	ret = sa1100_rtc_init(pdev, sa1100_rtc);
e4302aec	351	if (ret) {
3cdf4ad9 RH	352	dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
3cdf4ad9 RH	353	return ret;
dc944368 RJ	354	}
	355
	356	rtsr_clear_bits(pxa_rtc, RTSR_PIALE \| RTSR_RDALE1 \| RTSR_HZE);
0417ce2a	357
618c3003 JH	358	pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
618c3003 JH	359	&pxa_rtc_ops, THIS_MODULE);
0417ce2a	360	if (IS_ERR(pxa_rtc->rtc)) {
618c3003	361	ret = PTR_ERR(pxa_rtc->rtc);
0417ce2a	362	dev_err(dev, "Failed to register RTC device -> %d\n", ret);
618c3003	363	return ret;
0417ce2a AZ	364	}
0417ce2a AZ	365
dc944368 RJ	366	device_init_wakeup(dev, 1);
	367
	368	return 0;
dc944368 RJ	369	}
dc944368 RJ	370
0417ce2a	371	static int __exit pxa_rtc_remove(struct platform_device *pdev)
dc944368	372	{
a44802f8	373	struct device *dev = &pdev->dev;
dc944368	374
618c3003	375	pxa_rtc_release(dev);
dc944368 RJ	376	return 0;
	377	}
	378
9020b7cc	379	#ifdef CONFIG_OF
8b18daa1	380	static const struct of_device_id pxa_rtc_dt_ids[] = {
9020b7cc DM	381	{ .compatible = "marvell,pxa-rtc" },
	382	{}
	383	};
	384	MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
	385	#endif
	386
c5a40618	387	#ifdef CONFIG_PM_SLEEP
e6e698a4	388	static int pxa_rtc_suspend(struct device *dev)
dc944368	389	{
e6e698a4	390	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368	391
e6e698a4	392	if (device_may_wakeup(dev))
3cdf4ad9	393	enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
dc944368 RJ	394	return 0;
	395	}
	396
e6e698a4	397	static int pxa_rtc_resume(struct device *dev)
dc944368	398	{
e6e698a4	399	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368	400
e6e698a4	401	if (device_may_wakeup(dev))
3cdf4ad9	402	disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
dc944368 RJ	403	return 0;
dc944368 RJ	404	}
dc944368 RJ	405	#endif
dc944368 RJ	406
c5a40618 JH	407	static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
c5a40618 JH	408
dc944368	409	static struct platform_driver pxa_rtc_driver = {
dc944368	410	.remove = __exit_p(pxa_rtc_remove),
dc944368	411	.driver = {
e6e698a4	412	.name = "pxa-rtc",
9020b7cc	413	.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
e6e698a4	414	.pm = &pxa_rtc_pm_ops,
dc944368 RJ	415	},
	416	};
	417
7daba88e	418	module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
dc944368	419
57f63bc8	420	MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
dc944368 RJ	421	MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
	422	MODULE_LICENSE("GPL");
	423	MODULE_ALIAS("platform:pxa-rtc");