Commit | Line | Data |
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dc944368 RJ |
1 | /* |
2 | * Real Time Clock interface for XScale PXA27x and PXA3xx | |
3 | * | |
4 | * Copyright (C) 2008 Robert Jarzmik | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
0417ce2a | 22 | #include <linux/init.h> |
dc944368 RJ |
23 | #include <linux/platform_device.h> |
24 | #include <linux/module.h> | |
25 | #include <linux/rtc.h> | |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/interrupt.h> | |
0417ce2a | 28 | #include <linux/io.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
9020b7cc DM |
30 | #include <linux/of.h> |
31 | #include <linux/of_device.h> | |
dc944368 | 32 | |
4216d0bd AO |
33 | #include <mach/hardware.h> |
34 | ||
dc944368 RJ |
35 | #define TIMER_FREQ CLOCK_TICK_RATE |
36 | #define RTC_DEF_DIVIDER (32768 - 1) | |
37 | #define RTC_DEF_TRIM 0 | |
38 | #define MAXFREQ_PERIODIC 1000 | |
39 | ||
40 | /* | |
41 | * PXA Registers and bits definitions | |
42 | */ | |
43 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | |
44 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | |
45 | #define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */ | |
46 | #define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */ | |
47 | #define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */ | |
48 | #define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */ | |
49 | #define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */ | |
50 | #define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */ | |
51 | #define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */ | |
52 | #define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */ | |
53 | #define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */ | |
54 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | |
55 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | |
56 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | |
57 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | |
58 | #define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\ | |
59 | | RTSR_SWAL1 | RTSR_SWAL2) | |
60 | #define RYxR_YEAR_S 9 | |
61 | #define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S) | |
62 | #define RYxR_MONTH_S 5 | |
63 | #define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S) | |
64 | #define RYxR_DAY_MASK 0x1f | |
65 | #define RDxR_HOUR_S 12 | |
66 | #define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S) | |
67 | #define RDxR_MIN_S 6 | |
68 | #define RDxR_MIN_MASK (0x3f << RDxR_MIN_S) | |
69 | #define RDxR_SEC_MASK 0x3f | |
70 | ||
71 | #define RTSR 0x08 | |
72 | #define RTTR 0x0c | |
73 | #define RDCR 0x10 | |
74 | #define RYCR 0x14 | |
75 | #define RDAR1 0x18 | |
76 | #define RYAR1 0x1c | |
77 | #define RTCPICR 0x34 | |
78 | #define PIAR 0x38 | |
79 | ||
80 | #define rtc_readl(pxa_rtc, reg) \ | |
81 | __raw_readl((pxa_rtc)->base + (reg)) | |
82 | #define rtc_writel(pxa_rtc, reg, value) \ | |
83 | __raw_writel((value), (pxa_rtc)->base + (reg)) | |
84 | ||
85 | struct pxa_rtc { | |
86 | struct resource *ress; | |
87 | void __iomem *base; | |
88 | int irq_1Hz; | |
89 | int irq_Alrm; | |
90 | struct rtc_device *rtc; | |
91 | spinlock_t lock; /* Protects this structure */ | |
dc944368 RJ |
92 | }; |
93 | ||
94 | static u32 ryxr_calc(struct rtc_time *tm) | |
95 | { | |
96 | return ((tm->tm_year + 1900) << RYxR_YEAR_S) | |
97 | | ((tm->tm_mon + 1) << RYxR_MONTH_S) | |
98 | | tm->tm_mday; | |
99 | } | |
100 | ||
101 | static u32 rdxr_calc(struct rtc_time *tm) | |
102 | { | |
103 | return (tm->tm_hour << RDxR_HOUR_S) | (tm->tm_min << RDxR_MIN_S) | |
104 | | tm->tm_sec; | |
105 | } | |
106 | ||
107 | static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm) | |
108 | { | |
109 | tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900; | |
110 | tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1; | |
111 | tm->tm_mday = (rycr & RYxR_DAY_MASK); | |
112 | tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S; | |
113 | tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S; | |
114 | tm->tm_sec = rdcr & RDxR_SEC_MASK; | |
115 | } | |
116 | ||
117 | static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask) | |
118 | { | |
119 | u32 rtsr; | |
120 | ||
121 | rtsr = rtc_readl(pxa_rtc, RTSR); | |
122 | rtsr &= ~RTSR_TRIG_MASK; | |
123 | rtsr &= ~mask; | |
124 | rtc_writel(pxa_rtc, RTSR, rtsr); | |
125 | } | |
126 | ||
127 | static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask) | |
128 | { | |
129 | u32 rtsr; | |
130 | ||
131 | rtsr = rtc_readl(pxa_rtc, RTSR); | |
132 | rtsr &= ~RTSR_TRIG_MASK; | |
133 | rtsr |= mask; | |
134 | rtc_writel(pxa_rtc, RTSR, rtsr); | |
135 | } | |
136 | ||
137 | static irqreturn_t pxa_rtc_irq(int irq, void *dev_id) | |
138 | { | |
139 | struct platform_device *pdev = to_platform_device(dev_id); | |
140 | struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev); | |
141 | u32 rtsr; | |
142 | unsigned long events = 0; | |
143 | ||
144 | spin_lock(&pxa_rtc->lock); | |
145 | ||
146 | /* clear interrupt sources */ | |
147 | rtsr = rtc_readl(pxa_rtc, RTSR); | |
148 | rtc_writel(pxa_rtc, RTSR, rtsr); | |
149 | ||
150 | /* temporary disable rtc interrupts */ | |
151 | rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE); | |
152 | ||
153 | /* clear alarm interrupt if it has occurred */ | |
154 | if (rtsr & RTSR_RDAL1) | |
155 | rtsr &= ~RTSR_RDALE1; | |
156 | ||
157 | /* update irq data & counter */ | |
158 | if (rtsr & RTSR_RDAL1) | |
159 | events |= RTC_AF | RTC_IRQF; | |
160 | if (rtsr & RTSR_HZ) | |
161 | events |= RTC_UF | RTC_IRQF; | |
162 | if (rtsr & RTSR_PIAL) | |
163 | events |= RTC_PF | RTC_IRQF; | |
164 | ||
165 | rtc_update_irq(pxa_rtc->rtc, 1, events); | |
166 | ||
167 | /* enable back rtc interrupts */ | |
168 | rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK); | |
169 | ||
170 | spin_unlock(&pxa_rtc->lock); | |
171 | return IRQ_HANDLED; | |
172 | } | |
173 | ||
174 | static int pxa_rtc_open(struct device *dev) | |
175 | { | |
176 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
177 | int ret; | |
178 | ||
2f6e5f94 | 179 | ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, 0, |
dc944368 RJ |
180 | "rtc 1Hz", dev); |
181 | if (ret < 0) { | |
182 | dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz, | |
183 | ret); | |
184 | goto err_irq_1Hz; | |
185 | } | |
2f6e5f94 | 186 | ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, 0, |
dc944368 RJ |
187 | "rtc Alrm", dev); |
188 | if (ret < 0) { | |
189 | dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm, | |
190 | ret); | |
191 | goto err_irq_Alrm; | |
192 | } | |
193 | ||
194 | return 0; | |
195 | ||
196 | err_irq_Alrm: | |
197 | free_irq(pxa_rtc->irq_1Hz, dev); | |
198 | err_irq_1Hz: | |
199 | return ret; | |
200 | } | |
201 | ||
202 | static void pxa_rtc_release(struct device *dev) | |
203 | { | |
204 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
205 | ||
206 | spin_lock_irq(&pxa_rtc->lock); | |
207 | rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); | |
208 | spin_unlock_irq(&pxa_rtc->lock); | |
209 | ||
210 | free_irq(pxa_rtc->irq_Alrm, dev); | |
211 | free_irq(pxa_rtc->irq_1Hz, dev); | |
212 | } | |
213 | ||
93b1384f | 214 | static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled) |
dc944368 RJ |
215 | { |
216 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
dc944368 RJ |
217 | |
218 | spin_lock_irq(&pxa_rtc->lock); | |
93b1384f WZ |
219 | |
220 | if (enabled) | |
dc944368 | 221 | rtsr_set_bits(pxa_rtc, RTSR_RDALE1); |
93b1384f WZ |
222 | else |
223 | rtsr_clear_bits(pxa_rtc, RTSR_RDALE1); | |
224 | ||
225 | spin_unlock_irq(&pxa_rtc->lock); | |
226 | return 0; | |
227 | } | |
228 | ||
dc944368 RJ |
229 | static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm) |
230 | { | |
231 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
232 | u32 rycr, rdcr; | |
233 | ||
234 | rycr = rtc_readl(pxa_rtc, RYCR); | |
235 | rdcr = rtc_readl(pxa_rtc, RDCR); | |
236 | ||
237 | tm_calc(rycr, rdcr, tm); | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
242 | { | |
243 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
244 | ||
245 | rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm)); | |
246 | rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm)); | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
251 | static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
252 | { | |
253 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
254 | u32 rtsr, ryar, rdar; | |
255 | ||
256 | ryar = rtc_readl(pxa_rtc, RYAR1); | |
257 | rdar = rtc_readl(pxa_rtc, RDAR1); | |
258 | tm_calc(ryar, rdar, &alrm->time); | |
259 | ||
260 | rtsr = rtc_readl(pxa_rtc, RTSR); | |
261 | alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0; | |
262 | alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0; | |
263 | return 0; | |
264 | } | |
265 | ||
266 | static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
267 | { | |
268 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
269 | u32 rtsr; | |
270 | ||
271 | spin_lock_irq(&pxa_rtc->lock); | |
272 | ||
273 | rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time)); | |
274 | rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time)); | |
275 | ||
276 | rtsr = rtc_readl(pxa_rtc, RTSR); | |
277 | if (alrm->enabled) | |
278 | rtsr |= RTSR_RDALE1; | |
279 | else | |
280 | rtsr &= ~RTSR_RDALE1; | |
281 | rtc_writel(pxa_rtc, RTSR, rtsr); | |
282 | ||
283 | spin_unlock_irq(&pxa_rtc->lock); | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static int pxa_rtc_proc(struct device *dev, struct seq_file *seq) | |
289 | { | |
290 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); | |
291 | ||
292 | seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR)); | |
293 | seq_printf(seq, "update_IRQ\t: %s\n", | |
294 | (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no"); | |
295 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
296 | (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no"); | |
297 | seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR)); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | static const struct rtc_class_ops pxa_rtc_ops = { | |
303 | .open = pxa_rtc_open, | |
304 | .release = pxa_rtc_release, | |
dc944368 RJ |
305 | .read_time = pxa_rtc_read_time, |
306 | .set_time = pxa_rtc_set_time, | |
307 | .read_alarm = pxa_rtc_read_alarm, | |
308 | .set_alarm = pxa_rtc_set_alarm, | |
93b1384f | 309 | .alarm_irq_enable = pxa_alarm_irq_enable, |
dc944368 | 310 | .proc = pxa_rtc_proc, |
dc944368 RJ |
311 | }; |
312 | ||
0417ce2a | 313 | static int __init pxa_rtc_probe(struct platform_device *pdev) |
dc944368 RJ |
314 | { |
315 | struct device *dev = &pdev->dev; | |
316 | struct pxa_rtc *pxa_rtc; | |
317 | int ret; | |
318 | u32 rttr; | |
319 | ||
dc944368 RJ |
320 | pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL); |
321 | if (!pxa_rtc) | |
0417ce2a AZ |
322 | return -ENOMEM; |
323 | ||
324 | spin_lock_init(&pxa_rtc->lock); | |
325 | platform_set_drvdata(pdev, pxa_rtc); | |
dc944368 RJ |
326 | |
327 | ret = -ENXIO; | |
328 | pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
329 | if (!pxa_rtc->ress) { | |
330 | dev_err(dev, "No I/O memory resource defined\n"); | |
331 | goto err_ress; | |
332 | } | |
333 | ||
334 | pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0); | |
335 | if (pxa_rtc->irq_1Hz < 0) { | |
336 | dev_err(dev, "No 1Hz IRQ resource defined\n"); | |
337 | goto err_ress; | |
338 | } | |
339 | pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1); | |
340 | if (pxa_rtc->irq_Alrm < 0) { | |
341 | dev_err(dev, "No alarm IRQ resource defined\n"); | |
342 | goto err_ress; | |
343 | } | |
344 | ||
dc944368 RJ |
345 | ret = -ENOMEM; |
346 | pxa_rtc->base = ioremap(pxa_rtc->ress->start, | |
0417ce2a | 347 | resource_size(pxa_rtc->ress)); |
dc944368 RJ |
348 | if (!pxa_rtc->base) { |
349 | dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n"); | |
350 | goto err_map; | |
351 | } | |
352 | ||
353 | /* | |
354 | * If the clock divider is uninitialized then reset it to the | |
355 | * default value to get the 1Hz clock. | |
356 | */ | |
357 | if (rtc_readl(pxa_rtc, RTTR) == 0) { | |
358 | rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
359 | rtc_writel(pxa_rtc, RTTR, rttr); | |
360 | dev_warn(dev, "warning: initializing default clock" | |
361 | " divider/trim value\n"); | |
362 | } | |
363 | ||
364 | rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); | |
0417ce2a AZ |
365 | |
366 | pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops, | |
367 | THIS_MODULE); | |
368 | ret = PTR_ERR(pxa_rtc->rtc); | |
369 | if (IS_ERR(pxa_rtc->rtc)) { | |
370 | dev_err(dev, "Failed to register RTC device -> %d\n", ret); | |
371 | goto err_rtc_reg; | |
372 | } | |
373 | ||
dc944368 RJ |
374 | device_init_wakeup(dev, 1); |
375 | ||
376 | return 0; | |
377 | ||
dc944368 | 378 | err_rtc_reg: |
0417ce2a | 379 | iounmap(pxa_rtc->base); |
dc944368 | 380 | err_ress: |
0417ce2a | 381 | err_map: |
dc944368 | 382 | kfree(pxa_rtc); |
dc944368 RJ |
383 | return ret; |
384 | } | |
385 | ||
0417ce2a | 386 | static int __exit pxa_rtc_remove(struct platform_device *pdev) |
dc944368 RJ |
387 | { |
388 | struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev); | |
389 | ||
0417ce2a AZ |
390 | rtc_device_unregister(pxa_rtc->rtc); |
391 | ||
dc944368 RJ |
392 | spin_lock_irq(&pxa_rtc->lock); |
393 | iounmap(pxa_rtc->base); | |
dc944368 RJ |
394 | spin_unlock_irq(&pxa_rtc->lock); |
395 | ||
dc944368 RJ |
396 | kfree(pxa_rtc); |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
9020b7cc DM |
401 | #ifdef CONFIG_OF |
402 | static struct of_device_id pxa_rtc_dt_ids[] = { | |
403 | { .compatible = "marvell,pxa-rtc" }, | |
404 | {} | |
405 | }; | |
406 | MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids); | |
407 | #endif | |
408 | ||
dc944368 | 409 | #ifdef CONFIG_PM |
e6e698a4 | 410 | static int pxa_rtc_suspend(struct device *dev) |
dc944368 | 411 | { |
e6e698a4 | 412 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
dc944368 | 413 | |
e6e698a4 | 414 | if (device_may_wakeup(dev)) |
dc944368 RJ |
415 | enable_irq_wake(pxa_rtc->irq_Alrm); |
416 | return 0; | |
417 | } | |
418 | ||
e6e698a4 | 419 | static int pxa_rtc_resume(struct device *dev) |
dc944368 | 420 | { |
e6e698a4 | 421 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
dc944368 | 422 | |
e6e698a4 | 423 | if (device_may_wakeup(dev)) |
dc944368 RJ |
424 | disable_irq_wake(pxa_rtc->irq_Alrm); |
425 | return 0; | |
426 | } | |
e6e698a4 | 427 | |
47145210 | 428 | static const struct dev_pm_ops pxa_rtc_pm_ops = { |
e6e698a4 RJ |
429 | .suspend = pxa_rtc_suspend, |
430 | .resume = pxa_rtc_resume, | |
431 | }; | |
dc944368 RJ |
432 | #endif |
433 | ||
434 | static struct platform_driver pxa_rtc_driver = { | |
dc944368 | 435 | .remove = __exit_p(pxa_rtc_remove), |
dc944368 | 436 | .driver = { |
e6e698a4 | 437 | .name = "pxa-rtc", |
9020b7cc | 438 | .of_match_table = of_match_ptr(pxa_rtc_dt_ids), |
e6e698a4 RJ |
439 | #ifdef CONFIG_PM |
440 | .pm = &pxa_rtc_pm_ops, | |
441 | #endif | |
dc944368 RJ |
442 | }, |
443 | }; | |
444 | ||
445 | static int __init pxa_rtc_init(void) | |
446 | { | |
447 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) | |
0417ce2a | 448 | return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe); |
dc944368 RJ |
449 | |
450 | return -ENODEV; | |
451 | } | |
452 | ||
453 | static void __exit pxa_rtc_exit(void) | |
454 | { | |
455 | platform_driver_unregister(&pxa_rtc_driver); | |
456 | } | |
457 | ||
458 | module_init(pxa_rtc_init); | |
459 | module_exit(pxa_rtc_exit); | |
460 | ||
57f63bc8 | 461 | MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>"); |
dc944368 RJ |
462 | MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)"); |
463 | MODULE_LICENSE("GPL"); | |
464 | MODULE_ALIAS("platform:pxa-rtc"); |