[linux-2.6-block.git] / drivers / rtc / rtc-pxa.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Real Time Clock interface for XScale PXA27x and PXA3xx
 *
 * Copyright (C) 2008 Robert Jarzmik
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include "rtc-sa1100.h"

#define RTC_DEF_DIVIDER		(32768 - 1)
#define RTC_DEF_TRIM		0
#define MAXFREQ_PERIODIC	1000

/*
 * PXA Registers and bits definitions
 */
#define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
#define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
#define RTSR_PIAL	(1 << 13)	/* Periodic interrupt detected */
#define RTSR_SWALE2	(1 << 11)	/* RTC stopwatch alarm2 enable */
#define RTSR_SWAL2	(1 << 10)	/* RTC stopwatch alarm2 detected */
#define RTSR_SWALE1	(1 << 9)	/* RTC stopwatch alarm1 enable */
#define RTSR_SWAL1	(1 << 8)	/* RTC stopwatch alarm1 detected */
#define RTSR_RDALE2	(1 << 7)	/* RTC alarm2 enable */
#define RTSR_RDAL2	(1 << 6)	/* RTC alarm2 detected */
#define RTSR_RDALE1	(1 << 5)	/* RTC alarm1 enable */
#define RTSR_RDAL1	(1 << 4)	/* RTC alarm1 detected */
#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
#define RTSR_TRIG_MASK	(RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
			 | RTSR_SWAL1 | RTSR_SWAL2)
#define RYxR_YEAR_S	9
#define RYxR_YEAR_MASK	(0xfff << RYxR_YEAR_S)
#define RYxR_MONTH_S	5
#define RYxR_MONTH_MASK	(0xf << RYxR_MONTH_S)
#define RYxR_DAY_MASK	0x1f
#define RDxR_WOM_S     20
#define RDxR_WOM_MASK  (0x7 << RDxR_WOM_S)
#define RDxR_DOW_S     17
#define RDxR_DOW_MASK  (0x7 << RDxR_DOW_S)
#define RDxR_HOUR_S	12
#define RDxR_HOUR_MASK	(0x1f << RDxR_HOUR_S)
#define RDxR_MIN_S	6
#define RDxR_MIN_MASK	(0x3f << RDxR_MIN_S)
#define RDxR_SEC_MASK	0x3f

#define RTSR		0x08
#define RTTR		0x0c
#define RDCR		0x10
#define RYCR		0x14
#define RDAR1		0x18
#define RYAR1		0x1c
#define RTCPICR		0x34
#define PIAR		0x38

#define rtc_readl(pxa_rtc, reg)	\
	__raw_readl((pxa_rtc)->base + (reg))
#define rtc_writel(pxa_rtc, reg, value)	\
	__raw_writel((value), (pxa_rtc)->base + (reg))

struct pxa_rtc {
	struct sa1100_rtc sa1100_rtc;
	struct resource	*ress;
	void __iomem		*base;
	struct rtc_device	*rtc;
	spinlock_t		lock;		/* Protects this structure */
};


static u32 ryxr_calc(struct rtc_time *tm)
{
	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
		| ((tm->tm_mon + 1) << RYxR_MONTH_S)
		| tm->tm_mday;
}

static u32 rdxr_calc(struct rtc_time *tm)
{
	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
		| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
		| (tm->tm_hour << RDxR_HOUR_S)
		| (tm->tm_min << RDxR_MIN_S)
		| tm->tm_sec;
}

static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
{
	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
	tm->tm_mday = (rycr & RYxR_DAY_MASK);
	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
	tm->tm_sec = rdcr & RDxR_SEC_MASK;
}

static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
	u32 rtsr;

	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtsr &= ~RTSR_TRIG_MASK;
	rtsr &= ~mask;
	rtc_writel(pxa_rtc, RTSR, rtsr);
}

static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
	u32 rtsr;

	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtsr &= ~RTSR_TRIG_MASK;
	rtsr |= mask;
	rtc_writel(pxa_rtc, RTSR, rtsr);
}

static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
	u32 rtsr;
	unsigned long events = 0;

	spin_lock(&pxa_rtc->lock);

	/* clear interrupt sources */
	rtsr = rtc_readl(pxa_rtc, RTSR);
	rtc_writel(pxa_rtc, RTSR, rtsr);

	/* temporary disable rtc interrupts */
	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);

	/* clear alarm interrupt if it has occurred */
	if (rtsr & RTSR_RDAL1)
		rtsr &= ~RTSR_RDALE1;

	/* update irq data & counter */
	if (rtsr & RTSR_RDAL1)
		events |= RTC_AF | RTC_IRQF;
	if (rtsr & RTSR_HZ)
		events |= RTC_UF | RTC_IRQF;
	if (rtsr & RTSR_PIAL)
		events |= RTC_PF | RTC_IRQF;

	rtc_update_irq(pxa_rtc->rtc, 1, events);

	/* enable back rtc interrupts */
	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);

	spin_unlock(&pxa_rtc->lock);
	return IRQ_HANDLED;
}

static int pxa_rtc_open(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	int ret;

	ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
			  "rtc 1Hz", dev);
	if (ret < 0) {
		dev_err(dev, "can't get irq %i, err %d\n",
			pxa_rtc->sa1100_rtc.irq_1hz, ret);
		goto err_irq_1Hz;
	}
	ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
			  "rtc Alrm", dev);
	if (ret < 0) {
		dev_err(dev, "can't get irq %i, err %d\n",
			pxa_rtc->sa1100_rtc.irq_alarm, ret);
		goto err_irq_Alrm;
	}

	return 0;

err_irq_Alrm:
	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
err_irq_1Hz:
	return ret;
}

static void pxa_rtc_release(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	spin_lock_irq(&pxa_rtc->lock);
	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
	spin_unlock_irq(&pxa_rtc->lock);

	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
	free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
}

static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	spin_lock_irq(&pxa_rtc->lock);

	if (enabled)
		rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
	else
		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);

	spin_unlock_irq(&pxa_rtc->lock);
	return 0;
}

static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rycr, rdcr;

	rycr = rtc_readl(pxa_rtc, RYCR);
	rdcr = rtc_readl(pxa_rtc, RDCR);

	tm_calc(rycr, rdcr, tm);
	return 0;
}

static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));

	return 0;
}

static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rtsr, ryar, rdar;

	ryar = rtc_readl(pxa_rtc, RYAR1);
	rdar = rtc_readl(pxa_rtc, RDAR1);
	tm_calc(ryar, rdar, &alrm->time);

	rtsr = rtc_readl(pxa_rtc, RTSR);
	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
	return 0;
}

static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	u32 rtsr;

	spin_lock_irq(&pxa_rtc->lock);

	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));

	rtsr = rtc_readl(pxa_rtc, RTSR);
	if (alrm->enabled)
		rtsr |= RTSR_RDALE1;
	else
		rtsr &= ~RTSR_RDALE1;
	rtc_writel(pxa_rtc, RTSR, rtsr);

	spin_unlock_irq(&pxa_rtc->lock);

	return 0;
}

static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
	seq_printf(seq, "update_IRQ\t: %s\n",
		   (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
	seq_printf(seq, "periodic_IRQ\t: %s\n",
		   (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));

	return 0;
}

static const struct rtc_class_ops pxa_rtc_ops = {
	.read_time = pxa_rtc_read_time,
	.set_time = pxa_rtc_set_time,
	.read_alarm = pxa_rtc_read_alarm,
	.set_alarm = pxa_rtc_set_alarm,
	.alarm_irq_enable = pxa_alarm_irq_enable,
	.proc = pxa_rtc_proc,
};

static int __init pxa_rtc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct pxa_rtc *pxa_rtc;
	struct sa1100_rtc *sa1100_rtc;
	int ret;

	pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
	if (!pxa_rtc)
		return -ENOMEM;
	sa1100_rtc = &pxa_rtc->sa1100_rtc;

	spin_lock_init(&pxa_rtc->lock);
	platform_set_drvdata(pdev, pxa_rtc);

	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!pxa_rtc->ress) {
		dev_err(dev, "No I/O memory resource defined\n");
		return -ENXIO;
	}

	sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
	if (sa1100_rtc->irq_1hz < 0)
		return -ENXIO;
	sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
	if (sa1100_rtc->irq_alarm < 0)
		return -ENXIO;

	sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(sa1100_rtc->rtc))
		return PTR_ERR(sa1100_rtc->rtc);

	pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
				resource_size(pxa_rtc->ress));
	if (!pxa_rtc->base) {
		dev_err(dev, "Unable to map pxa RTC I/O memory\n");
		return -ENOMEM;
	}

	pxa_rtc_open(dev);

	sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
	sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
	sa1100_rtc->rtar = pxa_rtc->base + 0x4;
	sa1100_rtc->rttr = pxa_rtc->base + 0xc;
	ret = sa1100_rtc_init(pdev, sa1100_rtc);
	if (ret) {
		dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
		return ret;
	}

	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);

	pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
						&pxa_rtc_ops, THIS_MODULE);
	if (IS_ERR(pxa_rtc->rtc)) {
		ret = PTR_ERR(pxa_rtc->rtc);
		dev_err(dev, "Failed to register RTC device -> %d\n", ret);
		return ret;
	}

	device_init_wakeup(dev, 1);

	return 0;
}

static int __exit pxa_rtc_remove(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;

	pxa_rtc_release(dev);
	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id pxa_rtc_dt_ids[] = {
	{ .compatible = "marvell,pxa-rtc" },
	{}
};
MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
#endif

#ifdef CONFIG_PM_SLEEP
static int pxa_rtc_suspend(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
	return 0;
}

static int pxa_rtc_resume(struct device *dev)
{
	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);

static struct platform_driver pxa_rtc_driver = {
	.remove		= __exit_p(pxa_rtc_remove),
	.driver		= {
		.name	= "pxa-rtc",
		.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
		.pm	= &pxa_rtc_pm_ops,
	},
};

module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);

MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa-rtc");
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
dc944368 RJ	2	/*
	3	* Real Time Clock interface for XScale PXA27x and PXA3xx
	4	*
	5	* Copyright (C) 2008 Robert Jarzmik
dc944368 RJ	6	*/
dc944368 RJ	7
0417ce2a	8	#include <linux/init.h>
dc944368 RJ	9	#include <linux/platform_device.h>
	10	#include <linux/module.h>
	11	#include <linux/rtc.h>
	12	#include <linux/seq_file.h>
	13	#include <linux/interrupt.h>
0417ce2a	14	#include <linux/io.h>
5a0e3ad6	15	#include <linux/slab.h>
9020b7cc DM	16	#include <linux/of.h>
9020b7cc DM	17	#include <linux/of_device.h>
dc944368	18
3cdf4ad9 RH	19	#include "rtc-sa1100.h"
3cdf4ad9 RH	20
dc944368 RJ	21	#define RTC_DEF_DIVIDER (32768 - 1)
	22	#define RTC_DEF_TRIM 0
	23	#define MAXFREQ_PERIODIC 1000
	24
	25	/*
	26	* PXA Registers and bits definitions
	27	*/
	28	#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
	29	#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
	30	#define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
	31	#define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
	32	#define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
	33	#define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
	34	#define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
	35	#define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
	36	#define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
	37	#define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
	38	#define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
	39	#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
	40	#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
	41	#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
	42	#define RTSR_AL (1 << 0) /* RTC alarm detected */
	43	#define RTSR_TRIG_MASK (RTSR_AL \| RTSR_HZ \| RTSR_RDAL1 \| RTSR_RDAL2\
	44	\| RTSR_SWAL1 \| RTSR_SWAL2)
	45	#define RYxR_YEAR_S 9
	46	#define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
	47	#define RYxR_MONTH_S 5
	48	#define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
	49	#define RYxR_DAY_MASK 0x1f
c4243de7 LS	50	#define RDxR_WOM_S 20
	51	#define RDxR_WOM_MASK (0x7 << RDxR_WOM_S)
	52	#define RDxR_DOW_S 17
	53	#define RDxR_DOW_MASK (0x7 << RDxR_DOW_S)
dc944368 RJ	54	#define RDxR_HOUR_S 12
	55	#define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
	56	#define RDxR_MIN_S 6
	57	#define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
	58	#define RDxR_SEC_MASK 0x3f
	59
	60	#define RTSR 0x08
	61	#define RTTR 0x0c
	62	#define RDCR 0x10
	63	#define RYCR 0x14
	64	#define RDAR1 0x18
	65	#define RYAR1 0x1c
	66	#define RTCPICR 0x34
	67	#define PIAR 0x38
	68
	69	#define rtc_readl(pxa_rtc, reg) \
	70	__raw_readl((pxa_rtc)->base + (reg))
	71	#define rtc_writel(pxa_rtc, reg, value) \
	72	__raw_writel((value), (pxa_rtc)->base + (reg))
	73
	74	struct pxa_rtc {
3cdf4ad9	75	struct sa1100_rtc sa1100_rtc;
dc944368 RJ	76	struct resource *ress;
dc944368 RJ	77	void __iomem *base;
dc944368 RJ	78	struct rtc_device *rtc;
dc944368 RJ	79	spinlock_t lock; /* Protects this structure */
dc944368 RJ	80	};
dc944368 RJ	81
c4243de7	82
dc944368 RJ	83	static u32 ryxr_calc(struct rtc_time *tm)
	84	{
	85	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
	86	\| ((tm->tm_mon + 1) << RYxR_MONTH_S)
	87	\| tm->tm_mday;
	88	}
	89
	90	static u32 rdxr_calc(struct rtc_time *tm)
	91	{
c4243de7 LS	92	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
	93	\| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
	94	\| (tm->tm_hour << RDxR_HOUR_S)
	95	\| (tm->tm_min << RDxR_MIN_S)
dc944368 RJ	96	\| tm->tm_sec;
	97	}
	98
	99	static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
	100	{
	101	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
	102	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
	103	tm->tm_mday = (rycr & RYxR_DAY_MASK);
c4243de7	104	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
dc944368 RJ	105	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
	106	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
	107	tm->tm_sec = rdcr & RDxR_SEC_MASK;
	108	}
	109
	110	static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
	111	{
	112	u32 rtsr;
	113
	114	rtsr = rtc_readl(pxa_rtc, RTSR);
	115	rtsr &= ~RTSR_TRIG_MASK;
	116	rtsr &= ~mask;
	117	rtc_writel(pxa_rtc, RTSR, rtsr);
	118	}
	119
	120	static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
	121	{
	122	u32 rtsr;
	123
	124	rtsr = rtc_readl(pxa_rtc, RTSR);
	125	rtsr &= ~RTSR_TRIG_MASK;
	126	rtsr \|= mask;
	127	rtc_writel(pxa_rtc, RTSR, rtsr);
	128	}
	129
	130	static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
	131	{
527bd754	132	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
dc944368 RJ	133	u32 rtsr;
	134	unsigned long events = 0;
	135
	136	spin_lock(&pxa_rtc->lock);
	137
	138	/* clear interrupt sources */
	139	rtsr = rtc_readl(pxa_rtc, RTSR);
	140	rtc_writel(pxa_rtc, RTSR, rtsr);
	141
	142	/* temporary disable rtc interrupts */
	143	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 \| RTSR_PIALE \| RTSR_HZE);
	144
	145	/* clear alarm interrupt if it has occurred */
	146	if (rtsr & RTSR_RDAL1)
	147	rtsr &= ~RTSR_RDALE1;
	148
	149	/* update irq data & counter */
	150	if (rtsr & RTSR_RDAL1)
	151	events \|= RTC_AF \| RTC_IRQF;
	152	if (rtsr & RTSR_HZ)
	153	events \|= RTC_UF \| RTC_IRQF;
	154	if (rtsr & RTSR_PIAL)
	155	events \|= RTC_PF \| RTC_IRQF;
	156
	157	rtc_update_irq(pxa_rtc->rtc, 1, events);
	158
	159	/* enable back rtc interrupts */
	160	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
	161
	162	spin_unlock(&pxa_rtc->lock);
	163	return IRQ_HANDLED;
	164	}
	165
	166	static int pxa_rtc_open(struct device *dev)
	167	{
	168	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	169	int ret;
	170
3cdf4ad9	171	ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
dc944368 RJ	172	"rtc 1Hz", dev);
dc944368 RJ	173	if (ret < 0) {
3cdf4ad9 RH	174	dev_err(dev, "can't get irq %i, err %d\n",
3cdf4ad9 RH	175	pxa_rtc->sa1100_rtc.irq_1hz, ret);
dc944368 RJ	176	goto err_irq_1Hz;
dc944368 RJ	177	}
3cdf4ad9	178	ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
dc944368 RJ	179	"rtc Alrm", dev);
dc944368 RJ	180	if (ret < 0) {
3cdf4ad9 RH	181	dev_err(dev, "can't get irq %i, err %d\n",
3cdf4ad9 RH	182	pxa_rtc->sa1100_rtc.irq_alarm, ret);
dc944368 RJ	183	goto err_irq_Alrm;
	184	}
	185
	186	return 0;
	187
	188	err_irq_Alrm:
3cdf4ad9	189	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
dc944368 RJ	190	err_irq_1Hz:
	191	return ret;
	192	}
	193
	194	static void pxa_rtc_release(struct device *dev)
	195	{
	196	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	197
	198	spin_lock_irq(&pxa_rtc->lock);
	199	rtsr_clear_bits(pxa_rtc, RTSR_PIALE \| RTSR_RDALE1 \| RTSR_HZE);
	200	spin_unlock_irq(&pxa_rtc->lock);
	201
3cdf4ad9 RH	202	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
3cdf4ad9 RH	203	free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
dc944368 RJ	204	}
dc944368 RJ	205
93b1384f	206	static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
dc944368 RJ	207	{
dc944368 RJ	208	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368 RJ	209
dc944368 RJ	210	spin_lock_irq(&pxa_rtc->lock);
93b1384f WZ	211
93b1384f WZ	212	if (enabled)
dc944368	213	rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
93b1384f WZ	214	else
	215	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
	216
	217	spin_unlock_irq(&pxa_rtc->lock);
	218	return 0;
	219	}
	220
dc944368 RJ	221	static int pxa_rtc_read_time(struct device dev, struct rtc_time tm)
	222	{
	223	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	224	u32 rycr, rdcr;
	225
	226	rycr = rtc_readl(pxa_rtc, RYCR);
	227	rdcr = rtc_readl(pxa_rtc, RDCR);
	228
	229	tm_calc(rycr, rdcr, tm);
	230	return 0;
	231	}
	232
	233	static int pxa_rtc_set_time(struct device dev, struct rtc_time tm)
	234	{
	235	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	236
	237	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
	238	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
	239
	240	return 0;
	241	}
	242
	243	static int pxa_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	244	{
	245	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	246	u32 rtsr, ryar, rdar;
	247
	248	ryar = rtc_readl(pxa_rtc, RYAR1);
	249	rdar = rtc_readl(pxa_rtc, RDAR1);
	250	tm_calc(ryar, rdar, &alrm->time);
	251
	252	rtsr = rtc_readl(pxa_rtc, RTSR);
	253	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
	254	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
	255	return 0;
	256	}
	257
	258	static int pxa_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	259	{
	260	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	261	u32 rtsr;
	262
	263	spin_lock_irq(&pxa_rtc->lock);
	264
	265	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
	266	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
	267
	268	rtsr = rtc_readl(pxa_rtc, RTSR);
	269	if (alrm->enabled)
	270	rtsr \|= RTSR_RDALE1;
	271	else
	272	rtsr &= ~RTSR_RDALE1;
	273	rtc_writel(pxa_rtc, RTSR, rtsr);
	274
	275	spin_unlock_irq(&pxa_rtc->lock);
	276
	277	return 0;
	278	}
	279
	280	static int pxa_rtc_proc(struct device dev, struct seq_file seq)
	281	{
	282	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
	283
	284	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
285	seq_printf(seq, "update_IRQ\t: %s\n",
286	(rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
287	seq_printf(seq, "periodic_IRQ\t: %s\n",
288	(rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
289	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
290
291	return 0;
292	}
293
294	static const struct rtc_class_ops pxa_rtc_ops = {
dc944368 RJ	295	.read_time = pxa_rtc_read_time,
	296	.set_time = pxa_rtc_set_time,
	297	.read_alarm = pxa_rtc_read_alarm,
	298	.set_alarm = pxa_rtc_set_alarm,
93b1384f	299	.alarm_irq_enable = pxa_alarm_irq_enable,
dc944368	300	.proc = pxa_rtc_proc,
dc944368 RJ	301	};
dc944368 RJ	302
0417ce2a	303	static int __init pxa_rtc_probe(struct platform_device *pdev)
dc944368 RJ	304	{
	305	struct device *dev = &pdev->dev;
	306	struct pxa_rtc *pxa_rtc;
3cdf4ad9	307	struct sa1100_rtc *sa1100_rtc;
dc944368	308	int ret;
dc944368	309
618c3003	310	pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
dc944368	311	if (!pxa_rtc)
0417ce2a	312	return -ENOMEM;
3cdf4ad9	313	sa1100_rtc = &pxa_rtc->sa1100_rtc;
0417ce2a AZ	314
	315	spin_lock_init(&pxa_rtc->lock);
	316	platform_set_drvdata(pdev, pxa_rtc);
dc944368	317
dc944368 RJ	318	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	319	if (!pxa_rtc->ress) {
	320	dev_err(dev, "No I/O memory resource defined\n");
618c3003	321	return -ENXIO;
dc944368 RJ	322	}
dc944368 RJ	323
3cdf4ad9	324	sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
faac9102	325	if (sa1100_rtc->irq_1hz < 0)
618c3003	326	return -ENXIO;
3cdf4ad9	327	sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
faac9102	328	if (sa1100_rtc->irq_alarm < 0)
618c3003	329	return -ENXIO;
56c0c529	330
34127b36 LB	331	sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
	332	if (IS_ERR(sa1100_rtc->rtc))
	333	return PTR_ERR(sa1100_rtc->rtc);
	334
618c3003	335	pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
0417ce2a	336	resource_size(pxa_rtc->ress));
dc944368	337	if (!pxa_rtc->base) {
618c3003 JH	338	dev_err(dev, "Unable to map pxa RTC I/O memory\n");
618c3003 JH	339	return -ENOMEM;
dc944368 RJ	340	}
dc944368 RJ	341
56c0c529 AB	342	pxa_rtc_open(dev);
56c0c529 AB	343
90d0ae8e RH	344	sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
	345	sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
	346	sa1100_rtc->rtar = pxa_rtc->base + 0x4;
	347	sa1100_rtc->rttr = pxa_rtc->base + 0xc;
3cdf4ad9	348	ret = sa1100_rtc_init(pdev, sa1100_rtc);
e4302aec	349	if (ret) {
3cdf4ad9 RH	350	dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
3cdf4ad9 RH	351	return ret;
dc944368 RJ	352	}
	353
	354	rtsr_clear_bits(pxa_rtc, RTSR_PIALE \| RTSR_RDALE1 \| RTSR_HZE);
0417ce2a	355
618c3003 JH	356	pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
618c3003 JH	357	&pxa_rtc_ops, THIS_MODULE);
0417ce2a	358	if (IS_ERR(pxa_rtc->rtc)) {
618c3003	359	ret = PTR_ERR(pxa_rtc->rtc);
0417ce2a	360	dev_err(dev, "Failed to register RTC device -> %d\n", ret);
618c3003	361	return ret;
0417ce2a AZ	362	}
0417ce2a AZ	363
dc944368 RJ	364	device_init_wakeup(dev, 1);
	365
	366	return 0;
dc944368 RJ	367	}
dc944368 RJ	368
0417ce2a	369	static int __exit pxa_rtc_remove(struct platform_device *pdev)
dc944368	370	{
a44802f8	371	struct device *dev = &pdev->dev;
dc944368	372
618c3003	373	pxa_rtc_release(dev);
dc944368 RJ	374	return 0;
	375	}
	376
9020b7cc	377	#ifdef CONFIG_OF
8b18daa1	378	static const struct of_device_id pxa_rtc_dt_ids[] = {
9020b7cc DM	379	{ .compatible = "marvell,pxa-rtc" },
	380	{}
	381	};
	382	MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
	383	#endif
	384
c5a40618	385	#ifdef CONFIG_PM_SLEEP
e6e698a4	386	static int pxa_rtc_suspend(struct device *dev)
dc944368	387	{
e6e698a4	388	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368	389
e6e698a4	390	if (device_may_wakeup(dev))
3cdf4ad9	391	enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
dc944368 RJ	392	return 0;
	393	}
	394
e6e698a4	395	static int pxa_rtc_resume(struct device *dev)
dc944368	396	{
e6e698a4	397	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
dc944368	398
e6e698a4	399	if (device_may_wakeup(dev))
3cdf4ad9	400	disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
dc944368 RJ	401	return 0;
dc944368 RJ	402	}
dc944368 RJ	403	#endif
dc944368 RJ	404
c5a40618 JH	405	static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
c5a40618 JH	406
dc944368	407	static struct platform_driver pxa_rtc_driver = {
dc944368	408	.remove = __exit_p(pxa_rtc_remove),
dc944368	409	.driver = {
e6e698a4	410	.name = "pxa-rtc",
9020b7cc	411	.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
e6e698a4	412	.pm = &pxa_rtc_pm_ops,
dc944368 RJ	413	},
	414	};
	415
7daba88e	416	module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
dc944368	417
57f63bc8	418	MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
dc944368 RJ	419	MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
	420	MODULE_LICENSE("GPL");
	421	MODULE_ALIAS("platform:pxa-rtc");