Commit | Line | Data |
---|---|---|
9a9a54ad AG |
1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
5a418558 | 12 | #include <linux/of.h> |
9a9a54ad AG |
13 | #include <linux/module.h> |
14 | #include <linux/init.h> | |
15 | #include <linux/rtc.h> | |
5d7dc4cf | 16 | #include <linux/platform_device.h> |
9a9a54ad | 17 | #include <linux/pm.h> |
5d7dc4cf | 18 | #include <linux/regmap.h> |
9a9a54ad AG |
19 | #include <linux/slab.h> |
20 | #include <linux/spinlock.h> | |
21 | ||
9a9a54ad AG |
22 | /* RTC Register offsets from RTC CTRL REG */ |
23 | #define PM8XXX_ALARM_CTRL_OFFSET 0x01 | |
24 | #define PM8XXX_RTC_WRITE_OFFSET 0x02 | |
25 | #define PM8XXX_RTC_READ_OFFSET 0x06 | |
26 | #define PM8XXX_ALARM_RW_OFFSET 0x0A | |
27 | ||
28 | /* RTC_CTRL register bit fields */ | |
29 | #define PM8xxx_RTC_ENABLE BIT(7) | |
9a9a54ad AG |
30 | #define PM8xxx_RTC_ALARM_CLEAR BIT(0) |
31 | ||
32 | #define NUM_8_BIT_RTC_REGS 0x4 | |
33 | ||
c8d523a4 SV |
34 | /** |
35 | * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions | |
36 | * @ctrl: base address of control register | |
37 | * @write: base address of write register | |
38 | * @read: base address of read register | |
39 | * @alarm_ctrl: base address of alarm control register | |
40 | * @alarm_ctrl2: base address of alarm control2 register | |
41 | * @alarm_rw: base address of alarm read-write register | |
42 | * @alarm_en: alarm enable mask | |
43 | */ | |
44 | struct pm8xxx_rtc_regs { | |
45 | unsigned int ctrl; | |
46 | unsigned int write; | |
47 | unsigned int read; | |
48 | unsigned int alarm_ctrl; | |
49 | unsigned int alarm_ctrl2; | |
50 | unsigned int alarm_rw; | |
51 | unsigned int alarm_en; | |
52 | }; | |
53 | ||
9a9a54ad AG |
54 | /** |
55 | * struct pm8xxx_rtc - rtc driver internal structure | |
56 | * @rtc: rtc device for this driver. | |
5d7dc4cf | 57 | * @regmap: regmap used to access RTC registers |
5a418558 | 58 | * @allow_set_time: indicates whether writing to the RTC is allowed |
9a9a54ad | 59 | * @rtc_alarm_irq: rtc alarm irq number. |
9a9a54ad AG |
60 | * @ctrl_reg: rtc control register. |
61 | * @rtc_dev: device structure. | |
62 | * @ctrl_reg_lock: spinlock protecting access to ctrl_reg. | |
63 | */ | |
64 | struct pm8xxx_rtc { | |
65 | struct rtc_device *rtc; | |
5d7dc4cf | 66 | struct regmap *regmap; |
5a418558 | 67 | bool allow_set_time; |
9a9a54ad | 68 | int rtc_alarm_irq; |
c8d523a4 | 69 | const struct pm8xxx_rtc_regs *regs; |
9a9a54ad AG |
70 | struct device *rtc_dev; |
71 | spinlock_t ctrl_reg_lock; | |
72 | }; | |
73 | ||
9a9a54ad AG |
74 | /* |
75 | * Steps to write the RTC registers. | |
76 | * 1. Disable alarm if enabled. | |
77 | * 2. Write 0x00 to LSB. | |
78 | * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0]. | |
79 | * 4. Enable alarm if disabled in step 1. | |
80 | */ | |
81 | static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
82 | { | |
83 | int rc, i; | |
84 | unsigned long secs, irq_flags; | |
c8d523a4 SV |
85 | u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0; |
86 | unsigned int ctrl_reg; | |
9a9a54ad | 87 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
c8d523a4 | 88 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad | 89 | |
5a418558 JC |
90 | if (!rtc_dd->allow_set_time) |
91 | return -EACCES; | |
92 | ||
9a9a54ad AG |
93 | rtc_tm_to_time(tm, &secs); |
94 | ||
95 | for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { | |
96 | value[i] = secs & 0xFF; | |
97 | secs >>= 8; | |
98 | } | |
99 | ||
100 | dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); | |
101 | ||
102 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
9a9a54ad | 103 | |
c8d523a4 SV |
104 | rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg); |
105 | if (rc) | |
106 | goto rtc_rw_fail; | |
107 | ||
108 | if (ctrl_reg & regs->alarm_en) { | |
9a9a54ad | 109 | alarm_enabled = 1; |
c8d523a4 SV |
110 | ctrl_reg &= ~regs->alarm_en; |
111 | rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); | |
5d7dc4cf | 112 | if (rc) { |
5bed811d | 113 | dev_err(dev, "Write to RTC control register failed\n"); |
9a9a54ad AG |
114 | goto rtc_rw_fail; |
115 | } | |
5bed811d | 116 | } |
9a9a54ad AG |
117 | |
118 | /* Write 0 to Byte[0] */ | |
c8d523a4 | 119 | rc = regmap_write(rtc_dd->regmap, regs->write, 0); |
5d7dc4cf | 120 | if (rc) { |
9a9a54ad AG |
121 | dev_err(dev, "Write to RTC write data register failed\n"); |
122 | goto rtc_rw_fail; | |
123 | } | |
124 | ||
125 | /* Write Byte[1], Byte[2], Byte[3] */ | |
c8d523a4 | 126 | rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1, |
5d7dc4cf JC |
127 | &value[1], sizeof(value) - 1); |
128 | if (rc) { | |
9a9a54ad AG |
129 | dev_err(dev, "Write to RTC write data register failed\n"); |
130 | goto rtc_rw_fail; | |
131 | } | |
132 | ||
133 | /* Write Byte[0] */ | |
c8d523a4 | 134 | rc = regmap_write(rtc_dd->regmap, regs->write, value[0]); |
5d7dc4cf | 135 | if (rc) { |
9a9a54ad AG |
136 | dev_err(dev, "Write to RTC write data register failed\n"); |
137 | goto rtc_rw_fail; | |
138 | } | |
139 | ||
140 | if (alarm_enabled) { | |
c8d523a4 SV |
141 | ctrl_reg |= regs->alarm_en; |
142 | rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); | |
5d7dc4cf | 143 | if (rc) { |
5bed811d | 144 | dev_err(dev, "Write to RTC control register failed\n"); |
9a9a54ad AG |
145 | goto rtc_rw_fail; |
146 | } | |
9a9a54ad AG |
147 | } |
148 | ||
149 | rtc_rw_fail: | |
c8d523a4 | 150 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
9a9a54ad AG |
151 | |
152 | return rc; | |
153 | } | |
154 | ||
155 | static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
156 | { | |
157 | int rc; | |
5d7dc4cf | 158 | u8 value[NUM_8_BIT_RTC_REGS]; |
9a9a54ad | 159 | unsigned long secs; |
5d7dc4cf | 160 | unsigned int reg; |
9a9a54ad | 161 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
c8d523a4 | 162 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad | 163 | |
c8d523a4 | 164 | rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value)); |
5d7dc4cf | 165 | if (rc) { |
9a9a54ad AG |
166 | dev_err(dev, "RTC read data register failed\n"); |
167 | return rc; | |
168 | } | |
169 | ||
170 | /* | |
171 | * Read the LSB again and check if there has been a carry over. | |
172 | * If there is, redo the read operation. | |
173 | */ | |
c8d523a4 | 174 | rc = regmap_read(rtc_dd->regmap, regs->read, ®); |
9a9a54ad AG |
175 | if (rc < 0) { |
176 | dev_err(dev, "RTC read data register failed\n"); | |
177 | return rc; | |
178 | } | |
179 | ||
180 | if (unlikely(reg < value[0])) { | |
c8d523a4 | 181 | rc = regmap_bulk_read(rtc_dd->regmap, regs->read, |
5d7dc4cf JC |
182 | value, sizeof(value)); |
183 | if (rc) { | |
9a9a54ad AG |
184 | dev_err(dev, "RTC read data register failed\n"); |
185 | return rc; | |
186 | } | |
187 | } | |
188 | ||
189 | secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); | |
190 | ||
191 | rtc_time_to_tm(secs, tm); | |
192 | ||
9a9a54ad | 193 | dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n", |
5bed811d JC |
194 | secs, tm->tm_hour, tm->tm_min, tm->tm_sec, |
195 | tm->tm_mday, tm->tm_mon, tm->tm_year); | |
9a9a54ad AG |
196 | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
201 | { | |
202 | int rc, i; | |
c8d523a4 SV |
203 | u8 value[NUM_8_BIT_RTC_REGS]; |
204 | unsigned int ctrl_reg; | |
9a9a54ad AG |
205 | unsigned long secs, irq_flags; |
206 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
c8d523a4 | 207 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad AG |
208 | |
209 | rtc_tm_to_time(&alarm->time, &secs); | |
210 | ||
211 | for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { | |
212 | value[i] = secs & 0xFF; | |
213 | secs >>= 8; | |
214 | } | |
215 | ||
216 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
217 | ||
c8d523a4 | 218 | rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value, |
5d7dc4cf JC |
219 | sizeof(value)); |
220 | if (rc) { | |
9a9a54ad AG |
221 | dev_err(dev, "Write to RTC ALARM register failed\n"); |
222 | goto rtc_rw_fail; | |
223 | } | |
224 | ||
c8d523a4 SV |
225 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
226 | if (rc) | |
227 | goto rtc_rw_fail; | |
5bed811d JC |
228 | |
229 | if (alarm->enabled) | |
c8d523a4 | 230 | ctrl_reg |= regs->alarm_en; |
5bed811d | 231 | else |
c8d523a4 | 232 | ctrl_reg &= ~regs->alarm_en; |
9a9a54ad | 233 | |
c8d523a4 | 234 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
5d7dc4cf | 235 | if (rc) { |
c8d523a4 | 236 | dev_err(dev, "Write to RTC alarm control register failed\n"); |
9a9a54ad AG |
237 | goto rtc_rw_fail; |
238 | } | |
239 | ||
9a9a54ad | 240 | dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", |
5bed811d JC |
241 | alarm->time.tm_hour, alarm->time.tm_min, |
242 | alarm->time.tm_sec, alarm->time.tm_mday, | |
243 | alarm->time.tm_mon, alarm->time.tm_year); | |
9a9a54ad AG |
244 | rtc_rw_fail: |
245 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | |
246 | return rc; | |
247 | } | |
248 | ||
249 | static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
250 | { | |
251 | int rc; | |
252 | u8 value[NUM_8_BIT_RTC_REGS]; | |
253 | unsigned long secs; | |
254 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
c8d523a4 | 255 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad | 256 | |
c8d523a4 | 257 | rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value, |
5d7dc4cf JC |
258 | sizeof(value)); |
259 | if (rc) { | |
9a9a54ad AG |
260 | dev_err(dev, "RTC alarm time read failed\n"); |
261 | return rc; | |
262 | } | |
263 | ||
264 | secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); | |
265 | ||
266 | rtc_time_to_tm(secs, &alarm->time); | |
267 | ||
268 | rc = rtc_valid_tm(&alarm->time); | |
269 | if (rc < 0) { | |
270 | dev_err(dev, "Invalid alarm time read from RTC\n"); | |
271 | return rc; | |
272 | } | |
273 | ||
274 | dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", | |
5bed811d JC |
275 | alarm->time.tm_hour, alarm->time.tm_min, |
276 | alarm->time.tm_sec, alarm->time.tm_mday, | |
277 | alarm->time.tm_mon, alarm->time.tm_year); | |
9a9a54ad AG |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
282 | static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) | |
283 | { | |
284 | int rc; | |
285 | unsigned long irq_flags; | |
286 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
c8d523a4 SV |
287 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
288 | unsigned int ctrl_reg; | |
9a9a54ad AG |
289 | |
290 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
5bed811d | 291 | |
c8d523a4 SV |
292 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
293 | if (rc) | |
294 | goto rtc_rw_fail; | |
5bed811d JC |
295 | |
296 | if (enable) | |
c8d523a4 | 297 | ctrl_reg |= regs->alarm_en; |
5bed811d | 298 | else |
c8d523a4 | 299 | ctrl_reg &= ~regs->alarm_en; |
9a9a54ad | 300 | |
c8d523a4 | 301 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
5d7dc4cf | 302 | if (rc) { |
9a9a54ad AG |
303 | dev_err(dev, "Write to RTC control register failed\n"); |
304 | goto rtc_rw_fail; | |
305 | } | |
306 | ||
9a9a54ad AG |
307 | rtc_rw_fail: |
308 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | |
309 | return rc; | |
310 | } | |
311 | ||
5a418558 | 312 | static const struct rtc_class_ops pm8xxx_rtc_ops = { |
9a9a54ad | 313 | .read_time = pm8xxx_rtc_read_time, |
5a418558 | 314 | .set_time = pm8xxx_rtc_set_time, |
9a9a54ad AG |
315 | .set_alarm = pm8xxx_rtc_set_alarm, |
316 | .read_alarm = pm8xxx_rtc_read_alarm, | |
317 | .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable, | |
318 | }; | |
319 | ||
320 | static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) | |
321 | { | |
322 | struct pm8xxx_rtc *rtc_dd = dev_id; | |
c8d523a4 | 323 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
5d7dc4cf | 324 | unsigned int ctrl_reg; |
9a9a54ad AG |
325 | int rc; |
326 | unsigned long irq_flags; | |
327 | ||
328 | rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF); | |
329 | ||
330 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
331 | ||
332 | /* Clear the alarm enable bit */ | |
c8d523a4 SV |
333 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
334 | if (rc) { | |
335 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | |
336 | goto rtc_alarm_handled; | |
337 | } | |
338 | ||
339 | ctrl_reg &= ~regs->alarm_en; | |
9a9a54ad | 340 | |
c8d523a4 | 341 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
5d7dc4cf | 342 | if (rc) { |
9a9a54ad | 343 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
5bed811d | 344 | dev_err(rtc_dd->rtc_dev, |
c8d523a4 | 345 | "Write to alarm control register failed\n"); |
9a9a54ad AG |
346 | goto rtc_alarm_handled; |
347 | } | |
348 | ||
9a9a54ad AG |
349 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
350 | ||
351 | /* Clear RTC alarm register */ | |
c8d523a4 | 352 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg); |
5d7dc4cf | 353 | if (rc) { |
5bed811d | 354 | dev_err(rtc_dd->rtc_dev, |
c8d523a4 | 355 | "RTC Alarm control2 register read failed\n"); |
9a9a54ad AG |
356 | goto rtc_alarm_handled; |
357 | } | |
358 | ||
c8d523a4 SV |
359 | ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR; |
360 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg); | |
5d7dc4cf | 361 | if (rc) |
5bed811d | 362 | dev_err(rtc_dd->rtc_dev, |
c8d523a4 | 363 | "Write to RTC Alarm control2 register failed\n"); |
9a9a54ad AG |
364 | |
365 | rtc_alarm_handled: | |
366 | return IRQ_HANDLED; | |
367 | } | |
368 | ||
c8d523a4 SV |
369 | static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd) |
370 | { | |
371 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; | |
372 | unsigned int ctrl_reg; | |
373 | int rc; | |
374 | ||
375 | /* Check if the RTC is on, else turn it on */ | |
376 | rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg); | |
377 | if (rc) | |
378 | return rc; | |
379 | ||
380 | if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) { | |
381 | ctrl_reg |= PM8xxx_RTC_ENABLE; | |
382 | rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); | |
383 | if (rc) | |
384 | return rc; | |
385 | } | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | static const struct pm8xxx_rtc_regs pm8921_regs = { | |
391 | .ctrl = 0x11d, | |
392 | .write = 0x11f, | |
393 | .read = 0x123, | |
394 | .alarm_rw = 0x127, | |
395 | .alarm_ctrl = 0x11d, | |
396 | .alarm_ctrl2 = 0x11e, | |
397 | .alarm_en = BIT(1), | |
398 | }; | |
399 | ||
400 | static const struct pm8xxx_rtc_regs pm8058_regs = { | |
401 | .ctrl = 0x1e8, | |
402 | .write = 0x1ea, | |
403 | .read = 0x1ee, | |
404 | .alarm_rw = 0x1f2, | |
405 | .alarm_ctrl = 0x1e8, | |
406 | .alarm_ctrl2 = 0x1e9, | |
407 | .alarm_en = BIT(1), | |
408 | }; | |
409 | ||
410 | static const struct pm8xxx_rtc_regs pm8941_regs = { | |
411 | .ctrl = 0x6046, | |
412 | .write = 0x6040, | |
413 | .read = 0x6048, | |
414 | .alarm_rw = 0x6140, | |
415 | .alarm_ctrl = 0x6146, | |
416 | .alarm_ctrl2 = 0x6148, | |
417 | .alarm_en = BIT(7), | |
418 | }; | |
419 | ||
5a418558 JC |
420 | /* |
421 | * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out | |
422 | */ | |
423 | static const struct of_device_id pm8xxx_id_table[] = { | |
c8d523a4 | 424 | { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs }, |
08655bca | 425 | { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs }, |
c8d523a4 SV |
426 | { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs }, |
427 | { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs }, | |
5a418558 JC |
428 | { }, |
429 | }; | |
430 | MODULE_DEVICE_TABLE(of, pm8xxx_id_table); | |
431 | ||
5a167f45 | 432 | static int pm8xxx_rtc_probe(struct platform_device *pdev) |
9a9a54ad AG |
433 | { |
434 | int rc; | |
9a9a54ad | 435 | struct pm8xxx_rtc *rtc_dd; |
5a418558 | 436 | const struct of_device_id *match; |
9a9a54ad | 437 | |
5a418558 JC |
438 | match = of_match_node(pm8xxx_id_table, pdev->dev.of_node); |
439 | if (!match) | |
440 | return -ENXIO; | |
9a9a54ad | 441 | |
c417299c | 442 | rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL); |
49ae425b | 443 | if (rtc_dd == NULL) |
9a9a54ad | 444 | return -ENOMEM; |
9a9a54ad AG |
445 | |
446 | /* Initialise spinlock to protect RTC control register */ | |
447 | spin_lock_init(&rtc_dd->ctrl_reg_lock); | |
448 | ||
5d7dc4cf JC |
449 | rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
450 | if (!rtc_dd->regmap) { | |
451 | dev_err(&pdev->dev, "Parent regmap unavailable.\n"); | |
452 | return -ENXIO; | |
453 | } | |
454 | ||
9a9a54ad AG |
455 | rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0); |
456 | if (rtc_dd->rtc_alarm_irq < 0) { | |
457 | dev_err(&pdev->dev, "Alarm IRQ resource absent!\n"); | |
c417299c | 458 | return -ENXIO; |
9a9a54ad AG |
459 | } |
460 | ||
5a418558 JC |
461 | rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node, |
462 | "allow-set-time"); | |
9a9a54ad | 463 | |
c8d523a4 | 464 | rtc_dd->regs = match->data; |
9a9a54ad AG |
465 | rtc_dd->rtc_dev = &pdev->dev; |
466 | ||
c8d523a4 SV |
467 | rc = pm8xxx_rtc_enable(rtc_dd); |
468 | if (rc) | |
c417299c | 469 | return rc; |
9a9a54ad AG |
470 | |
471 | platform_set_drvdata(pdev, rtc_dd); | |
472 | ||
fda9909d JC |
473 | device_init_wakeup(&pdev->dev, 1); |
474 | ||
9a9a54ad | 475 | /* Register the RTC device */ |
c417299c | 476 | rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc", |
5bed811d | 477 | &pm8xxx_rtc_ops, THIS_MODULE); |
9a9a54ad AG |
478 | if (IS_ERR(rtc_dd->rtc)) { |
479 | dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n", | |
5bed811d | 480 | __func__, PTR_ERR(rtc_dd->rtc)); |
c417299c | 481 | return PTR_ERR(rtc_dd->rtc); |
9a9a54ad AG |
482 | } |
483 | ||
484 | /* Request the alarm IRQ */ | |
bffcbc08 JC |
485 | rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq, |
486 | pm8xxx_alarm_trigger, | |
487 | IRQF_TRIGGER_RISING, | |
488 | "pm8xxx_rtc_alarm", rtc_dd); | |
9a9a54ad AG |
489 | if (rc < 0) { |
490 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc); | |
c417299c | 491 | return rc; |
9a9a54ad AG |
492 | } |
493 | ||
9a9a54ad AG |
494 | dev_dbg(&pdev->dev, "Probe success !!\n"); |
495 | ||
496 | return 0; | |
9a9a54ad AG |
497 | } |
498 | ||
9a9a54ad AG |
499 | #ifdef CONFIG_PM_SLEEP |
500 | static int pm8xxx_rtc_resume(struct device *dev) | |
501 | { | |
502 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
503 | ||
504 | if (device_may_wakeup(dev)) | |
505 | disable_irq_wake(rtc_dd->rtc_alarm_irq); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int pm8xxx_rtc_suspend(struct device *dev) | |
511 | { | |
512 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
513 | ||
514 | if (device_may_wakeup(dev)) | |
515 | enable_irq_wake(rtc_dd->rtc_alarm_irq); | |
516 | ||
517 | return 0; | |
518 | } | |
519 | #endif | |
520 | ||
5bed811d JC |
521 | static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops, |
522 | pm8xxx_rtc_suspend, | |
523 | pm8xxx_rtc_resume); | |
9a9a54ad AG |
524 | |
525 | static struct platform_driver pm8xxx_rtc_driver = { | |
526 | .probe = pm8xxx_rtc_probe, | |
9a9a54ad | 527 | .driver = { |
5a418558 | 528 | .name = "rtc-pm8xxx", |
5a418558 JC |
529 | .pm = &pm8xxx_rtc_pm_ops, |
530 | .of_match_table = pm8xxx_id_table, | |
9a9a54ad AG |
531 | }, |
532 | }; | |
533 | ||
0c4eae66 | 534 | module_platform_driver(pm8xxx_rtc_driver); |
9a9a54ad AG |
535 | |
536 | MODULE_ALIAS("platform:rtc-pm8xxx"); | |
537 | MODULE_DESCRIPTION("PMIC8xxx RTC driver"); | |
538 | MODULE_LICENSE("GPL v2"); | |
539 | MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>"); |