[linux-2.6-block.git] / drivers / rtc / rtc-pm8xxx.c

/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/of.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

/* RTC Register offsets from RTC CTRL REG */
#define PM8XXX_ALARM_CTRL_OFFSET	0x01
#define PM8XXX_RTC_WRITE_OFFSET		0x02
#define PM8XXX_RTC_READ_OFFSET		0x06
#define PM8XXX_ALARM_RW_OFFSET		0x0A

/* RTC_CTRL register bit fields */
#define PM8xxx_RTC_ENABLE		BIT(7)
#define PM8xxx_RTC_ALARM_CLEAR		BIT(0)

#define NUM_8_BIT_RTC_REGS		0x4

/**
 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
 * @ctrl: base address of control register
 * @write: base address of write register
 * @read: base address of read register
 * @alarm_ctrl: base address of alarm control register
 * @alarm_ctrl2: base address of alarm control2 register
 * @alarm_rw: base address of alarm read-write register
 * @alarm_en: alarm enable mask
 */
struct pm8xxx_rtc_regs {
	unsigned int ctrl;
	unsigned int write;
	unsigned int read;
	unsigned int alarm_ctrl;
	unsigned int alarm_ctrl2;
	unsigned int alarm_rw;
	unsigned int alarm_en;
};

/**
 * struct pm8xxx_rtc -  rtc driver internal structure
 * @rtc:		rtc device for this driver.
 * @regmap:		regmap used to access RTC registers
 * @allow_set_time:	indicates whether writing to the RTC is allowed
 * @rtc_alarm_irq:	rtc alarm irq number.
 * @ctrl_reg:		rtc control register.
 * @rtc_dev:		device structure.
 * @ctrl_reg_lock:	spinlock protecting access to ctrl_reg.
 */
struct pm8xxx_rtc {
	struct rtc_device *rtc;
	struct regmap *regmap;
	bool allow_set_time;
	int rtc_alarm_irq;
	const struct pm8xxx_rtc_regs *regs;
	struct device *rtc_dev;
	spinlock_t ctrl_reg_lock;
};

/*
 * Steps to write the RTC registers.
 * 1. Disable alarm if enabled.
 * 2. Disable rtc if enabled.
 * 3. Write 0x00 to LSB.
 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
 * 5. Enable rtc if disabled in step 2.
 * 6. Enable alarm if disabled in step 1.
 */
static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	int rc, i;
	unsigned long secs, irq_flags;
	u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
	unsigned int ctrl_reg, rtc_ctrl_reg;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;

	if (!rtc_dd->allow_set_time)
		return -EACCES;

	rtc_tm_to_time(tm, &secs);

	dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);

	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
		value[i] = secs & 0xFF;
		secs >>= 8;
	}

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
	if (rc)
		goto rtc_rw_fail;

	if (ctrl_reg & regs->alarm_en) {
		alarm_enabled = 1;
		ctrl_reg &= ~regs->alarm_en;
		rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
		if (rc) {
			dev_err(dev, "Write to RTC Alarm control register failed\n");
			goto rtc_rw_fail;
		}
	}

	/* Disable RTC H/w before writing on RTC register */
	rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
	if (rc)
		goto rtc_rw_fail;

	if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
		rtc_disabled = 1;
		rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
		rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
		if (rc) {
			dev_err(dev, "Write to RTC control register failed\n");
			goto rtc_rw_fail;
		}
	}

	/* Write 0 to Byte[0] */
	rc = regmap_write(rtc_dd->regmap, regs->write, 0);
	if (rc) {
		dev_err(dev, "Write to RTC write data register failed\n");
		goto rtc_rw_fail;
	}

	/* Write Byte[1], Byte[2], Byte[3] */
	rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
			       &value[1], sizeof(value) - 1);
	if (rc) {
		dev_err(dev, "Write to RTC write data register failed\n");
		goto rtc_rw_fail;
	}

	/* Write Byte[0] */
	rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
	if (rc) {
		dev_err(dev, "Write to RTC write data register failed\n");
		goto rtc_rw_fail;
	}

	/* Enable RTC H/w after writing on RTC register */
	if (rtc_disabled) {
		rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
		rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
		if (rc) {
			dev_err(dev, "Write to RTC control register failed\n");
			goto rtc_rw_fail;
		}
	}

	if (alarm_enabled) {
		ctrl_reg |= regs->alarm_en;
		rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
		if (rc) {
			dev_err(dev, "Write to RTC Alarm control register failed\n");
			goto rtc_rw_fail;
		}
	}

rtc_rw_fail:
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);

	return rc;
}

static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	int rc;
	u8 value[NUM_8_BIT_RTC_REGS];
	unsigned long secs;
	unsigned int reg;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;

	rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
	if (rc) {
		dev_err(dev, "RTC read data register failed\n");
		return rc;
	}

	/*
	 * Read the LSB again and check if there has been a carry over.
	 * If there is, redo the read operation.
	 */
	rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
	if (rc < 0) {
		dev_err(dev, "RTC read data register failed\n");
		return rc;
	}

	if (unlikely(reg < value[0])) {
		rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
				      value, sizeof(value));
		if (rc) {
			dev_err(dev, "RTC read data register failed\n");
			return rc;
		}
	}

	secs = value[0] | (value[1] << 8) | (value[2] << 16) |
	       ((unsigned long)value[3] << 24);

	rtc_time_to_tm(secs, tm);

	dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);

	return 0;
}

static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	int rc, i;
	u8 value[NUM_8_BIT_RTC_REGS];
	unsigned int ctrl_reg;
	unsigned long secs, irq_flags;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;

	rtc_tm_to_time(&alarm->time, &secs);

	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
		value[i] = secs & 0xFF;
		secs >>= 8;
	}

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

	rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
			       sizeof(value));
	if (rc) {
		dev_err(dev, "Write to RTC ALARM register failed\n");
		goto rtc_rw_fail;
	}

	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
	if (rc)
		goto rtc_rw_fail;

	if (alarm->enabled)
		ctrl_reg |= regs->alarm_en;
	else
		ctrl_reg &= ~regs->alarm_en;

	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
	if (rc) {
		dev_err(dev, "Write to RTC alarm control register failed\n");
		goto rtc_rw_fail;
	}

	dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
		&alarm->time, &alarm->time);
rtc_rw_fail:
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	return rc;
}

static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	int rc;
	u8 value[NUM_8_BIT_RTC_REGS];
	unsigned long secs;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;

	rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
			      sizeof(value));
	if (rc) {
		dev_err(dev, "RTC alarm time read failed\n");
		return rc;
	}

	secs = value[0] | (value[1] << 8) | (value[2] << 16) |
	       ((unsigned long)value[3] << 24);

	rtc_time_to_tm(secs, &alarm->time);

	rc = rtc_valid_tm(&alarm->time);
	if (rc < 0) {
		dev_err(dev, "Invalid alarm time read from RTC\n");
		return rc;
	}

	dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
		&alarm->time, &alarm->time);

	return 0;
}

static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	int rc;
	unsigned long irq_flags;
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
	unsigned int ctrl_reg;

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
	if (rc)
		goto rtc_rw_fail;

	if (enable)
		ctrl_reg |= regs->alarm_en;
	else
		ctrl_reg &= ~regs->alarm_en;

	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
	if (rc) {
		dev_err(dev, "Write to RTC control register failed\n");
		goto rtc_rw_fail;
	}

rtc_rw_fail:
	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	return rc;
}

static const struct rtc_class_ops pm8xxx_rtc_ops = {
	.read_time	= pm8xxx_rtc_read_time,
	.set_time	= pm8xxx_rtc_set_time,
	.set_alarm	= pm8xxx_rtc_set_alarm,
	.read_alarm	= pm8xxx_rtc_read_alarm,
	.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
};

static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
{
	struct pm8xxx_rtc *rtc_dd = dev_id;
	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
	unsigned int ctrl_reg;
	int rc;
	unsigned long irq_flags;

	rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);

	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);

	/* Clear the alarm enable bit */
	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
	if (rc) {
		spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
		goto rtc_alarm_handled;
	}

	ctrl_reg &= ~regs->alarm_en;

	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
	if (rc) {
		spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
		dev_err(rtc_dd->rtc_dev,
			"Write to alarm control register failed\n");
		goto rtc_alarm_handled;
	}

	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);

	/* Clear RTC alarm register */
	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
	if (rc) {
		dev_err(rtc_dd->rtc_dev,
			"RTC Alarm control2 register read failed\n");
		goto rtc_alarm_handled;
	}

	ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
	if (rc)
		dev_err(rtc_dd->rtc_dev,
			"Write to RTC Alarm control2 register failed\n");

rtc_alarm_handled:
	return IRQ_HANDLED;
}

static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
{
	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
	unsigned int ctrl_reg;
	int rc;

	/* Check if the RTC is on, else turn it on */
	rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
	if (rc)
		return rc;

	if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
		ctrl_reg |= PM8xxx_RTC_ENABLE;
		rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
		if (rc)
			return rc;
	}

	return 0;
}

static const struct pm8xxx_rtc_regs pm8921_regs = {
	.ctrl		= 0x11d,
	.write		= 0x11f,
	.read		= 0x123,
	.alarm_rw	= 0x127,
	.alarm_ctrl	= 0x11d,
	.alarm_ctrl2	= 0x11e,
	.alarm_en	= BIT(1),
};

static const struct pm8xxx_rtc_regs pm8058_regs = {
	.ctrl		= 0x1e8,
	.write		= 0x1ea,
	.read		= 0x1ee,
	.alarm_rw	= 0x1f2,
	.alarm_ctrl	= 0x1e8,
	.alarm_ctrl2	= 0x1e9,
	.alarm_en	= BIT(1),
};

static const struct pm8xxx_rtc_regs pm8941_regs = {
	.ctrl		= 0x6046,
	.write		= 0x6040,
	.read		= 0x6048,
	.alarm_rw	= 0x6140,
	.alarm_ctrl	= 0x6146,
	.alarm_ctrl2	= 0x6148,
	.alarm_en	= BIT(7),
};

/*
 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
 */
static const struct of_device_id pm8xxx_id_table[] = {
	{ .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
	{ .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
	{ .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
	{ .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
	{ },
};
MODULE_DEVICE_TABLE(of, pm8xxx_id_table);

static int pm8xxx_rtc_probe(struct platform_device *pdev)
{
	int rc;
	struct pm8xxx_rtc *rtc_dd;
	const struct of_device_id *match;

	match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
	if (!match)
		return -ENXIO;

	rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
	if (rtc_dd == NULL)
		return -ENOMEM;

	/* Initialise spinlock to protect RTC control register */
	spin_lock_init(&rtc_dd->ctrl_reg_lock);

	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	if (!rtc_dd->regmap) {
		dev_err(&pdev->dev, "Parent regmap unavailable.\n");
		return -ENXIO;
	}

	rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
	if (rtc_dd->rtc_alarm_irq < 0) {
		dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
		return -ENXIO;
	}

	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
						      "allow-set-time");

	rtc_dd->regs = match->data;
	rtc_dd->rtc_dev = &pdev->dev;

	rc = pm8xxx_rtc_enable(rtc_dd);
	if (rc)
		return rc;

	platform_set_drvdata(pdev, rtc_dd);

	device_init_wakeup(&pdev->dev, 1);

	/* Register the RTC device */
	rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
					       &pm8xxx_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc_dd->rtc)) {
		dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
			__func__, PTR_ERR(rtc_dd->rtc));
		return PTR_ERR(rtc_dd->rtc);
	}

	/* Request the alarm IRQ */
	rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
					  pm8xxx_alarm_trigger,
					  IRQF_TRIGGER_RISING,
					  "pm8xxx_rtc_alarm", rtc_dd);
	if (rc < 0) {
		dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
		return rc;
	}

	dev_dbg(&pdev->dev, "Probe success !!\n");

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int pm8xxx_rtc_resume(struct device *dev)
{
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(rtc_dd->rtc_alarm_irq);

	return 0;
}

static int pm8xxx_rtc_suspend(struct device *dev)
{
	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(rtc_dd->rtc_alarm_irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
			 pm8xxx_rtc_suspend,
			 pm8xxx_rtc_resume);

static struct platform_driver pm8xxx_rtc_driver = {
	.probe		= pm8xxx_rtc_probe,
	.driver	= {
		.name		= "rtc-pm8xxx",
		.pm		= &pm8xxx_rtc_pm_ops,
		.of_match_table	= pm8xxx_id_table,
	},
};

module_platform_driver(pm8xxx_rtc_driver);

MODULE_ALIAS("platform:rtc-pm8xxx");
MODULE_DESCRIPTION("PMIC8xxx RTC driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
Commit	Line	Data
9a9a54ad AG	1	/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*/
5a418558	12	#include <linux/of.h>
9a9a54ad AG	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/rtc.h>
5d7dc4cf	16	#include <linux/platform_device.h>
9a9a54ad	17	#include <linux/pm.h>
5d7dc4cf	18	#include <linux/regmap.h>
9a9a54ad AG	19	#include <linux/slab.h>
	20	#include <linux/spinlock.h>
	21
9a9a54ad AG	22	/* RTC Register offsets from RTC CTRL REG */
	23	#define PM8XXX_ALARM_CTRL_OFFSET 0x01
	24	#define PM8XXX_RTC_WRITE_OFFSET 0x02
	25	#define PM8XXX_RTC_READ_OFFSET 0x06
	26	#define PM8XXX_ALARM_RW_OFFSET 0x0A
	27
	28	/* RTC_CTRL register bit fields */
	29	#define PM8xxx_RTC_ENABLE BIT(7)
9a9a54ad AG	30	#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
	31
	32	#define NUM_8_BIT_RTC_REGS 0x4
	33
c8d523a4 SV	34	/**
	35	* struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
	36	* @ctrl: base address of control register
	37	* @write: base address of write register
	38	* @read: base address of read register
	39	* @alarm_ctrl: base address of alarm control register
	40	* @alarm_ctrl2: base address of alarm control2 register
	41	* @alarm_rw: base address of alarm read-write register
	42	* @alarm_en: alarm enable mask
	43	*/
	44	struct pm8xxx_rtc_regs {
	45	unsigned int ctrl;
	46	unsigned int write;
	47	unsigned int read;
	48	unsigned int alarm_ctrl;
	49	unsigned int alarm_ctrl2;
	50	unsigned int alarm_rw;
	51	unsigned int alarm_en;
	52	};
	53
9a9a54ad AG	54	/**
	55	* struct pm8xxx_rtc - rtc driver internal structure
	56	* @rtc: rtc device for this driver.
5d7dc4cf	57	* @regmap: regmap used to access RTC registers
5a418558	58	* @allow_set_time: indicates whether writing to the RTC is allowed
9a9a54ad	59	* @rtc_alarm_irq: rtc alarm irq number.
9a9a54ad AG	60	* @ctrl_reg: rtc control register.
	61	* @rtc_dev: device structure.
	62	* @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
	63	*/
	64	struct pm8xxx_rtc {
	65	struct rtc_device *rtc;
5d7dc4cf	66	struct regmap *regmap;
5a418558	67	bool allow_set_time;
9a9a54ad	68	int rtc_alarm_irq;
c8d523a4	69	const struct pm8xxx_rtc_regs *regs;
9a9a54ad AG	70	struct device *rtc_dev;
	71	spinlock_t ctrl_reg_lock;
	72	};
	73
9a9a54ad AG	74	/*
	75	* Steps to write the RTC registers.
	76	* 1. Disable alarm if enabled.
83220bf3 MA	77	* 2. Disable rtc if enabled.
	78	* 3. Write 0x00 to LSB.
	79	* 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
	80	* 5. Enable rtc if disabled in step 2.
	81	* 6. Enable alarm if disabled in step 1.
9a9a54ad AG	82	*/
	83	static int pm8xxx_rtc_set_time(struct device dev, struct rtc_time tm)
	84	{
	85	int rc, i;
	86	unsigned long secs, irq_flags;
83220bf3 MA	87	u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
83220bf3 MA	88	unsigned int ctrl_reg, rtc_ctrl_reg;
9a9a54ad	89	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
c8d523a4	90	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
9a9a54ad	91
5a418558 JC	92	if (!rtc_dd->allow_set_time)
	93	return -EACCES;
	94
9a9a54ad AG	95	rtc_tm_to_time(tm, &secs);
9a9a54ad AG	96
83220bf3 MA	97	dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
83220bf3 MA	98
9a9a54ad AG	99	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
	100	value[i] = secs & 0xFF;
	101	secs >>= 8;
	102	}
	103
9a9a54ad	104	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
9a9a54ad	105
83220bf3	106	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
c8d523a4 SV	107	if (rc)
	108	goto rtc_rw_fail;
	109
	110	if (ctrl_reg & regs->alarm_en) {
9a9a54ad	111	alarm_enabled = 1;
c8d523a4	112	ctrl_reg &= ~regs->alarm_en;
83220bf3 MA	113	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
	114	if (rc) {
	115	dev_err(dev, "Write to RTC Alarm control register failed\n");
	116	goto rtc_rw_fail;
	117	}
	118	}
	119
	120	/* Disable RTC H/w before writing on RTC register */
	121	rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
	122	if (rc)
	123	goto rtc_rw_fail;
	124
	125	if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
	126	rtc_disabled = 1;
	127	rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
	128	rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
5d7dc4cf	129	if (rc) {
5bed811d	130	dev_err(dev, "Write to RTC control register failed\n");
9a9a54ad AG	131	goto rtc_rw_fail;
9a9a54ad AG	132	}
5bed811d	133	}
9a9a54ad AG	134
9a9a54ad AG	135	/* Write 0 to Byte[0] */
c8d523a4	136	rc = regmap_write(rtc_dd->regmap, regs->write, 0);
5d7dc4cf	137	if (rc) {
9a9a54ad AG	138	dev_err(dev, "Write to RTC write data register failed\n");
	139	goto rtc_rw_fail;
	140	}
	141
	142	/* Write Byte[1], Byte[2], Byte[3] */
c8d523a4	143	rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
5d7dc4cf JC	144	&value[1], sizeof(value) - 1);
5d7dc4cf JC	145	if (rc) {
9a9a54ad AG	146	dev_err(dev, "Write to RTC write data register failed\n");
	147	goto rtc_rw_fail;
	148	}
	149
	150	/* Write Byte[0] */
c8d523a4	151	rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
5d7dc4cf	152	if (rc) {
9a9a54ad AG	153	dev_err(dev, "Write to RTC write data register failed\n");
	154	goto rtc_rw_fail;
	155	}
	156
83220bf3 MA	157	/* Enable RTC H/w after writing on RTC register */
	158	if (rtc_disabled) {
	159	rtc_ctrl_reg \|= PM8xxx_RTC_ENABLE;
	160	rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
	161	if (rc) {
	162	dev_err(dev, "Write to RTC control register failed\n");
	163	goto rtc_rw_fail;
	164	}
	165	}
	166
9a9a54ad	167	if (alarm_enabled) {
c8d523a4	168	ctrl_reg \|= regs->alarm_en;
83220bf3	169	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
5d7dc4cf	170	if (rc) {
83220bf3	171	dev_err(dev, "Write to RTC Alarm control register failed\n");
9a9a54ad AG	172	goto rtc_rw_fail;
9a9a54ad AG	173	}
9a9a54ad AG	174	}
	175
	176	rtc_rw_fail:
c8d523a4	177	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
9a9a54ad AG	178
	179	return rc;
	180	}
	181
	182	static int pm8xxx_rtc_read_time(struct device dev, struct rtc_time tm)
	183	{
	184	int rc;
5d7dc4cf	185	u8 value[NUM_8_BIT_RTC_REGS];
9a9a54ad	186	unsigned long secs;
5d7dc4cf	187	unsigned int reg;
9a9a54ad	188	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
c8d523a4	189	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
9a9a54ad	190
c8d523a4	191	rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
5d7dc4cf	192	if (rc) {
9a9a54ad AG	193	dev_err(dev, "RTC read data register failed\n");
	194	return rc;
	195	}
	196
	197	/*
	198	* Read the LSB again and check if there has been a carry over.
	199	* If there is, redo the read operation.
	200	*/
c8d523a4	201	rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
9a9a54ad AG	202	if (rc < 0) {
	203	dev_err(dev, "RTC read data register failed\n");
	204	return rc;
	205	}
	206
	207	if (unlikely(reg < value[0])) {
c8d523a4	208	rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
5d7dc4cf JC	209	value, sizeof(value));
5d7dc4cf JC	210	if (rc) {
9a9a54ad AG	211	dev_err(dev, "RTC read data register failed\n");
	212	return rc;
	213	}
	214	}
	215
e4228088 CIK	216	secs = value[0] \| (value[1] << 8) \| (value[2] << 16) \|
e4228088 CIK	217	((unsigned long)value[3] << 24);
9a9a54ad AG	218
	219	rtc_time_to_tm(secs, tm);
	220
4f5ef6ee	221	dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
9a9a54ad AG	222
	223	return 0;
	224	}
	225
	226	static int pm8xxx_rtc_set_alarm(struct device dev, struct rtc_wkalrm alarm)
	227	{
	228	int rc, i;
c8d523a4 SV	229	u8 value[NUM_8_BIT_RTC_REGS];
c8d523a4 SV	230	unsigned int ctrl_reg;
9a9a54ad AG	231	unsigned long secs, irq_flags;
9a9a54ad AG	232	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
c8d523a4	233	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
9a9a54ad AG	234
	235	rtc_tm_to_time(&alarm->time, &secs);
	236
	237	for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
	238	value[i] = secs & 0xFF;
	239	secs >>= 8;
	240	}
	241
	242	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
	243
c8d523a4	244	rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
5d7dc4cf JC	245	sizeof(value));
5d7dc4cf JC	246	if (rc) {
9a9a54ad AG	247	dev_err(dev, "Write to RTC ALARM register failed\n");
	248	goto rtc_rw_fail;
	249	}
	250
c8d523a4 SV	251	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
	252	if (rc)
	253	goto rtc_rw_fail;
5bed811d JC	254
5bed811d JC	255	if (alarm->enabled)
c8d523a4	256	ctrl_reg \|= regs->alarm_en;
5bed811d	257	else
c8d523a4	258	ctrl_reg &= ~regs->alarm_en;
9a9a54ad	259
c8d523a4	260	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
5d7dc4cf	261	if (rc) {
c8d523a4	262	dev_err(dev, "Write to RTC alarm control register failed\n");
9a9a54ad AG	263	goto rtc_rw_fail;
	264	}
	265
4f5ef6ee AS	266	dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
4f5ef6ee AS	267	&alarm->time, &alarm->time);
9a9a54ad AG	268	rtc_rw_fail:
	269	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	270	return rc;
	271	}
	272
	273	static int pm8xxx_rtc_read_alarm(struct device dev, struct rtc_wkalrm alarm)
	274	{
	275	int rc;
	276	u8 value[NUM_8_BIT_RTC_REGS];
	277	unsigned long secs;
	278	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
c8d523a4	279	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
9a9a54ad	280
c8d523a4	281	rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
5d7dc4cf JC	282	sizeof(value));
5d7dc4cf JC	283	if (rc) {
9a9a54ad AG	284	dev_err(dev, "RTC alarm time read failed\n");
	285	return rc;
	286	}
	287
e4228088 CIK	288	secs = value[0] \| (value[1] << 8) \| (value[2] << 16) \|
e4228088 CIK	289	((unsigned long)value[3] << 24);
9a9a54ad AG	290
	291	rtc_time_to_tm(secs, &alarm->time);
	292
	293	rc = rtc_valid_tm(&alarm->time);
	294	if (rc < 0) {
	295	dev_err(dev, "Invalid alarm time read from RTC\n");
	296	return rc;
	297	}
	298
4f5ef6ee AS	299	dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
4f5ef6ee AS	300	&alarm->time, &alarm->time);
9a9a54ad AG	301
	302	return 0;
	303	}
	304
	305	static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	306	{
	307	int rc;
	308	unsigned long irq_flags;
	309	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
c8d523a4 SV	310	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
c8d523a4 SV	311	unsigned int ctrl_reg;
9a9a54ad AG	312
9a9a54ad AG	313	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
5bed811d	314
c8d523a4 SV	315	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
	316	if (rc)
	317	goto rtc_rw_fail;
5bed811d JC	318
5bed811d JC	319	if (enable)
c8d523a4	320	ctrl_reg \|= regs->alarm_en;
5bed811d	321	else
c8d523a4	322	ctrl_reg &= ~regs->alarm_en;
9a9a54ad	323
c8d523a4	324	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
5d7dc4cf	325	if (rc) {
9a9a54ad AG	326	dev_err(dev, "Write to RTC control register failed\n");
	327	goto rtc_rw_fail;
	328	}
	329
9a9a54ad AG	330	rtc_rw_fail:
	331	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	332	return rc;
	333	}
	334
5a418558	335	static const struct rtc_class_ops pm8xxx_rtc_ops = {
9a9a54ad	336	.read_time = pm8xxx_rtc_read_time,
5a418558	337	.set_time = pm8xxx_rtc_set_time,
9a9a54ad AG	338	.set_alarm = pm8xxx_rtc_set_alarm,
	339	.read_alarm = pm8xxx_rtc_read_alarm,
	340	.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
	341	};
	342
	343	static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
	344	{
	345	struct pm8xxx_rtc *rtc_dd = dev_id;
c8d523a4	346	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
5d7dc4cf	347	unsigned int ctrl_reg;
9a9a54ad AG	348	int rc;
	349	unsigned long irq_flags;
	350
	351	rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF \| RTC_AF);
	352
	353	spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
	354
	355	/* Clear the alarm enable bit */
c8d523a4 SV	356	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
	357	if (rc) {
	358	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	359	goto rtc_alarm_handled;
	360	}
	361
	362	ctrl_reg &= ~regs->alarm_en;
9a9a54ad	363
c8d523a4	364	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
5d7dc4cf	365	if (rc) {
9a9a54ad	366	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
5bed811d	367	dev_err(rtc_dd->rtc_dev,
c8d523a4	368	"Write to alarm control register failed\n");
9a9a54ad AG	369	goto rtc_alarm_handled;
	370	}
	371
9a9a54ad AG	372	spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
	373
	374	/* Clear RTC alarm register */
c8d523a4	375	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
5d7dc4cf	376	if (rc) {
5bed811d	377	dev_err(rtc_dd->rtc_dev,
c8d523a4	378	"RTC Alarm control2 register read failed\n");
9a9a54ad AG	379	goto rtc_alarm_handled;
	380	}
	381
c8d523a4 SV	382	ctrl_reg \|= PM8xxx_RTC_ALARM_CLEAR;
c8d523a4 SV	383	rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
5d7dc4cf	384	if (rc)
5bed811d	385	dev_err(rtc_dd->rtc_dev,
c8d523a4	386	"Write to RTC Alarm control2 register failed\n");
9a9a54ad AG	387
	388	rtc_alarm_handled:
	389	return IRQ_HANDLED;
	390	}
	391
c8d523a4 SV	392	static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
	393	{
	394	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
	395	unsigned int ctrl_reg;
	396	int rc;
	397
	398	/* Check if the RTC is on, else turn it on */
	399	rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
	400	if (rc)
	401	return rc;
	402
	403	if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
	404	ctrl_reg \|= PM8xxx_RTC_ENABLE;
	405	rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
	406	if (rc)
	407	return rc;
	408	}
	409
	410	return 0;
	411	}
	412
	413	static const struct pm8xxx_rtc_regs pm8921_regs = {
	414	.ctrl = 0x11d,
	415	.write = 0x11f,
	416	.read = 0x123,
	417	.alarm_rw = 0x127,
	418	.alarm_ctrl = 0x11d,
	419	.alarm_ctrl2 = 0x11e,
	420	.alarm_en = BIT(1),
	421	};
	422
	423	static const struct pm8xxx_rtc_regs pm8058_regs = {
	424	.ctrl = 0x1e8,
	425	.write = 0x1ea,
	426	.read = 0x1ee,
	427	.alarm_rw = 0x1f2,
	428	.alarm_ctrl = 0x1e8,
	429	.alarm_ctrl2 = 0x1e9,
	430	.alarm_en = BIT(1),
	431	};
	432
	433	static const struct pm8xxx_rtc_regs pm8941_regs = {
	434	.ctrl = 0x6046,
	435	.write = 0x6040,
	436	.read = 0x6048,
	437	.alarm_rw = 0x6140,
	438	.alarm_ctrl = 0x6146,
	439	.alarm_ctrl2 = 0x6148,
	440	.alarm_en = BIT(7),
	441	};
	442
5a418558 JC	443	/*
	444	* Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
	445	*/
	446	static const struct of_device_id pm8xxx_id_table[] = {
c8d523a4	447	{ .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
08655bca	448	{ .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
c8d523a4 SV	449	{ .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
c8d523a4 SV	450	{ .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
5a418558 JC	451	{ },
	452	};
	453	MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
	454
5a167f45	455	static int pm8xxx_rtc_probe(struct platform_device *pdev)
9a9a54ad AG	456	{
9a9a54ad AG	457	int rc;
9a9a54ad	458	struct pm8xxx_rtc *rtc_dd;
5a418558	459	const struct of_device_id *match;
9a9a54ad	460
5a418558 JC	461	match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
	462	if (!match)
	463	return -ENXIO;
9a9a54ad	464
c417299c	465	rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
49ae425b	466	if (rtc_dd == NULL)
9a9a54ad	467	return -ENOMEM;
9a9a54ad AG	468
	469	/* Initialise spinlock to protect RTC control register */
	470	spin_lock_init(&rtc_dd->ctrl_reg_lock);
	471
5d7dc4cf JC	472	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	473	if (!rtc_dd->regmap) {
	474	dev_err(&pdev->dev, "Parent regmap unavailable.\n");
	475	return -ENXIO;
	476	}
	477
9a9a54ad AG	478	rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
	479	if (rtc_dd->rtc_alarm_irq < 0) {
	480	dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
c417299c	481	return -ENXIO;
9a9a54ad AG	482	}
9a9a54ad AG	483
5a418558 JC	484	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
5a418558 JC	485	"allow-set-time");
9a9a54ad	486
c8d523a4	487	rtc_dd->regs = match->data;
9a9a54ad AG	488	rtc_dd->rtc_dev = &pdev->dev;
9a9a54ad AG	489
c8d523a4 SV	490	rc = pm8xxx_rtc_enable(rtc_dd);
c8d523a4 SV	491	if (rc)
c417299c	492	return rc;
9a9a54ad AG	493
	494	platform_set_drvdata(pdev, rtc_dd);
	495
fda9909d JC	496	device_init_wakeup(&pdev->dev, 1);
fda9909d JC	497
9a9a54ad	498	/* Register the RTC device */
c417299c	499	rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
5bed811d	500	&pm8xxx_rtc_ops, THIS_MODULE);
9a9a54ad AG	501	if (IS_ERR(rtc_dd->rtc)) {
9a9a54ad AG	502	dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
5bed811d	503	__func__, PTR_ERR(rtc_dd->rtc));
c417299c	504	return PTR_ERR(rtc_dd->rtc);
9a9a54ad AG	505	}
	506
	507	/* Request the alarm IRQ */
bffcbc08 JC	508	rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
	509	pm8xxx_alarm_trigger,
	510	IRQF_TRIGGER_RISING,
	511	"pm8xxx_rtc_alarm", rtc_dd);
9a9a54ad AG	512	if (rc < 0) {
9a9a54ad AG	513	dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
c417299c	514	return rc;
9a9a54ad AG	515	}
9a9a54ad AG	516
9a9a54ad AG	517	dev_dbg(&pdev->dev, "Probe success !!\n");
	518
	519	return 0;
9a9a54ad AG	520	}
9a9a54ad AG	521
9a9a54ad AG	522	#ifdef CONFIG_PM_SLEEP
	523	static int pm8xxx_rtc_resume(struct device *dev)
	524	{
	525	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	526
	527	if (device_may_wakeup(dev))
	528	disable_irq_wake(rtc_dd->rtc_alarm_irq);
	529
	530	return 0;
	531	}
	532
	533	static int pm8xxx_rtc_suspend(struct device *dev)
	534	{
	535	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
	536
	537	if (device_may_wakeup(dev))
	538	enable_irq_wake(rtc_dd->rtc_alarm_irq);
	539
	540	return 0;
	541	}
	542	#endif
	543
5bed811d JC	544	static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
	545	pm8xxx_rtc_suspend,
	546	pm8xxx_rtc_resume);
9a9a54ad AG	547
	548	static struct platform_driver pm8xxx_rtc_driver = {
	549	.probe = pm8xxx_rtc_probe,
9a9a54ad	550	.driver = {
5a418558	551	.name = "rtc-pm8xxx",
5a418558 JC	552	.pm = &pm8xxx_rtc_pm_ops,
5a418558 JC	553	.of_match_table = pm8xxx_id_table,
9a9a54ad AG	554	},
	555	};
	556
0c4eae66	557	module_platform_driver(pm8xxx_rtc_driver);
9a9a54ad AG	558
	559	MODULE_ALIAS("platform:rtc-pm8xxx");
	560	MODULE_DESCRIPTION("PMIC8xxx RTC driver");
	561	MODULE_LICENSE("GPL v2");
	562	MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");