[linux-2.6-block.git] / drivers / rtc / rtc-pl031.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/rtc/rtc-pl031.c
 *
 * Real Time Clock interface for ARM AMBA PrimeCell 031 RTC
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright 2006 (c) MontaVista Software, Inc.
 *
 * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
 * Copyright 2010 (c) ST-Ericsson AB
 */
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/io.h>
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/pm_wakeirq.h>
#include <linux/slab.h>

/*
 * Register definitions
 */
#define	RTC_DR		0x00	/* Data read register */
#define	RTC_MR		0x04	/* Match register */
#define	RTC_LR		0x08	/* Data load register */
#define	RTC_CR		0x0c	/* Control register */
#define	RTC_IMSC	0x10	/* Interrupt mask and set register */
#define	RTC_RIS		0x14	/* Raw interrupt status register */
#define	RTC_MIS		0x18	/* Masked interrupt status register */
#define	RTC_ICR		0x1c	/* Interrupt clear register */
/* ST variants have additional timer functionality */
#define RTC_TDR		0x20	/* Timer data read register */
#define RTC_TLR		0x24	/* Timer data load register */
#define RTC_TCR		0x28	/* Timer control register */
#define RTC_YDR		0x30	/* Year data read register */
#define RTC_YMR		0x34	/* Year match register */
#define RTC_YLR		0x38	/* Year data load register */

#define RTC_CR_EN	(1 << 0)	/* counter enable bit */
#define RTC_CR_CWEN	(1 << 26)	/* Clockwatch enable bit */

#define RTC_TCR_EN	(1 << 1) /* Periodic timer enable bit */

/* Common bit definitions for Interrupt status and control registers */
#define RTC_BIT_AI	(1 << 0) /* Alarm interrupt bit */
#define RTC_BIT_PI	(1 << 1) /* Periodic interrupt bit. ST variants only. */

/* Common bit definations for ST v2 for reading/writing time */
#define RTC_SEC_SHIFT 0
#define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */
#define RTC_MIN_SHIFT 6
#define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */
#define RTC_HOUR_SHIFT 12
#define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */
#define RTC_WDAY_SHIFT 17
#define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */
#define RTC_MDAY_SHIFT 20
#define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */
#define RTC_MON_SHIFT 25
#define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */

#define RTC_TIMER_FREQ 32768

/**
 * struct pl031_vendor_data - per-vendor variations
 * @ops: the vendor-specific operations used on this silicon version
 * @clockwatch: if this is an ST Microelectronics silicon version with a
 *	clockwatch function
 * @st_weekday: if this is an ST Microelectronics silicon version that need
 *	the weekday fix
 * @irqflags: special IRQ flags per variant
 */
struct pl031_vendor_data {
	struct rtc_class_ops ops;
	bool clockwatch;
	bool st_weekday;
	unsigned long irqflags;
	time64_t range_min;
	timeu64_t range_max;
};

struct pl031_local {
	struct pl031_vendor_data *vendor;
	struct rtc_device *rtc;
	void __iomem *base;
};

static int pl031_alarm_irq_enable(struct device *dev,
	unsigned int enabled)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);
	unsigned long imsc;

	/* Clear any pending alarm interrupts. */
	writel(RTC_BIT_AI, ldata->base + RTC_ICR);

	imsc = readl(ldata->base + RTC_IMSC);

	if (enabled == 1)
		writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC);
	else
		writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);

	return 0;
}

/*
 * Convert Gregorian date to ST v2 RTC format.
 */
static int pl031_stv2_tm_to_time(struct device *dev,
				 struct rtc_time *tm, unsigned long *st_time,
	unsigned long *bcd_year)
{
	int year = tm->tm_year + 1900;
	int wday = tm->tm_wday;

	/* wday masking is not working in hardware so wday must be valid */
	if (wday < -1 || wday > 6) {
		dev_err(dev, "invalid wday value %d\n", tm->tm_wday);
		return -EINVAL;
	} else if (wday == -1) {
		/* wday is not provided, calculate it here */
		struct rtc_time calc_tm;

		rtc_time64_to_tm(rtc_tm_to_time64(tm), &calc_tm);
		wday = calc_tm.tm_wday;
	}

	*bcd_year = (bin2bcd(year % 100) | bin2bcd(year / 100) << 8);

	*st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT)
			|	(tm->tm_mday << RTC_MDAY_SHIFT)
			|	((wday + 1) << RTC_WDAY_SHIFT)
			|	(tm->tm_hour << RTC_HOUR_SHIFT)
			|	(tm->tm_min << RTC_MIN_SHIFT)
			|	(tm->tm_sec << RTC_SEC_SHIFT);

	return 0;
}

/*
 * Convert ST v2 RTC format to Gregorian date.
 */
static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year,
	struct rtc_time *tm)
{
	tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100);
	tm->tm_mon  = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1;
	tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT);
	tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1;
	tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT);
	tm->tm_min  = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT);
	tm->tm_sec  = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT);

	tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
	tm->tm_year -= 1900;

	return 0;
}

static int pl031_stv2_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);

	pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR),
			readl(ldata->base + RTC_YDR), tm);

	return 0;
}

static int pl031_stv2_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned long time;
	unsigned long bcd_year;
	struct pl031_local *ldata = dev_get_drvdata(dev);
	int ret;

	ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year);
	if (ret == 0) {
		writel(bcd_year, ldata->base + RTC_YLR);
		writel(time, ldata->base + RTC_LR);
	}

	return ret;
}

static int pl031_stv2_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);
	int ret;

	ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR),
			readl(ldata->base + RTC_YMR), &alarm->time);

	alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
	alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;

	return ret;
}

static int pl031_stv2_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);
	unsigned long time;
	unsigned long bcd_year;
	int ret;

	ret = pl031_stv2_tm_to_time(dev, &alarm->time,
				    &time, &bcd_year);
	if (ret == 0) {
		writel(bcd_year, ldata->base + RTC_YMR);
		writel(time, ldata->base + RTC_MR);

		pl031_alarm_irq_enable(dev, alarm->enabled);
	}

	return ret;
}

static irqreturn_t pl031_interrupt(int irq, void *dev_id)
{
	struct pl031_local *ldata = dev_id;
	unsigned long rtcmis;
	unsigned long events = 0;

	rtcmis = readl(ldata->base + RTC_MIS);
	if (rtcmis & RTC_BIT_AI) {
		writel(RTC_BIT_AI, ldata->base + RTC_ICR);
		events |= (RTC_AF | RTC_IRQF);
		rtc_update_irq(ldata->rtc, 1, events);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int pl031_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);

	rtc_time64_to_tm(readl(ldata->base + RTC_DR), tm);

	return 0;
}

static int pl031_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);

	writel(rtc_tm_to_time64(tm), ldata->base + RTC_LR);

	return 0;
}

static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);

	rtc_time64_to_tm(readl(ldata->base + RTC_MR), &alarm->time);

	alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
	alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;

	return 0;
}

static int pl031_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
	struct pl031_local *ldata = dev_get_drvdata(dev);

	writel(rtc_tm_to_time64(&alarm->time), ldata->base + RTC_MR);
	pl031_alarm_irq_enable(dev, alarm->enabled);

	return 0;
}

static int pl031_remove(struct amba_device *adev)
{
	struct pl031_local *ldata = dev_get_drvdata(&adev->dev);

	dev_pm_clear_wake_irq(&adev->dev);
	device_init_wakeup(&adev->dev, false);
	if (adev->irq[0])
		free_irq(adev->irq[0], ldata);
	amba_release_regions(adev);

	return 0;
}

static int pl031_probe(struct amba_device *adev, const struct amba_id *id)
{
	int ret;
	struct pl031_local *ldata;
	struct pl031_vendor_data *vendor = id->data;
	struct rtc_class_ops *ops;
	unsigned long time, data;

	ret = amba_request_regions(adev, NULL);
	if (ret)
		goto err_req;

	ldata = devm_kzalloc(&adev->dev, sizeof(struct pl031_local),
			     GFP_KERNEL);
	ops = devm_kmemdup(&adev->dev, &vendor->ops, sizeof(vendor->ops),
			   GFP_KERNEL);
	if (!ldata || !ops) {
		ret = -ENOMEM;
		goto out;
	}

	ldata->vendor = vendor;
	ldata->base = devm_ioremap(&adev->dev, adev->res.start,
				   resource_size(&adev->res));
	if (!ldata->base) {
		ret = -ENOMEM;
		goto out;
	}

	amba_set_drvdata(adev, ldata);

	dev_dbg(&adev->dev, "designer ID = 0x%02x\n", amba_manf(adev));
	dev_dbg(&adev->dev, "revision = 0x%01x\n", amba_rev(adev));

	data = readl(ldata->base + RTC_CR);
	/* Enable the clockwatch on ST Variants */
	if (vendor->clockwatch)
		data |= RTC_CR_CWEN;
	else
		data |= RTC_CR_EN;
	writel(data, ldata->base + RTC_CR);

	/*
	 * On ST PL031 variants, the RTC reset value does not provide correct
	 * weekday for 2000-01-01. Correct the erroneous sunday to saturday.
	 */
	if (vendor->st_weekday) {
		if (readl(ldata->base + RTC_YDR) == 0x2000) {
			time = readl(ldata->base + RTC_DR);
			if ((time &
			     (RTC_MON_MASK | RTC_MDAY_MASK | RTC_WDAY_MASK))
			    == 0x02120000) {
				time = time | (0x7 << RTC_WDAY_SHIFT);
				writel(0x2000, ldata->base + RTC_YLR);
				writel(time, ldata->base + RTC_LR);
			}
		}
	}

	if (!adev->irq[0]) {
		/* When there's no interrupt, no point in exposing the alarm */
		ops->read_alarm = NULL;
		ops->set_alarm = NULL;
		ops->alarm_irq_enable = NULL;
	}

	device_init_wakeup(&adev->dev, true);
	ldata->rtc = devm_rtc_allocate_device(&adev->dev);
	if (IS_ERR(ldata->rtc))
		return PTR_ERR(ldata->rtc);

	ldata->rtc->ops = ops;
	ldata->rtc->range_min = vendor->range_min;
	ldata->rtc->range_max = vendor->range_max;

	ret = rtc_register_device(ldata->rtc);
	if (ret)
		goto out;

	if (adev->irq[0]) {
		ret = request_irq(adev->irq[0], pl031_interrupt,
				  vendor->irqflags, "rtc-pl031", ldata);
		if (ret)
			goto out;
		dev_pm_set_wake_irq(&adev->dev, adev->irq[0]);
	}
	return 0;

out:
	amba_release_regions(adev);
err_req:

	return ret;
}

/* Operations for the original ARM version */
static struct pl031_vendor_data arm_pl031 = {
	.ops = {
		.read_time = pl031_read_time,
		.set_time = pl031_set_time,
		.read_alarm = pl031_read_alarm,
		.set_alarm = pl031_set_alarm,
		.alarm_irq_enable = pl031_alarm_irq_enable,
	},
	.range_max = U32_MAX,
};

/* The First ST derivative */
static struct pl031_vendor_data stv1_pl031 = {
	.ops = {
		.read_time = pl031_read_time,
		.set_time = pl031_set_time,
		.read_alarm = pl031_read_alarm,
		.set_alarm = pl031_set_alarm,
		.alarm_irq_enable = pl031_alarm_irq_enable,
	},
	.clockwatch = true,
	.st_weekday = true,
	.range_max = U32_MAX,
};

/* And the second ST derivative */
static struct pl031_vendor_data stv2_pl031 = {
	.ops = {
		.read_time = pl031_stv2_read_time,
		.set_time = pl031_stv2_set_time,
		.read_alarm = pl031_stv2_read_alarm,
		.set_alarm = pl031_stv2_set_alarm,
		.alarm_irq_enable = pl031_alarm_irq_enable,
	},
	.clockwatch = true,
	.st_weekday = true,
	/*
	 * This variant shares the IRQ with another block and must not
	 * suspend that IRQ line.
	 * TODO check if it shares with IRQF_NO_SUSPEND user, else we can
	 * remove IRQF_COND_SUSPEND
	 */
	.irqflags = IRQF_SHARED | IRQF_COND_SUSPEND,
	.range_min = RTC_TIMESTAMP_BEGIN_0000,
	.range_max = RTC_TIMESTAMP_END_9999,
};

static const struct amba_id pl031_ids[] = {
	{
		.id = 0x00041031,
		.mask = 0x000fffff,
		.data = &arm_pl031,
	},
	/* ST Micro variants */
	{
		.id = 0x00180031,
		.mask = 0x00ffffff,
		.data = &stv1_pl031,
	},
	{
		.id = 0x00280031,
		.mask = 0x00ffffff,
		.data = &stv2_pl031,
	},
	{0, 0},
};

MODULE_DEVICE_TABLE(amba, pl031_ids);

static struct amba_driver pl031_driver = {
	.drv = {
		.name = "rtc-pl031",
	},
	.id_table = pl031_ids,
	.probe = pl031_probe,
	.remove = pl031_remove,
};

module_amba_driver(pl031_driver);

MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
MODULE_DESCRIPTION("ARM AMBA PL031 RTC Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
8ae6e163 DS	2	/*
	3	* drivers/rtc/rtc-pl031.c
	4	*
	5	* Real Time Clock interface for ARM AMBA PrimeCell 031 RTC
	6	*
	7	* Author: Deepak Saxena <dsaxena@plexity.net>
	8	*
	9	* Copyright 2006 (c) MontaVista Software, Inc.
	10	*
c72881e8 LW	11	* Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
c72881e8 LW	12	* Copyright 2010 (c) ST-Ericsson AB
8ae6e163	13	*/
8ae6e163 DS	14	#include <linux/module.h>
	15	#include <linux/rtc.h>
	16	#include <linux/init.h>
8ae6e163	17	#include <linux/interrupt.h>
8ae6e163	18	#include <linux/amba/bus.h>
2dba8518	19	#include <linux/io.h>
c72881e8 LW	20	#include <linux/bcd.h>
c72881e8 LW	21	#include <linux/delay.h>
eff6dd41	22	#include <linux/pm_wakeirq.h>
5a0e3ad6	23	#include <linux/slab.h>
8ae6e163 DS	24
	25	/*
	26	* Register definitions
	27	*/
	28	#define RTC_DR 0x00 /* Data read register */
	29	#define RTC_MR 0x04 /* Match register */
	30	#define RTC_LR 0x08 /* Data load register */
	31	#define RTC_CR 0x0c /* Control register */
	32	#define RTC_IMSC 0x10 /* Interrupt mask and set register */
	33	#define RTC_RIS 0x14 /* Raw interrupt status register */
	34	#define RTC_MIS 0x18 /* Masked interrupt status register */
	35	#define RTC_ICR 0x1c /* Interrupt clear register */
c72881e8 LW	36	/* ST variants have additional timer functionality */
	37	#define RTC_TDR 0x20 /* Timer data read register */
	38	#define RTC_TLR 0x24 /* Timer data load register */
	39	#define RTC_TCR 0x28 /* Timer control register */
	40	#define RTC_YDR 0x30 /* Year data read register */
	41	#define RTC_YMR 0x34 /* Year match register */
	42	#define RTC_YLR 0x38 /* Year data load register */
	43
e7e034e1	44	#define RTC_CR_EN (1 << 0) /* counter enable bit */
c72881e8 LW	45	#define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */
	46
	47	#define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */
	48
	49	/* Common bit definitions for Interrupt status and control registers */
	50	#define RTC_BIT_AI (1 << 0) /* Alarm interrupt bit */
	51	#define RTC_BIT_PI (1 << 1) /* Periodic interrupt bit. ST variants only. */
	52
	53	/* Common bit definations for ST v2 for reading/writing time */
	54	#define RTC_SEC_SHIFT 0
	55	#define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */
	56	#define RTC_MIN_SHIFT 6
	57	#define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */
	58	#define RTC_HOUR_SHIFT 12
	59	#define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */
	60	#define RTC_WDAY_SHIFT 17
	61	#define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */
	62	#define RTC_MDAY_SHIFT 20
	63	#define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */
	64	#define RTC_MON_SHIFT 25
	65	#define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */
	66
	67	#define RTC_TIMER_FREQ 32768
8ae6e163	68
aff05ed5 LW	69	/**
	70	* struct pl031_vendor_data - per-vendor variations
	71	* @ops: the vendor-specific operations used on this silicon version
1bb457fc LW	72	* @clockwatch: if this is an ST Microelectronics silicon version with a
	73	* clockwatch function
	74	* @st_weekday: if this is an ST Microelectronics silicon version that need
	75	* the weekday fix
559a6fc0	76	* @irqflags: special IRQ flags per variant
aff05ed5 LW	77	*/
	78	struct pl031_vendor_data {
	79	struct rtc_class_ops ops;
1bb457fc LW	80	bool clockwatch;
1bb457fc LW	81	bool st_weekday;
559a6fc0	82	unsigned long irqflags;
03f2a0e4 AB	83	time64_t range_min;
03f2a0e4 AB	84	timeu64_t range_max;
aff05ed5 LW	85	};
aff05ed5 LW	86
8ae6e163	87	struct pl031_local {
aff05ed5	88	struct pl031_vendor_data *vendor;
8ae6e163 DS	89	struct rtc_device *rtc;
	90	void __iomem *base;
	91	};
	92
c72881e8 LW	93	static int pl031_alarm_irq_enable(struct device *dev,
	94	unsigned int enabled)
	95	{
	96	struct pl031_local *ldata = dev_get_drvdata(dev);
	97	unsigned long imsc;
	98
	99	/* Clear any pending alarm interrupts. */
	100	writel(RTC_BIT_AI, ldata->base + RTC_ICR);
	101
	102	imsc = readl(ldata->base + RTC_IMSC);
	103
	104	if (enabled == 1)
	105	writel(imsc \| RTC_BIT_AI, ldata->base + RTC_IMSC);
	106	else
	107	writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);
	108
	109	return 0;
	110	}
	111
	112	/*
	113	* Convert Gregorian date to ST v2 RTC format.
	114	*/
	115	static int pl031_stv2_tm_to_time(struct device *dev,
	116	struct rtc_time tm, unsigned long st_time,
	117	unsigned long *bcd_year)
	118	{
	119	int year = tm->tm_year + 1900;
	120	int wday = tm->tm_wday;
	121
	122	/* wday masking is not working in hardware so wday must be valid */
	123	if (wday < -1 \|\| wday > 6) {
	124	dev_err(dev, "invalid wday value %d\n", tm->tm_wday);
	125	return -EINVAL;
	126	} else if (wday == -1) {
	127	/* wday is not provided, calculate it here */
c72881e8 LW	128	struct rtc_time calc_tm;
c72881e8 LW	129
c8ff5841	130	rtc_time64_to_tm(rtc_tm_to_time64(tm), &calc_tm);
c72881e8 LW	131	wday = calc_tm.tm_wday;
	132	}
	133
	134	*bcd_year = (bin2bcd(year % 100) \| bin2bcd(year / 100) << 8);
	135
	136	*st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT)
	137	\| (tm->tm_mday << RTC_MDAY_SHIFT)
	138	\| ((wday + 1) << RTC_WDAY_SHIFT)
	139	\| (tm->tm_hour << RTC_HOUR_SHIFT)
	140	\| (tm->tm_min << RTC_MIN_SHIFT)
	141	\| (tm->tm_sec << RTC_SEC_SHIFT);
	142
	143	return 0;
	144	}
	145
	146	/*
	147	* Convert ST v2 RTC format to Gregorian date.
	148	*/
	149	static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year,
	150	struct rtc_time *tm)
	151	{
	152	tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100);
	153	tm->tm_mon = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1;
	154	tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT);
	155	tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1;
	156	tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT);
	157	tm->tm_min = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT);
	158	tm->tm_sec = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT);
	159
	160	tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
	161	tm->tm_year -= 1900;
	162
	163	return 0;
	164	}
	165
	166	static int pl031_stv2_read_time(struct device dev, struct rtc_time tm)
	167	{
	168	struct pl031_local *ldata = dev_get_drvdata(dev);
	169
	170	pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR),
	171	readl(ldata->base + RTC_YDR), tm);
	172
	173	return 0;
	174	}
	175
	176	static int pl031_stv2_set_time(struct device dev, struct rtc_time tm)
	177	{
	178	unsigned long time;
	179	unsigned long bcd_year;
	180	struct pl031_local *ldata = dev_get_drvdata(dev);
	181	int ret;
	182
	183	ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year);
	184	if (ret == 0) {
	185	writel(bcd_year, ldata->base + RTC_YLR);
	186	writel(time, ldata->base + RTC_LR);
	187	}
	188
	189	return ret;
	190	}
	191
	192	static int pl031_stv2_read_alarm(struct device dev, struct rtc_wkalrm alarm)
8ae6e163	193	{
c72881e8 LW	194	struct pl031_local *ldata = dev_get_drvdata(dev);
c72881e8 LW	195	int ret;
8ae6e163	196
c72881e8 LW	197	ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR),
c72881e8 LW	198	readl(ldata->base + RTC_YMR), &alarm->time);
8ae6e163	199
c72881e8 LW	200	alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
	201	alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
	202
	203	return ret;
8ae6e163 DS	204	}
8ae6e163 DS	205
c72881e8	206	static int pl031_stv2_set_alarm(struct device dev, struct rtc_wkalrm alarm)
8ae6e163 DS	207	{
8ae6e163 DS	208	struct pl031_local *ldata = dev_get_drvdata(dev);
c72881e8 LW	209	unsigned long time;
	210	unsigned long bcd_year;
	211	int ret;
	212
61c9fbff AB	213	ret = pl031_stv2_tm_to_time(dev, &alarm->time,
61c9fbff AB	214	&time, &bcd_year);
c72881e8	215	if (ret == 0) {
61c9fbff AB	216	writel(bcd_year, ldata->base + RTC_YMR);
	217	writel(time, ldata->base + RTC_MR);
	218
	219	pl031_alarm_irq_enable(dev, alarm->enabled);
c72881e8 LW	220	}
	221
	222	return ret;
	223	}
	224
	225	static irqreturn_t pl031_interrupt(int irq, void *dev_id)
	226	{
	227	struct pl031_local *ldata = dev_id;
	228	unsigned long rtcmis;
	229	unsigned long events = 0;
	230
	231	rtcmis = readl(ldata->base + RTC_MIS);
ac2dee59 RK	232	if (rtcmis & RTC_BIT_AI) {
	233	writel(RTC_BIT_AI, ldata->base + RTC_ICR);
	234	events \|= (RTC_AF \| RTC_IRQF);
c72881e8	235	rtc_update_irq(ldata->rtc, 1, events);
8ae6e163	236
c72881e8	237	return IRQ_HANDLED;
8ae6e163 DS	238	}
8ae6e163 DS	239
c72881e8	240	return IRQ_NONE;
8ae6e163 DS	241	}
	242
	243	static int pl031_read_time(struct device dev, struct rtc_time tm)
	244	{
	245	struct pl031_local *ldata = dev_get_drvdata(dev);
	246
c8ff5841	247	rtc_time64_to_tm(readl(ldata->base + RTC_DR), tm);
8ae6e163 DS	248
	249	return 0;
	250	}
	251
	252	static int pl031_set_time(struct device dev, struct rtc_time tm)
	253	{
8ae6e163 DS	254	struct pl031_local *ldata = dev_get_drvdata(dev);
8ae6e163 DS	255
c8ff5841	256	writel(rtc_tm_to_time64(tm), ldata->base + RTC_LR);
c72881e8	257
c8ff5841	258	return 0;
8ae6e163 DS	259	}
	260
	261	static int pl031_read_alarm(struct device dev, struct rtc_wkalrm alarm)
	262	{
	263	struct pl031_local *ldata = dev_get_drvdata(dev);
	264
c8ff5841	265	rtc_time64_to_tm(readl(ldata->base + RTC_MR), &alarm->time);
c72881e8 LW	266
	267	alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
	268	alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
8ae6e163 DS	269
	270	return 0;
	271	}
	272
	273	static int pl031_set_alarm(struct device dev, struct rtc_wkalrm alarm)
	274	{
	275	struct pl031_local *ldata = dev_get_drvdata(dev);
c72881e8	276
c8ff5841	277	writel(rtc_tm_to_time64(&alarm->time), ldata->base + RTC_MR);
4df2ef85	278	pl031_alarm_irq_enable(dev, alarm->enabled);
c72881e8	279
c8ff5841	280	return 0;
c72881e8 LW	281	}
c72881e8 LW	282
8ae6e163 DS	283	static int pl031_remove(struct amba_device *adev)
	284	{
	285	struct pl031_local *ldata = dev_get_drvdata(&adev->dev);
	286
eff6dd41 SH	287	dev_pm_clear_wake_irq(&adev->dev);
eff6dd41 SH	288	device_init_wakeup(&adev->dev, false);
5b64a296 RK	289	if (adev->irq[0])
5b64a296 RK	290	free_irq(adev->irq[0], ldata);
2dba8518	291	amba_release_regions(adev);
8ae6e163 DS	292
	293	return 0;
	294	}
	295
aa25afad	296	static int pl031_probe(struct amba_device adev, const struct amba_id id)
8ae6e163 DS	297	{
	298	int ret;
	299	struct pl031_local *ldata;
aff05ed5	300	struct pl031_vendor_data *vendor = id->data;
b86f581f	301	struct rtc_class_ops *ops;
e7e034e1	302	unsigned long time, data;
8ae6e163	303
2dba8518 RK	304	ret = amba_request_regions(adev, NULL);
	305	if (ret)
	306	goto err_req;
8ae6e163	307
273c868e RK	308	ldata = devm_kzalloc(&adev->dev, sizeof(struct pl031_local),
273c868e RK	309	GFP_KERNEL);
b86f581f RK	310	ops = devm_kmemdup(&adev->dev, &vendor->ops, sizeof(vendor->ops),
	311	GFP_KERNEL);
	312	if (!ldata \|\| !ops) {
8ae6e163 DS	313	ret = -ENOMEM;
	314	goto out;
	315	}
8ae6e163	316
b86f581f	317	ldata->vendor = vendor;
273c868e RK	318	ldata->base = devm_ioremap(&adev->dev, adev->res.start,
273c868e RK	319	resource_size(&adev->res));
8ae6e163 DS	320	if (!ldata->base) {
8ae6e163 DS	321	ret = -ENOMEM;
273c868e	322	goto out;
8ae6e163 DS	323	}
8ae6e163 DS	324
2dba8518 RK	325	amba_set_drvdata(adev, ldata);
2dba8518 RK	326
1bb457fc LW	327	dev_dbg(&adev->dev, "designer ID = 0x%02x\n", amba_manf(adev));
1bb457fc LW	328	dev_dbg(&adev->dev, "revision = 0x%01x\n", amba_rev(adev));
8ae6e163	329
e7e034e1	330	data = readl(ldata->base + RTC_CR);
c72881e8	331	/* Enable the clockwatch on ST Variants */
1bb457fc	332	if (vendor->clockwatch)
e7e034e1	333	data \|= RTC_CR_CWEN;
3399cfb5 LW	334	else
	335	data \|= RTC_CR_EN;
	336	writel(data, ldata->base + RTC_CR);
c72881e8	337
c0a5f4a0 RK	338	/*
	339	* On ST PL031 variants, the RTC reset value does not provide correct
	340	* weekday for 2000-01-01. Correct the erroneous sunday to saturday.
	341	*/
1bb457fc	342	if (vendor->st_weekday) {
c0a5f4a0 RK	343	if (readl(ldata->base + RTC_YDR) == 0x2000) {
	344	time = readl(ldata->base + RTC_DR);
	345	if ((time &
	346	(RTC_MON_MASK \| RTC_MDAY_MASK \| RTC_WDAY_MASK))
	347	== 0x02120000) {
	348	time = time \| (0x7 << RTC_WDAY_SHIFT);
	349	writel(0x2000, ldata->base + RTC_YLR);
	350	writel(time, ldata->base + RTC_LR);
	351	}
	352	}
	353	}
	354
b86f581f RK	355	if (!adev->irq[0]) {
	356	/* When there's no interrupt, no point in exposing the alarm */
	357	ops->read_alarm = NULL;
	358	ops->set_alarm = NULL;
	359	ops->alarm_irq_enable = NULL;
	360	}
	361
eff6dd41	362	device_init_wakeup(&adev->dev, true);
b7aff107 AB	363	ldata->rtc = devm_rtc_allocate_device(&adev->dev);
	364	if (IS_ERR(ldata->rtc))
	365	return PTR_ERR(ldata->rtc);
	366
	367	ldata->rtc->ops = ops;
03f2a0e4 AB	368	ldata->rtc->range_min = vendor->range_min;
03f2a0e4 AB	369	ldata->rtc->range_max = vendor->range_max;
b7aff107 AB	370
	371	ret = rtc_register_device(ldata->rtc);
	372	if (ret)
273c868e	373	goto out;
8ae6e163	374
5b64a296 RK	375	if (adev->irq[0]) {
	376	ret = request_irq(adev->irq[0], pl031_interrupt,
	377	vendor->irqflags, "rtc-pl031", ldata);
	378	if (ret)
b7aff107	379	goto out;
5b64a296	380	dev_pm_set_wake_irq(&adev->dev, adev->irq[0]);
c72881e8	381	}
8ae6e163 DS	382	return 0;
8ae6e163 DS	383
8ae6e163	384	out:
2dba8518 RK	385	amba_release_regions(adev);
2dba8518 RK	386	err_req:
c72881e8	387
8ae6e163 DS	388	return ret;
	389	}
	390
c72881e8	391	/* Operations for the original ARM version */
aff05ed5 LW	392	static struct pl031_vendor_data arm_pl031 = {
	393	.ops = {
	394	.read_time = pl031_read_time,
	395	.set_time = pl031_set_time,
	396	.read_alarm = pl031_read_alarm,
	397	.set_alarm = pl031_set_alarm,
	398	.alarm_irq_enable = pl031_alarm_irq_enable,
	399	},
03f2a0e4	400	.range_max = U32_MAX,
c72881e8 LW	401	};
	402
	403	/* The First ST derivative */
aff05ed5 LW	404	static struct pl031_vendor_data stv1_pl031 = {
	405	.ops = {
	406	.read_time = pl031_read_time,
	407	.set_time = pl031_set_time,
	408	.read_alarm = pl031_read_alarm,
	409	.set_alarm = pl031_set_alarm,
	410	.alarm_irq_enable = pl031_alarm_irq_enable,
	411	},
1bb457fc LW	412	.clockwatch = true,
1bb457fc LW	413	.st_weekday = true,
03f2a0e4	414	.range_max = U32_MAX,
c72881e8 LW	415	};
	416
	417	/* And the second ST derivative */
aff05ed5 LW	418	static struct pl031_vendor_data stv2_pl031 = {
	419	.ops = {
	420	.read_time = pl031_stv2_read_time,
	421	.set_time = pl031_stv2_set_time,
	422	.read_alarm = pl031_stv2_read_alarm,
	423	.set_alarm = pl031_stv2_set_alarm,
	424	.alarm_irq_enable = pl031_alarm_irq_enable,
	425	},
1bb457fc LW	426	.clockwatch = true,
1bb457fc LW	427	.st_weekday = true,
559a6fc0 MW	428	/*
	429	* This variant shares the IRQ with another block and must not
	430	* suspend that IRQ line.
eff6dd41 SH	431	* TODO check if it shares with IRQF_NO_SUSPEND user, else we can
eff6dd41 SH	432	* remove IRQF_COND_SUSPEND
559a6fc0	433	*/
eff6dd41	434	.irqflags = IRQF_SHARED \| IRQF_COND_SUSPEND,
03f2a0e4 AB	435	.range_min = RTC_TIMESTAMP_BEGIN_0000,
03f2a0e4 AB	436	.range_max = RTC_TIMESTAMP_END_9999,
c72881e8 LW	437	};
c72881e8 LW	438
eb508b36	439	static const struct amba_id pl031_ids[] = {
8ae6e163	440	{
2934d6a8 LW	441	.id = 0x00041031,
2934d6a8 LW	442	.mask = 0x000fffff,
aff05ed5	443	.data = &arm_pl031,
c72881e8 LW	444	},
	445	/* ST Micro variants */
	446	{
	447	.id = 0x00180031,
	448	.mask = 0x00ffffff,
aff05ed5	449	.data = &stv1_pl031,
c72881e8 LW	450	},
	451	{
	452	.id = 0x00280031,
	453	.mask = 0x00ffffff,
aff05ed5	454	.data = &stv2_pl031,
2934d6a8	455	},
8ae6e163 DS	456	{0, 0},
	457	};
	458
f5feac2a DM	459	MODULE_DEVICE_TABLE(amba, pl031_ids);
f5feac2a DM	460
8ae6e163 DS	461	static struct amba_driver pl031_driver = {
	462	.drv = {
	463	.name = "rtc-pl031",
	464	},
	465	.id_table = pl031_ids,
	466	.probe = pl031_probe,
	467	.remove = pl031_remove,
	468	};
	469
9e5ed094	470	module_amba_driver(pl031_driver);
8ae6e163	471
27675ef0	472	MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
8ae6e163 DS	473	MODULE_DESCRIPTION("ARM AMBA PL031 RTC Driver");
8ae6e163 DS	474	MODULE_LICENSE("GPL");