[linux-2.6-block.git] / drivers / rtc / rtc-pcf85063.c

// SPDX-License-Identifier: GPL-2.0
/*
 * An I2C driver for the PCF85063 RTC
 * Copyright 2014 Rose Technology
 *
 * Author: Søren Andersen <san@rosetechnology.dk>
 * Maintainers: http://www.nslu2-linux.org/
 *
 * Copyright (C) 2019 Micro Crystal AG
 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
 */
#include <linux/clk-provider.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>

/*
 * Information for this driver was pulled from the following datasheets.
 *
 *  https://www.nxp.com/documents/data_sheet/PCF85063A.pdf
 *  https://www.nxp.com/documents/data_sheet/PCF85063TP.pdf
 *
 *  PCF85063A -- Rev. 6 — 18 November 2015
 *  PCF85063TP -- Rev. 4 — 6 May 2015
 *
 *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
 *  RV8263 -- Rev. 1.0 — January 2019
 */

#define PCF85063_REG_CTRL1		0x00 /* status */
#define PCF85063_REG_CTRL1_CAP_SEL	BIT(0)
#define PCF85063_REG_CTRL1_STOP		BIT(5)

#define PCF85063_REG_CTRL2		0x01
#define PCF85063_CTRL2_AF		BIT(6)
#define PCF85063_CTRL2_AIE		BIT(7)

#define PCF85063_REG_OFFSET		0x02
#define PCF85063_OFFSET_SIGN_BIT	6	/* 2's complement sign bit */
#define PCF85063_OFFSET_MODE		BIT(7)
#define PCF85063_OFFSET_STEP0		4340
#define PCF85063_OFFSET_STEP1		4069

#define PCF85063_REG_CLKO_F_MASK	0x07 /* frequency mask */
#define PCF85063_REG_CLKO_F_32768HZ	0x00
#define PCF85063_REG_CLKO_F_OFF		0x07

#define PCF85063_REG_RAM		0x03

#define PCF85063_REG_SC			0x04 /* datetime */
#define PCF85063_REG_SC_OS		0x80

#define PCF85063_REG_ALM_S		0x0b
#define PCF85063_AEN			BIT(7)

struct pcf85063_config {
	struct regmap_config regmap;
	unsigned has_alarms:1;
	unsigned force_cap_7000:1;
};

struct pcf85063 {
	struct rtc_device	*rtc;
	struct regmap		*regmap;
#ifdef CONFIG_COMMON_CLK
	struct clk_hw		clkout_hw;
#endif
};

static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int rc;
	u8 regs[7];

	/*
	 * while reading, the time/date registers are blocked and not updated
	 * anymore until the access is finished. To not lose a second
	 * event, the access must be finished within one second. So, read all
	 * time/date registers in one turn.
	 */
	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
			      sizeof(regs));
	if (rc)
		return rc;

	/* if the clock has lost its power it makes no sense to use its time */
	if (regs[0] & PCF85063_REG_SC_OS) {
		dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
		return -EINVAL;
	}

	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
	tm->tm_min = bcd2bin(regs[1] & 0x7F);
	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
	tm->tm_wday = regs[4] & 0x07;
	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
	tm->tm_year = bcd2bin(regs[6]);
	tm->tm_year += 100;

	return 0;
}

static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int rc;
	u8 regs[7];

	/*
	 * to accurately set the time, reset the divider chain and keep it in
	 * reset state until all time/date registers are written
	 */
	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				PCF85063_REG_CTRL1_STOP,
				PCF85063_REG_CTRL1_STOP);
	if (rc)
		return rc;

	/* hours, minutes and seconds */
	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */

	regs[1] = bin2bcd(tm->tm_min);
	regs[2] = bin2bcd(tm->tm_hour);

	/* Day of month, 1 - 31 */
	regs[3] = bin2bcd(tm->tm_mday);

	/* Day, 0 - 6 */
	regs[4] = tm->tm_wday & 0x07;

	/* month, 1 - 12 */
	regs[5] = bin2bcd(tm->tm_mon + 1);

	/* year and century */
	regs[6] = bin2bcd(tm->tm_year - 100);

	/* write all registers at once */
	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
			       regs, sizeof(regs));
	if (rc)
		return rc;

	/*
	 * Write the control register as a separate action since the size of
	 * the register space is different between the PCF85063TP and
	 * PCF85063A devices.  The rollover point can not be used.
	 */
	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				  PCF85063_REG_CTRL1_STOP, 0);
}

static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	u8 buf[4];
	unsigned int val;
	int ret;

	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
			       buf, sizeof(buf));
	if (ret)
		return ret;

	alrm->time.tm_sec = bcd2bin(buf[0]);
	alrm->time.tm_min = bcd2bin(buf[1]);
	alrm->time.tm_hour = bcd2bin(buf[2]);
	alrm->time.tm_mday = bcd2bin(buf[3]);

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	if (ret)
		return ret;

	alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);

	return 0;
}

static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	u8 buf[5];
	int ret;

	buf[0] = bin2bcd(alrm->time.tm_sec);
	buf[1] = bin2bcd(alrm->time.tm_min);
	buf[2] = bin2bcd(alrm->time.tm_hour);
	buf[3] = bin2bcd(alrm->time.tm_mday);
	buf[4] = PCF85063_AEN; /* Do not match on week day */

	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
	if (ret)
		return ret;

	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
				buf, sizeof(buf));
	if (ret)
		return ret;

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
				  alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
}

static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
					 unsigned int enabled)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				  PCF85063_CTRL2_AIE,
				  enabled ? PCF85063_CTRL2_AIE : 0);
}

static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
{
	struct pcf85063 *pcf85063 = dev_id;
	unsigned int val;
	int err;

	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	if (err)
		return IRQ_NONE;

	if (val & PCF85063_CTRL2_AF) {
		rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
		regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
				   0);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int pcf85063_read_offset(struct device *dev, long *offset)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	long val;
	u32 reg;
	int ret;

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
	if (ret < 0)
		return ret;

	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
			    PCF85063_OFFSET_SIGN_BIT);

	if (reg & PCF85063_OFFSET_MODE)
		*offset = val * PCF85063_OFFSET_STEP1;
	else
		*offset = val * PCF85063_OFFSET_STEP0;

	return 0;
}

static int pcf85063_set_offset(struct device *dev, long offset)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	s8 mode0, mode1, reg;
	unsigned int error0, error1;

	if (offset > PCF85063_OFFSET_STEP0 * 63)
		return -ERANGE;
	if (offset < PCF85063_OFFSET_STEP0 * -64)
		return -ERANGE;

	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);

	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
	if (mode1 > 63 || mode1 < -64 || error0 < error1)
		reg = mode0 & ~PCF85063_OFFSET_MODE;
	else
		reg = mode1 | PCF85063_OFFSET_MODE;

	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
}

static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
			  unsigned long arg)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int status, ret = 0;

	switch (cmd) {
	case RTC_VL_READ:
		ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
		if (ret < 0)
			return ret;

		status = status & PCF85063_REG_SC_OS ? RTC_VL_DATA_INVALID : 0;

		return put_user(status, (unsigned int __user *)arg);

	default:
		return -ENOIOCTLCMD;
	}
}

static const struct rtc_class_ops pcf85063_rtc_ops = {
	.read_time	= pcf85063_rtc_read_time,
	.set_time	= pcf85063_rtc_set_time,
	.read_offset	= pcf85063_read_offset,
	.set_offset	= pcf85063_set_offset,
	.ioctl		= pcf85063_ioctl,
};

static const struct rtc_class_ops pcf85063_rtc_ops_alarm = {
	.read_time	= pcf85063_rtc_read_time,
	.set_time	= pcf85063_rtc_set_time,
	.read_offset	= pcf85063_read_offset,
	.set_offset	= pcf85063_set_offset,
	.read_alarm	= pcf85063_rtc_read_alarm,
	.set_alarm	= pcf85063_rtc_set_alarm,
	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
	.ioctl		= pcf85063_ioctl,
};

static int pcf85063_nvmem_read(void *priv, unsigned int offset,
			       void *val, size_t bytes)
{
	return regmap_read(priv, PCF85063_REG_RAM, val);
}

static int pcf85063_nvmem_write(void *priv, unsigned int offset,
				void *val, size_t bytes)
{
	return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
}

static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
				     const struct device_node *np,
				     unsigned int force_cap)
{
	u32 load = 7000;
	u8 reg = 0;

	if (force_cap)
		load = force_cap;
	else
		of_property_read_u32(np, "quartz-load-femtofarads", &load);

	switch (load) {
	default:
		dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
			 load);
		fallthrough;
	case 7000:
		break;
	case 12500:
		reg = PCF85063_REG_CTRL1_CAP_SEL;
		break;
	}

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				  PCF85063_REG_CTRL1_CAP_SEL, reg);
}

#ifdef CONFIG_COMMON_CLK
/*
 * Handling of the clkout
 */

#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)

static int clkout_rates[] = {
	32768,
	16384,
	8192,
	4096,
	2048,
	1024,
	1,
	0
};

static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	unsigned int buf;
	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);

	if (ret < 0)
		return 0;

	buf &= PCF85063_REG_CLKO_F_MASK;
	return clkout_rates[buf];
}

static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
				       unsigned long *prate)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
		if (clkout_rates[i] <= rate)
			return clkout_rates[i];

	return 0;
}

static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	int i;

	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
		if (clkout_rates[i] == rate)
			return regmap_update_bits(pcf85063->regmap,
				PCF85063_REG_CTRL2,
				PCF85063_REG_CLKO_F_MASK, i);

	return -EINVAL;
}

static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	unsigned int buf;
	int ret;

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &buf);
	if (ret < 0)
		return ret;
	buf &= PCF85063_REG_CLKO_F_MASK;

	if (enable) {
		if (buf == PCF85063_REG_CLKO_F_OFF)
			buf = PCF85063_REG_CLKO_F_32768HZ;
		else
			return 0;
	} else {
		if (buf != PCF85063_REG_CLKO_F_OFF)
			buf = PCF85063_REG_CLKO_F_OFF;
		else
			return 0;
	}

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
					PCF85063_REG_CLKO_F_MASK, buf);
}

static int pcf85063_clkout_prepare(struct clk_hw *hw)
{
	return pcf85063_clkout_control(hw, 1);
}

static void pcf85063_clkout_unprepare(struct clk_hw *hw)
{
	pcf85063_clkout_control(hw, 0);
}

static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	unsigned int buf;
	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);

	if (ret < 0)
		return 0;

	return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
}

static const struct clk_ops pcf85063_clkout_ops = {
	.prepare = pcf85063_clkout_prepare,
	.unprepare = pcf85063_clkout_unprepare,
	.is_prepared = pcf85063_clkout_is_prepared,
	.recalc_rate = pcf85063_clkout_recalc_rate,
	.round_rate = pcf85063_clkout_round_rate,
	.set_rate = pcf85063_clkout_set_rate,
};

static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
{
	struct clk *clk;
	struct clk_init_data init;

	init.name = "pcf85063-clkout";
	init.ops = &pcf85063_clkout_ops;
	init.flags = 0;
	init.parent_names = NULL;
	init.num_parents = 0;
	pcf85063->clkout_hw.init = &init;

	/* optional override of the clockname */
	of_property_read_string(pcf85063->rtc->dev.of_node,
				"clock-output-names", &init.name);

	/* register the clock */
	clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);

	if (!IS_ERR(clk))
		of_clk_add_provider(pcf85063->rtc->dev.of_node,
				    of_clk_src_simple_get, clk);

	return clk;
}
#endif

static const struct pcf85063_config pcf85063a_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x11,
	},
	.has_alarms = 1,
};

static const struct pcf85063_config pcf85063tp_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x0a,
	},
};

static const struct pcf85063_config rv8263_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x11,
	},
	.has_alarms = 1,
	.force_cap_7000 = 1,
};

static int pcf85063_probe(struct i2c_client *client)
{
	struct pcf85063 *pcf85063;
	unsigned int tmp;
	int err;
	const struct pcf85063_config *config = &pcf85063tp_config;
	const void *data = of_device_get_match_data(&client->dev);
	struct nvmem_config nvmem_cfg = {
		.name = "pcf85063_nvram",
		.reg_read = pcf85063_nvmem_read,
		.reg_write = pcf85063_nvmem_write,
		.type = NVMEM_TYPE_BATTERY_BACKED,
		.size = 1,
	};

	dev_dbg(&client->dev, "%s\n", __func__);

	pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
				GFP_KERNEL);
	if (!pcf85063)
		return -ENOMEM;

	if (data)
		config = data;

	pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
	if (IS_ERR(pcf85063->regmap))
		return PTR_ERR(pcf85063->regmap);

	i2c_set_clientdata(client, pcf85063);

	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
	if (err) {
		dev_err(&client->dev, "RTC chip is not present\n");
		return err;
	}

	pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
	if (IS_ERR(pcf85063->rtc))
		return PTR_ERR(pcf85063->rtc);

	err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
					config->force_cap_7000 ? 7000 : 0);
	if (err < 0)
		dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
			 err);

	pcf85063->rtc->ops = &pcf85063_rtc_ops;
	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
	pcf85063->rtc->uie_unsupported = 1;

	if (config->has_alarms && client->irq > 0) {
		err = devm_request_threaded_irq(&client->dev, client->irq,
						NULL, pcf85063_rtc_handle_irq,
						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
						"pcf85063", pcf85063);
		if (err) {
			dev_warn(&pcf85063->rtc->dev,
				 "unable to request IRQ, alarms disabled\n");
		} else {
			pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm;
			device_init_wakeup(&client->dev, true);
			err = dev_pm_set_wake_irq(&client->dev, client->irq);
			if (err)
				dev_err(&pcf85063->rtc->dev,
					"failed to enable irq wake\n");
		}
	}

	nvmem_cfg.priv = pcf85063->regmap;
	rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);

#ifdef CONFIG_COMMON_CLK
	/* register clk in common clk framework */
	pcf85063_clkout_register_clk(pcf85063);
#endif

	return rtc_register_device(pcf85063->rtc);
}

#ifdef CONFIG_OF
static const struct of_device_id pcf85063_of_match[] = {
	{ .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
	{ .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
	{ .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
	{ .compatible = "microcrystal,rv8263", .data = &rv8263_config },
	{}
};
MODULE_DEVICE_TABLE(of, pcf85063_of_match);
#endif

static struct i2c_driver pcf85063_driver = {
	.driver		= {
		.name	= "rtc-pcf85063",
		.of_match_table = of_match_ptr(pcf85063_of_match),
	},
	.probe_new	= pcf85063_probe,
};

module_i2c_driver(pcf85063_driver);

MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
MODULE_DESCRIPTION("PCF85063 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
de311aa8	1	// SPDX-License-Identifier: GPL-2.0
796b7abb SA	2	/*
	3	* An I2C driver for the PCF85063 RTC
	4	* Copyright 2014 Rose Technology
	5	*
	6	* Author: Søren Andersen <san@rosetechnology.dk>
	7	* Maintainers: http://www.nslu2-linux.org/
5b3a3ade AB	8	*
	9	* Copyright (C) 2019 Micro Crystal AG
	10	* Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
796b7abb	11	*/
8c229ab6	12	#include <linux/clk-provider.h>
796b7abb SA	13	#include <linux/i2c.h>
	14	#include <linux/bcd.h>
	15	#include <linux/rtc.h>
	16	#include <linux/module.h>
e89b60d0	17	#include <linux/of_device.h>
05cb3a56	18	#include <linux/pm_wakeirq.h>
e89b60d0	19	#include <linux/regmap.h>
796b7abb	20
0d981f81 CD	21	/*
	22	* Information for this driver was pulled from the following datasheets.
	23	*
3567d3d1 AK	24	* https://www.nxp.com/documents/data_sheet/PCF85063A.pdf
3567d3d1 AK	25	* https://www.nxp.com/documents/data_sheet/PCF85063TP.pdf
0d981f81 CD	26	*
	27	* PCF85063A -- Rev. 6 — 18 November 2015
	28	* PCF85063TP -- Rev. 4 — 6 May 2015
5b3a3ade AB	29	*
	30	* https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
	31	* RV8263 -- Rev. 1.0 — January 2019
	32	*/
0d981f81	33
796b7abb	34	#define PCF85063_REG_CTRL1 0x00 /* status */
bbb43838	35	#define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
31d4d33e	36	#define PCF85063_REG_CTRL1_STOP BIT(5)
796b7abb	37
05cb3a56 AB	38	#define PCF85063_REG_CTRL2 0x01
	39	#define PCF85063_CTRL2_AF BIT(6)
	40	#define PCF85063_CTRL2_AIE BIT(7)
	41
85370d3d AB	42	#define PCF85063_REG_OFFSET 0x02
	43	#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
	44	#define PCF85063_OFFSET_MODE BIT(7)
	45	#define PCF85063_OFFSET_STEP0 4340
	46	#define PCF85063_OFFSET_STEP1 4069
	47
8c229ab6 MM	48	#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
	49	#define PCF85063_REG_CLKO_F_32768HZ 0x00
	50	#define PCF85063_REG_CLKO_F_OFF 0x07
	51
fadfd092 AB	52	#define PCF85063_REG_RAM 0x03
fadfd092 AB	53
796b7abb	54	#define PCF85063_REG_SC 0x04 /* datetime */
6cc4c8b1	55	#define PCF85063_REG_SC_OS 0x80
796b7abb	56
05cb3a56 AB	57	#define PCF85063_REG_ALM_S 0x0b
	58	#define PCF85063_AEN BIT(7)
	59
0e2e8777 AB	60	struct pcf85063_config {
0e2e8777 AB	61	struct regmap_config regmap;
05cb3a56	62	unsigned has_alarms:1;
5b3a3ade	63	unsigned force_cap_7000:1;
0e2e8777 AB	64	};
0e2e8777 AB	65
e89b60d0 AB	66	struct pcf85063 {
	67	struct rtc_device *rtc;
	68	struct regmap *regmap;
8c229ab6 MM	69	#ifdef CONFIG_COMMON_CLK
	70	struct clk_hw clkout_hw;
	71	#endif
e89b60d0	72	};
0d981f81	73
965271df	74	static int pcf85063_rtc_read_time(struct device dev, struct rtc_time tm)
796b7abb	75	{
e89b60d0	76	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
7b576848	77	int rc;
7b576848 JB	78	u8 regs[7];
	79
	80	/*
	81	* while reading, the time/date registers are blocked and not updated
	82	* anymore until the access is finished. To not lose a second
	83	* event, the access must be finished within one second. So, read all
	84	* time/date registers in one turn.
	85	*/
e89b60d0 AB	86	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
	87	sizeof(regs));
	88	if (rc)
	89	return rc;
796b7abb	90
6cc4c8b1 JB	91	/* if the clock has lost its power it makes no sense to use its time */
6cc4c8b1 JB	92	if (regs[0] & PCF85063_REG_SC_OS) {
e89b60d0	93	dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
6cc4c8b1 JB	94	return -EINVAL;
	95	}
	96
7b576848 JB	97	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
	98	tm->tm_min = bcd2bin(regs[1] & 0x7F);
	99	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
	100	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
	101	tm->tm_wday = regs[4] & 0x07;
	102	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
	103	tm->tm_year = bcd2bin(regs[6]);
c421ce72	104	tm->tm_year += 100;
796b7abb	105
0a6b8886	106	return 0;
796b7abb SA	107	}
796b7abb SA	108
965271df	109	static int pcf85063_rtc_set_time(struct device dev, struct rtc_time tm)
796b7abb	110	{
e89b60d0	111	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
31d4d33e	112	int rc;
0d981f81	113	u8 regs[7];
796b7abb	114
31d4d33e JB	115	/*
	116	* to accurately set the time, reset the divider chain and keep it in
	117	* reset state until all time/date registers are written
	118	*/
e89b60d0 AB	119	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
	120	PCF85063_REG_CTRL1_STOP,
	121	PCF85063_REG_CTRL1_STOP);
	122	if (rc)
31d4d33e	123	return rc;
796b7abb SA	124
796b7abb SA	125	/* hours, minutes and seconds */
31d4d33e	126	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
796b7abb	127
31d4d33e JB	128	regs[1] = bin2bcd(tm->tm_min);
31d4d33e JB	129	regs[2] = bin2bcd(tm->tm_hour);
796b7abb SA	130
796b7abb SA	131	/* Day of month, 1 - 31 */
31d4d33e	132	regs[3] = bin2bcd(tm->tm_mday);
796b7abb SA	133
796b7abb SA	134	/* Day, 0 - 6 */
31d4d33e	135	regs[4] = tm->tm_wday & 0x07;
796b7abb SA	136
796b7abb SA	137	/* month, 1 - 12 */
31d4d33e	138	regs[5] = bin2bcd(tm->tm_mon + 1);
796b7abb SA	139
796b7abb SA	140	/* year and century */
c421ce72	141	regs[6] = bin2bcd(tm->tm_year - 100);
31d4d33e	142
31d4d33e	143	/* write all registers at once */
e89b60d0 AB	144	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
	145	regs, sizeof(regs));
	146	if (rc)
31d4d33e	147	return rc;
796b7abb	148
0d981f81 CD	149	/*
	150	* Write the control register as a separate action since the size of
	151	* the register space is different between the PCF85063TP and
	152	* PCF85063A devices. The rollover point can not be used.
	153	*/
e89b60d0 AB	154	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
e89b60d0 AB	155	PCF85063_REG_CTRL1_STOP, 0);
796b7abb SA	156	}
796b7abb SA	157
05cb3a56 AB	158	static int pcf85063_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	159	{
	160	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	161	u8 buf[4];
	162	unsigned int val;
	163	int ret;
	164
	165	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
	166	buf, sizeof(buf));
	167	if (ret)
	168	return ret;
	169
	170	alrm->time.tm_sec = bcd2bin(buf[0]);
	171	alrm->time.tm_min = bcd2bin(buf[1]);
	172	alrm->time.tm_hour = bcd2bin(buf[2]);
	173	alrm->time.tm_mday = bcd2bin(buf[3]);
	174
	175	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	176	if (ret)
	177	return ret;
	178
	179	alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
	180
	181	return 0;
	182	}
	183
	184	static int pcf85063_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	185	{
	186	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	187	u8 buf[5];
	188	int ret;
	189
	190	buf[0] = bin2bcd(alrm->time.tm_sec);
	191	buf[1] = bin2bcd(alrm->time.tm_min);
	192	buf[2] = bin2bcd(alrm->time.tm_hour);
	193	buf[3] = bin2bcd(alrm->time.tm_mday);
	194	buf[4] = PCF85063_AEN; /* Do not match on week day */
	195
	196	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	197	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF, 0);
	198	if (ret)
	199	return ret;
	200
	201	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
	202	buf, sizeof(buf));
	203	if (ret)
	204	return ret;
	205
	206	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	207	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF,
	208	alrm->enabled ? PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
	209	}
	210
	211	static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
	212	unsigned int enabled)
	213	{
	214	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	215
	216	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	217	PCF85063_CTRL2_AIE,
	218	enabled ? PCF85063_CTRL2_AIE : 0);
	219	}
	220
	221	static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
222	{
223	struct pcf85063 *pcf85063 = dev_id;
224	unsigned int val;
225	int err;
226
227	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
228	if (err)
229	return IRQ_NONE;
230
231	if (val & PCF85063_CTRL2_AF) {
232	rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF \| RTC_AF);
233	regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
234	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF,
235	0);
236	return IRQ_HANDLED;
237	}
238
239	return IRQ_NONE;
240	}
241
85370d3d AB	242	static int pcf85063_read_offset(struct device dev, long offset)
	243	{
	244	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	245	long val;
	246	u32 reg;
	247	int ret;
	248
	249	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
	250	if (ret < 0)
	251	return ret;
	252
	253	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
	254	PCF85063_OFFSET_SIGN_BIT);
	255
	256	if (reg & PCF85063_OFFSET_MODE)
	257	offset = val PCF85063_OFFSET_STEP1;
	258	else
	259	offset = val PCF85063_OFFSET_STEP0;
	260
	261	return 0;
	262	}
	263
	264	static int pcf85063_set_offset(struct device *dev, long offset)
	265	{
	266	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	267	s8 mode0, mode1, reg;
	268	unsigned int error0, error1;
	269
	270	if (offset > PCF85063_OFFSET_STEP0 * 63)
	271	return -ERANGE;
	272	if (offset < PCF85063_OFFSET_STEP0 * -64)
	273	return -ERANGE;
	274
	275	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
	276	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
	277
	278	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
	279	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
	280	if (mode1 > 63 \|\| mode1 < -64 \|\| error0 < error1)
	281	reg = mode0 & ~PCF85063_OFFSET_MODE;
	282	else
	283	reg = mode1 \| PCF85063_OFFSET_MODE;
	284
	285	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
	286	}
	287
27ff836d AB	288	static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
	289	unsigned long arg)
	290	{
	291	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	292	int status, ret = 0;
	293
	294	switch (cmd) {
	295	case RTC_VL_READ:
	296	ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
	297	if (ret < 0)
	298	return ret;
	299
f86dc5bd	300	status = status & PCF85063_REG_SC_OS ? RTC_VL_DATA_INVALID : 0;
27ff836d	301
f86dc5bd	302	return put_user(status, (unsigned int __user *)arg);
27ff836d	303
27ff836d AB	304	default:
	305	return -ENOIOCTLCMD;
	306	}
	307	}
	308
796b7abb SA	309	static const struct rtc_class_ops pcf85063_rtc_ops = {
796b7abb SA	310	.read_time = pcf85063_rtc_read_time,
85370d3d AB	311	.set_time = pcf85063_rtc_set_time,
	312	.read_offset = pcf85063_read_offset,
	313	.set_offset = pcf85063_set_offset,
27ff836d	314	.ioctl = pcf85063_ioctl,
796b7abb SA	315	};
796b7abb SA	316
05cb3a56 AB	317	static const struct rtc_class_ops pcf85063_rtc_ops_alarm = {
	318	.read_time = pcf85063_rtc_read_time,
	319	.set_time = pcf85063_rtc_set_time,
85370d3d AB	320	.read_offset = pcf85063_read_offset,
85370d3d AB	321	.set_offset = pcf85063_set_offset,
05cb3a56 AB	322	.read_alarm = pcf85063_rtc_read_alarm,
	323	.set_alarm = pcf85063_rtc_set_alarm,
	324	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
27ff836d	325	.ioctl = pcf85063_ioctl,
05cb3a56 AB	326	};
05cb3a56 AB	327
fadfd092 AB	328	static int pcf85063_nvmem_read(void *priv, unsigned int offset,
	329	void *val, size_t bytes)
	330	{
	331	return regmap_read(priv, PCF85063_REG_RAM, val);
	332	}
	333
	334	static int pcf85063_nvmem_write(void *priv, unsigned int offset,
	335	void *val, size_t bytes)
	336	{
	337	return regmap_write(priv, PCF85063_REG_RAM, (u8 )val);
	338	}
	339
e89b60d0	340	static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
5b3a3ade AB	341	const struct device_node *np,
5b3a3ade AB	342	unsigned int force_cap)
bbb43838	343	{
e89b60d0 AB	344	u32 load = 7000;
e89b60d0 AB	345	u8 reg = 0;
bbb43838	346
5b3a3ade AB	347	if (force_cap)
	348	load = force_cap;
	349	else
	350	of_property_read_u32(np, "quartz-load-femtofarads", &load);
	351
bbb43838 SR	352	switch (load) {
bbb43838 SR	353	default:
e89b60d0	354	dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
bbb43838	355	load);
df561f66	356	fallthrough;
bbb43838	357	case 7000:
bbb43838 SR	358	break;
bbb43838 SR	359	case 12500:
e89b60d0	360	reg = PCF85063_REG_CTRL1_CAP_SEL;
bbb43838 SR	361	break;
	362	}
	363
e89b60d0 AB	364	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
e89b60d0 AB	365	PCF85063_REG_CTRL1_CAP_SEL, reg);
bbb43838 SR	366	}
bbb43838 SR	367
8c229ab6 MM	368	#ifdef CONFIG_COMMON_CLK
	369	/*
	370	* Handling of the clkout
	371	*/
	372
	373	#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
	374
	375	static int clkout_rates[] = {
	376	32768,
	377	16384,
	378	8192,
	379	4096,
	380	2048,
	381	1024,
	382	1,
	383	0
	384	};
	385
	386	static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
	387	unsigned long parent_rate)
	388	{
	389	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	390	unsigned int buf;
	391	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
	392
	393	if (ret < 0)
	394	return 0;
	395
	396	buf &= PCF85063_REG_CLKO_F_MASK;
	397	return clkout_rates[buf];
	398	}
	399
	400	static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
	401	unsigned long *prate)
	402	{
	403	int i;
	404
	405	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
	406	if (clkout_rates[i] <= rate)
	407	return clkout_rates[i];
	408
	409	return 0;
	410	}
	411
	412	static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
	413	unsigned long parent_rate)
	414	{
	415	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	416	int i;
	417
	418	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
	419	if (clkout_rates[i] == rate)
	420	return regmap_update_bits(pcf85063->regmap,
	421	PCF85063_REG_CTRL2,
	422	PCF85063_REG_CLKO_F_MASK, i);
	423
	424	return -EINVAL;
	425	}
	426
	427	static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
	428	{
	429	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	430	unsigned int buf;
	431	int ret;
432
433	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &buf);
434	if (ret < 0)
435	return ret;
436	buf &= PCF85063_REG_CLKO_F_MASK;
437
438	if (enable) {
439	if (buf == PCF85063_REG_CLKO_F_OFF)
440	buf = PCF85063_REG_CLKO_F_32768HZ;
441	else
442	return 0;
443	} else {
444	if (buf != PCF85063_REG_CLKO_F_OFF)
445	buf = PCF85063_REG_CLKO_F_OFF;
446	else
447	return 0;
448	}
449
450	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
451	PCF85063_REG_CLKO_F_MASK, buf);
452	}
453
454	static int pcf85063_clkout_prepare(struct clk_hw *hw)
455	{
456	return pcf85063_clkout_control(hw, 1);
457	}
458
459	static void pcf85063_clkout_unprepare(struct clk_hw *hw)
460	{
461	pcf85063_clkout_control(hw, 0);
462	}
463
464	static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
465	{
466	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
467	unsigned int buf;
468	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
469
470	if (ret < 0)
471	return 0;
472
473	return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
474	}
475
476	static const struct clk_ops pcf85063_clkout_ops = {
477	.prepare = pcf85063_clkout_prepare,
478	.unprepare = pcf85063_clkout_unprepare,
479	.is_prepared = pcf85063_clkout_is_prepared,
480	.recalc_rate = pcf85063_clkout_recalc_rate,
481	.round_rate = pcf85063_clkout_round_rate,
482	.set_rate = pcf85063_clkout_set_rate,
483	};
484
485	static struct clk pcf85063_clkout_register_clk(struct pcf85063 pcf85063)
486	{
487	struct clk *clk;
488	struct clk_init_data init;
489
490	init.name = "pcf85063-clkout";
491	init.ops = &pcf85063_clkout_ops;
492	init.flags = 0;
493	init.parent_names = NULL;
494	init.num_parents = 0;
495	pcf85063->clkout_hw.init = &init;
496
497	/* optional override of the clockname */
498	of_property_read_string(pcf85063->rtc->dev.of_node,
499	"clock-output-names", &init.name);
500
501	/* register the clock */
502	clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
503
504	if (!IS_ERR(clk))
505	of_clk_add_provider(pcf85063->rtc->dev.of_node,
506	of_clk_src_simple_get, clk);
507
508	return clk;
509	}
510	#endif
511
0e2e8777 AB	512	static const struct pcf85063_config pcf85063a_config = {
	513	.regmap = {
	514	.reg_bits = 8,
	515	.val_bits = 8,
	516	.max_register = 0x11,
	517	},
05cb3a56	518	.has_alarms = 1,
0e2e8777 AB	519	};
	520
	521	static const struct pcf85063_config pcf85063tp_config = {
	522	.regmap = {
	523	.reg_bits = 8,
	524	.val_bits = 8,
	525	.max_register = 0x0a,
	526	},
e89b60d0 AB	527	};
e89b60d0 AB	528
5b3a3ade AB	529	static const struct pcf85063_config rv8263_config = {
	530	.regmap = {
	531	.reg_bits = 8,
	532	.val_bits = 8,
	533	.max_register = 0x11,
	534	},
	535	.has_alarms = 1,
	536	.force_cap_7000 = 1,
	537	};
	538
0f21700a	539	static int pcf85063_probe(struct i2c_client *client)
796b7abb	540	{
e89b60d0 AB	541	struct pcf85063 *pcf85063;
e89b60d0 AB	542	unsigned int tmp;
c18b4c52	543	int err;
0e2e8777 AB	544	const struct pcf85063_config *config = &pcf85063tp_config;
0e2e8777 AB	545	const void *data = of_device_get_match_data(&client->dev);
fadfd092 AB	546	struct nvmem_config nvmem_cfg = {
	547	.name = "pcf85063_nvram",
	548	.reg_read = pcf85063_nvmem_read,
	549	.reg_write = pcf85063_nvmem_write,
	550	.type = NVMEM_TYPE_BATTERY_BACKED,
	551	.size = 1,
	552	};
796b7abb SA	553
	554	dev_dbg(&client->dev, "%s\n", __func__);
	555
e89b60d0 AB	556	pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
	557	GFP_KERNEL);
	558	if (!pcf85063)
	559	return -ENOMEM;
	560
0e2e8777 AB	561	if (data)
	562	config = data;
	563
	564	pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
e89b60d0 AB	565	if (IS_ERR(pcf85063->regmap))
	566	return PTR_ERR(pcf85063->regmap);
	567
	568	i2c_set_clientdata(client, pcf85063);
	569
	570	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
	571	if (err) {
c18b4c52 MK	572	dev_err(&client->dev, "RTC chip is not present\n");
	573	return err;
	574	}
	575
e89b60d0 AB	576	pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
	577	if (IS_ERR(pcf85063->rtc))
	578	return PTR_ERR(pcf85063->rtc);
	579
5b3a3ade AB	580	err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
5b3a3ade AB	581	config->force_cap_7000 ? 7000 : 0);
bbb43838 SR	582	if (err < 0)
	583	dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
	584	err);
	585
e89b60d0 AB	586	pcf85063->rtc->ops = &pcf85063_rtc_ops;
	587	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	588	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
05cb3a56 AB	589	pcf85063->rtc->uie_unsupported = 1;
	590
	591	if (config->has_alarms && client->irq > 0) {
	592	err = devm_request_threaded_irq(&client->dev, client->irq,
	593	NULL, pcf85063_rtc_handle_irq,
	594	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	595	"pcf85063", pcf85063);
	596	if (err) {
	597	dev_warn(&pcf85063->rtc->dev,
	598	"unable to request IRQ, alarms disabled\n");
	599	} else {
	600	pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm;
	601	device_init_wakeup(&client->dev, true);
	602	err = dev_pm_set_wake_irq(&client->dev, client->irq);
	603	if (err)
	604	dev_err(&pcf85063->rtc->dev,
	605	"failed to enable irq wake\n");
	606	}
	607	}
796b7abb	608
fadfd092 AB	609	nvmem_cfg.priv = pcf85063->regmap;
	610	rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
	611
8c229ab6 MM	612	#ifdef CONFIG_COMMON_CLK
	613	/* register clk in common clk framework */
	614	pcf85063_clkout_register_clk(pcf85063);
	615	#endif
	616
e89b60d0	617	return rtc_register_device(pcf85063->rtc);
796b7abb SA	618	}
796b7abb SA	619
796b7abb SA	620	#ifdef CONFIG_OF
796b7abb SA	621	static const struct of_device_id pcf85063_of_match[] = {
0e2e8777 AB	622	{ .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
	623	{ .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
	624	{ .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
5b3a3ade	625	{ .compatible = "microcrystal,rv8263", .data = &rv8263_config },
796b7abb SA	626	{}
	627	};
	628	MODULE_DEVICE_TABLE(of, pcf85063_of_match);
	629	#endif
	630
	631	static struct i2c_driver pcf85063_driver = {
	632	.driver = {
	633	.name = "rtc-pcf85063",
796b7abb SA	634	.of_match_table = of_match_ptr(pcf85063_of_match),
796b7abb SA	635	},
0f21700a	636	.probe_new = pcf85063_probe,
796b7abb SA	637	};
	638
	639	module_i2c_driver(pcf85063_driver);
	640
	641	MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
	642	MODULE_DESCRIPTION("PCF85063 RTC driver");
	643	MODULE_LICENSE("GPL");