[linux-block.git] / drivers / rtc / rtc-pcf85063.c

// SPDX-License-Identifier: GPL-2.0
/*
 * An I2C driver for the PCF85063 RTC
 * Copyright 2014 Rose Technology
 *
 * Author: Søren Andersen <san@rosetechnology.dk>
 * Maintainers: http://www.nslu2-linux.org/
 *
 * Copyright (C) 2019 Micro Crystal AG
 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
 */
#include <linux/clk-provider.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>

/*
 * Information for this driver was pulled from the following datasheets.
 *
 *  https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
 *  https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
 *
 *  PCF85063A -- Rev. 7 — 30 March 2018
 *  PCF85063TP -- Rev. 4 — 6 May 2015
 *
 *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
 *  RV8263 -- Rev. 1.0 — January 2019
 */

#define PCF85063_REG_CTRL1		0x00 /* status */
#define PCF85063_REG_CTRL1_CAP_SEL	BIT(0)
#define PCF85063_REG_CTRL1_STOP		BIT(5)
#define PCF85063_REG_CTRL1_EXT_TEST	BIT(7)

#define PCF85063_REG_CTRL2		0x01
#define PCF85063_CTRL2_AF		BIT(6)
#define PCF85063_CTRL2_AIE		BIT(7)

#define PCF85063_REG_OFFSET		0x02
#define PCF85063_OFFSET_SIGN_BIT	6	/* 2's complement sign bit */
#define PCF85063_OFFSET_MODE		BIT(7)
#define PCF85063_OFFSET_STEP0		4340
#define PCF85063_OFFSET_STEP1		4069

#define PCF85063_REG_CLKO_F_MASK	0x07 /* frequency mask */
#define PCF85063_REG_CLKO_F_32768HZ	0x00
#define PCF85063_REG_CLKO_F_OFF		0x07

#define PCF85063_REG_RAM		0x03

#define PCF85063_REG_SC			0x04 /* datetime */
#define PCF85063_REG_SC_OS		0x80

#define PCF85063_REG_ALM_S		0x0b
#define PCF85063_AEN			BIT(7)

struct pcf85063_config {
	struct regmap_config regmap;
	unsigned has_alarms:1;
	unsigned force_cap_7000:1;
};

struct pcf85063 {
	struct rtc_device	*rtc;
	struct regmap		*regmap;
#ifdef CONFIG_COMMON_CLK
	struct clk_hw		clkout_hw;
#endif
};

static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int rc;
	u8 regs[7];

	/*
	 * while reading, the time/date registers are blocked and not updated
	 * anymore until the access is finished. To not lose a second
	 * event, the access must be finished within one second. So, read all
	 * time/date registers in one turn.
	 */
	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
			      sizeof(regs));
	if (rc)
		return rc;

	/* if the clock has lost its power it makes no sense to use its time */
	if (regs[0] & PCF85063_REG_SC_OS) {
		dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
		return -EINVAL;
	}

	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
	tm->tm_min = bcd2bin(regs[1] & 0x7F);
	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
	tm->tm_wday = regs[4] & 0x07;
	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
	tm->tm_year = bcd2bin(regs[6]);
	tm->tm_year += 100;

	return 0;
}

static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int rc;
	u8 regs[7];

	/*
	 * to accurately set the time, reset the divider chain and keep it in
	 * reset state until all time/date registers are written
	 */
	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				PCF85063_REG_CTRL1_EXT_TEST |
				PCF85063_REG_CTRL1_STOP,
				PCF85063_REG_CTRL1_STOP);
	if (rc)
		return rc;

	/* hours, minutes and seconds */
	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */

	regs[1] = bin2bcd(tm->tm_min);
	regs[2] = bin2bcd(tm->tm_hour);

	/* Day of month, 1 - 31 */
	regs[3] = bin2bcd(tm->tm_mday);

	/* Day, 0 - 6 */
	regs[4] = tm->tm_wday & 0x07;

	/* month, 1 - 12 */
	regs[5] = bin2bcd(tm->tm_mon + 1);

	/* year and century */
	regs[6] = bin2bcd(tm->tm_year - 100);

	/* write all registers at once */
	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
			       regs, sizeof(regs));
	if (rc)
		return rc;

	/*
	 * Write the control register as a separate action since the size of
	 * the register space is different between the PCF85063TP and
	 * PCF85063A devices.  The rollover point can not be used.
	 */
	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				  PCF85063_REG_CTRL1_STOP, 0);
}

static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	u8 buf[4];
	unsigned int val;
	int ret;

	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
			       buf, sizeof(buf));
	if (ret)
		return ret;

	alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
	alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
	alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
	alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	if (ret)
		return ret;

	alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);

	return 0;
}

static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	u8 buf[5];
	int ret;

	buf[0] = bin2bcd(alrm->time.tm_sec);
	buf[1] = bin2bcd(alrm->time.tm_min);
	buf[2] = bin2bcd(alrm->time.tm_hour);
	buf[3] = bin2bcd(alrm->time.tm_mday);
	buf[4] = PCF85063_AEN; /* Do not match on week day */

	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
	if (ret)
		return ret;

	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
				buf, sizeof(buf));
	if (ret)
		return ret;

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
				  alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
}

static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
					 unsigned int enabled)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				  PCF85063_CTRL2_AIE,
				  enabled ? PCF85063_CTRL2_AIE : 0);
}

static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
{
	struct pcf85063 *pcf85063 = dev_id;
	unsigned int val;
	int err;

	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	if (err)
		return IRQ_NONE;

	if (val & PCF85063_CTRL2_AF) {
		rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
		regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
				   0);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int pcf85063_read_offset(struct device *dev, long *offset)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	long val;
	u32 reg;
	int ret;

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
	if (ret < 0)
		return ret;

	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
			    PCF85063_OFFSET_SIGN_BIT);

	if (reg & PCF85063_OFFSET_MODE)
		*offset = val * PCF85063_OFFSET_STEP1;
	else
		*offset = val * PCF85063_OFFSET_STEP0;

	return 0;
}

static int pcf85063_set_offset(struct device *dev, long offset)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	s8 mode0, mode1, reg;
	unsigned int error0, error1;

	if (offset > PCF85063_OFFSET_STEP0 * 63)
		return -ERANGE;
	if (offset < PCF85063_OFFSET_STEP0 * -64)
		return -ERANGE;

	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);

	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
	if (mode1 > 63 || mode1 < -64 || error0 < error1)
		reg = mode0 & ~PCF85063_OFFSET_MODE;
	else
		reg = mode1 | PCF85063_OFFSET_MODE;

	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
}

static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
			  unsigned long arg)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int status, ret = 0;

	switch (cmd) {
	case RTC_VL_READ:
		ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
		if (ret < 0)
			return ret;

		status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;

		return put_user(status, (unsigned int __user *)arg);

	default:
		return -ENOIOCTLCMD;
	}
}

static const struct rtc_class_ops pcf85063_rtc_ops = {
	.read_time	= pcf85063_rtc_read_time,
	.set_time	= pcf85063_rtc_set_time,
	.read_offset	= pcf85063_read_offset,
	.set_offset	= pcf85063_set_offset,
	.read_alarm	= pcf85063_rtc_read_alarm,
	.set_alarm	= pcf85063_rtc_set_alarm,
	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
	.ioctl		= pcf85063_ioctl,
};

static int pcf85063_nvmem_read(void *priv, unsigned int offset,
			       void *val, size_t bytes)
{
	return regmap_read(priv, PCF85063_REG_RAM, val);
}

static int pcf85063_nvmem_write(void *priv, unsigned int offset,
				void *val, size_t bytes)
{
	return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
}

static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
				     const struct device_node *np,
				     unsigned int force_cap)
{
	u32 load = 7000;
	u8 reg = 0;

	if (force_cap)
		load = force_cap;
	else
		of_property_read_u32(np, "quartz-load-femtofarads", &load);

	switch (load) {
	default:
		dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
			 load);
		fallthrough;
	case 7000:
		break;
	case 12500:
		reg = PCF85063_REG_CTRL1_CAP_SEL;
		break;
	}

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				  PCF85063_REG_CTRL1_CAP_SEL, reg);
}

#ifdef CONFIG_COMMON_CLK
/*
 * Handling of the clkout
 */

#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)

static int clkout_rates[] = {
	32768,
	16384,
	8192,
	4096,
	2048,
	1024,
	1,
	0
};

static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	unsigned int buf;
	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);

	if (ret < 0)
		return 0;

	buf &= PCF85063_REG_CLKO_F_MASK;
	return clkout_rates[buf];
}

static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
				       unsigned long *prate)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
		if (clkout_rates[i] <= rate)
			return clkout_rates[i];

	return 0;
}

static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long parent_rate)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	int i;

	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
		if (clkout_rates[i] == rate)
			return regmap_update_bits(pcf85063->regmap,
				PCF85063_REG_CTRL2,
				PCF85063_REG_CLKO_F_MASK, i);

	return -EINVAL;
}

static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	unsigned int buf;
	int ret;

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
	if (ret < 0)
		return ret;
	buf &= PCF85063_REG_CLKO_F_MASK;

	if (enable) {
		if (buf == PCF85063_REG_CLKO_F_OFF)
			buf = PCF85063_REG_CLKO_F_32768HZ;
		else
			return 0;
	} else {
		if (buf != PCF85063_REG_CLKO_F_OFF)
			buf = PCF85063_REG_CLKO_F_OFF;
		else
			return 0;
	}

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
					PCF85063_REG_CLKO_F_MASK, buf);
}

static int pcf85063_clkout_prepare(struct clk_hw *hw)
{
	return pcf85063_clkout_control(hw, 1);
}

static void pcf85063_clkout_unprepare(struct clk_hw *hw)
{
	pcf85063_clkout_control(hw, 0);
}

static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
{
	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	unsigned int buf;
	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);

	if (ret < 0)
		return 0;

	return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
}

static const struct clk_ops pcf85063_clkout_ops = {
	.prepare = pcf85063_clkout_prepare,
	.unprepare = pcf85063_clkout_unprepare,
	.is_prepared = pcf85063_clkout_is_prepared,
	.recalc_rate = pcf85063_clkout_recalc_rate,
	.round_rate = pcf85063_clkout_round_rate,
	.set_rate = pcf85063_clkout_set_rate,
};

static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
{
	struct clk *clk;
	struct clk_init_data init;
	struct device_node *node = pcf85063->rtc->dev.parent->of_node;
	struct device_node *fixed_clock;

	fixed_clock = of_get_child_by_name(node, "clock");
	if (fixed_clock) {
		/*
		 * skip registering square wave clock when a fixed
		 * clock has been registered. The fixed clock is
		 * registered automatically when being referenced.
		 */
		of_node_put(fixed_clock);
		return NULL;
	}

	init.name = "pcf85063-clkout";
	init.ops = &pcf85063_clkout_ops;
	init.flags = 0;
	init.parent_names = NULL;
	init.num_parents = 0;
	pcf85063->clkout_hw.init = &init;

	/* optional override of the clockname */
	of_property_read_string(node, "clock-output-names", &init.name);

	/* register the clock */
	clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);

	if (!IS_ERR(clk))
		of_clk_add_provider(node, of_clk_src_simple_get, clk);

	return clk;
}
#endif

enum pcf85063_type {
	PCF85063,
	PCF85063TP,
	PCF85063A,
	RV8263,
	PCF85063_LAST_ID
};

static struct pcf85063_config pcf85063_cfg[] = {
	[PCF85063] = {
		.regmap = {
			.reg_bits = 8,
			.val_bits = 8,
			.max_register = 0x0a,
		},
	},
	[PCF85063TP] = {
		.regmap = {
			.reg_bits = 8,
			.val_bits = 8,
			.max_register = 0x0a,
		},
	},
	[PCF85063A] = {
		.regmap = {
			.reg_bits = 8,
			.val_bits = 8,
			.max_register = 0x11,
		},
		.has_alarms = 1,
	},
	[RV8263] = {
		.regmap = {
			.reg_bits = 8,
			.val_bits = 8,
			.max_register = 0x11,
		},
		.has_alarms = 1,
		.force_cap_7000 = 1,
	},
};

static const struct i2c_device_id pcf85063_ids[];

static int pcf85063_probe(struct i2c_client *client)
{
	struct pcf85063 *pcf85063;
	unsigned int tmp;
	int err;
	const struct pcf85063_config *config;
	struct nvmem_config nvmem_cfg = {
		.name = "pcf85063_nvram",
		.reg_read = pcf85063_nvmem_read,
		.reg_write = pcf85063_nvmem_write,
		.type = NVMEM_TYPE_BATTERY_BACKED,
		.size = 1,
	};

	dev_dbg(&client->dev, "%s\n", __func__);

	pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
				GFP_KERNEL);
	if (!pcf85063)
		return -ENOMEM;

	if (client->dev.of_node) {
		config = of_device_get_match_data(&client->dev);
		if (!config)
			return -ENODEV;
	} else {
		enum pcf85063_type type =
			i2c_match_id(pcf85063_ids, client)->driver_data;
		if (type >= PCF85063_LAST_ID)
			return -ENODEV;
		config = &pcf85063_cfg[type];
	}

	pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
	if (IS_ERR(pcf85063->regmap))
		return PTR_ERR(pcf85063->regmap);

	i2c_set_clientdata(client, pcf85063);

	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
	if (err) {
		dev_err(&client->dev, "RTC chip is not present\n");
		return err;
	}

	pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
	if (IS_ERR(pcf85063->rtc))
		return PTR_ERR(pcf85063->rtc);

	err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
					config->force_cap_7000 ? 7000 : 0);
	if (err < 0)
		dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
			 err);

	pcf85063->rtc->ops = &pcf85063_rtc_ops;
	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
	set_bit(RTC_FEATURE_ALARM_RES_2S, pcf85063->rtc->features);
	clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
	clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);

	if (config->has_alarms && client->irq > 0) {
		unsigned long irqflags = IRQF_TRIGGER_LOW;

		if (dev_fwnode(&client->dev))
			irqflags = 0;

		err = devm_request_threaded_irq(&client->dev, client->irq,
						NULL, pcf85063_rtc_handle_irq,
						irqflags | IRQF_ONESHOT,
						"pcf85063", pcf85063);
		if (err) {
			dev_warn(&pcf85063->rtc->dev,
				 "unable to request IRQ, alarms disabled\n");
		} else {
			set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
			device_init_wakeup(&client->dev, true);
			err = dev_pm_set_wake_irq(&client->dev, client->irq);
			if (err)
				dev_err(&pcf85063->rtc->dev,
					"failed to enable irq wake\n");
		}
	}

	nvmem_cfg.priv = pcf85063->regmap;
	devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);

#ifdef CONFIG_COMMON_CLK
	/* register clk in common clk framework */
	pcf85063_clkout_register_clk(pcf85063);
#endif

	return devm_rtc_register_device(pcf85063->rtc);
}

static const struct i2c_device_id pcf85063_ids[] = {
	{ "pca85073a", PCF85063A },
	{ "pcf85063", PCF85063 },
	{ "pcf85063tp", PCF85063TP },
	{ "pcf85063a", PCF85063A },
	{ "rv8263", RV8263 },
	{}
};
MODULE_DEVICE_TABLE(i2c, pcf85063_ids);

#ifdef CONFIG_OF
static const struct of_device_id pcf85063_of_match[] = {
	{ .compatible = "nxp,pca85073a", .data = &pcf85063_cfg[PCF85063A] },
	{ .compatible = "nxp,pcf85063", .data = &pcf85063_cfg[PCF85063] },
	{ .compatible = "nxp,pcf85063tp", .data = &pcf85063_cfg[PCF85063TP] },
	{ .compatible = "nxp,pcf85063a", .data = &pcf85063_cfg[PCF85063A] },
	{ .compatible = "microcrystal,rv8263", .data = &pcf85063_cfg[RV8263] },
	{}
};
MODULE_DEVICE_TABLE(of, pcf85063_of_match);
#endif

static struct i2c_driver pcf85063_driver = {
	.driver		= {
		.name	= "rtc-pcf85063",
		.of_match_table = of_match_ptr(pcf85063_of_match),
	},
	.probe_new	= pcf85063_probe,
	.id_table	= pcf85063_ids,
};

module_i2c_driver(pcf85063_driver);

MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
MODULE_DESCRIPTION("PCF85063 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
de311aa8	1	// SPDX-License-Identifier: GPL-2.0
796b7abb SA	2	/*
	3	* An I2C driver for the PCF85063 RTC
	4	* Copyright 2014 Rose Technology
	5	*
	6	* Author: Søren Andersen <san@rosetechnology.dk>
	7	* Maintainers: http://www.nslu2-linux.org/
5b3a3ade AB	8	*
	9	* Copyright (C) 2019 Micro Crystal AG
	10	* Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
796b7abb	11	*/
8c229ab6	12	#include <linux/clk-provider.h>
796b7abb SA	13	#include <linux/i2c.h>
	14	#include <linux/bcd.h>
	15	#include <linux/rtc.h>
	16	#include <linux/module.h>
e89b60d0	17	#include <linux/of_device.h>
05cb3a56	18	#include <linux/pm_wakeirq.h>
e89b60d0	19	#include <linux/regmap.h>
796b7abb	20
0d981f81 CD	21	/*
	22	* Information for this driver was pulled from the following datasheets.
	23	*
663bff17 FE	24	* https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
663bff17 FE	25	* https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
0d981f81	26	*
98c25b80	27	* PCF85063A -- Rev. 7 — 30 March 2018
0d981f81	28	* PCF85063TP -- Rev. 4 — 6 May 2015
5b3a3ade AB	29	*
	30	* https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
	31	* RV8263 -- Rev. 1.0 — January 2019
	32	*/
0d981f81	33
796b7abb	34	#define PCF85063_REG_CTRL1 0x00 /* status */
bbb43838	35	#define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
31d4d33e	36	#define PCF85063_REG_CTRL1_STOP BIT(5)
9f08c9ed	37	#define PCF85063_REG_CTRL1_EXT_TEST BIT(7)
796b7abb	38
05cb3a56 AB	39	#define PCF85063_REG_CTRL2 0x01
	40	#define PCF85063_CTRL2_AF BIT(6)
	41	#define PCF85063_CTRL2_AIE BIT(7)
	42
85370d3d AB	43	#define PCF85063_REG_OFFSET 0x02
	44	#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
	45	#define PCF85063_OFFSET_MODE BIT(7)
	46	#define PCF85063_OFFSET_STEP0 4340
	47	#define PCF85063_OFFSET_STEP1 4069
	48
8c229ab6 MM	49	#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
	50	#define PCF85063_REG_CLKO_F_32768HZ 0x00
	51	#define PCF85063_REG_CLKO_F_OFF 0x07
	52
fadfd092 AB	53	#define PCF85063_REG_RAM 0x03
fadfd092 AB	54
796b7abb	55	#define PCF85063_REG_SC 0x04 /* datetime */
6cc4c8b1	56	#define PCF85063_REG_SC_OS 0x80
796b7abb	57
05cb3a56 AB	58	#define PCF85063_REG_ALM_S 0x0b
	59	#define PCF85063_AEN BIT(7)
	60
0e2e8777 AB	61	struct pcf85063_config {
0e2e8777 AB	62	struct regmap_config regmap;
05cb3a56	63	unsigned has_alarms:1;
5b3a3ade	64	unsigned force_cap_7000:1;
0e2e8777 AB	65	};
0e2e8777 AB	66
e89b60d0 AB	67	struct pcf85063 {
	68	struct rtc_device *rtc;
	69	struct regmap *regmap;
8c229ab6 MM	70	#ifdef CONFIG_COMMON_CLK
	71	struct clk_hw clkout_hw;
	72	#endif
e89b60d0	73	};
0d981f81	74
965271df	75	static int pcf85063_rtc_read_time(struct device dev, struct rtc_time tm)
796b7abb	76	{
e89b60d0	77	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
7b576848	78	int rc;
7b576848 JB	79	u8 regs[7];
	80
	81	/*
	82	* while reading, the time/date registers are blocked and not updated
	83	* anymore until the access is finished. To not lose a second
	84	* event, the access must be finished within one second. So, read all
	85	* time/date registers in one turn.
	86	*/
e89b60d0 AB	87	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
	88	sizeof(regs));
	89	if (rc)
	90	return rc;
796b7abb	91
6cc4c8b1 JB	92	/* if the clock has lost its power it makes no sense to use its time */
6cc4c8b1 JB	93	if (regs[0] & PCF85063_REG_SC_OS) {
e89b60d0	94	dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
6cc4c8b1 JB	95	return -EINVAL;
	96	}
	97
7b576848 JB	98	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
	99	tm->tm_min = bcd2bin(regs[1] & 0x7F);
	100	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
	101	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
	102	tm->tm_wday = regs[4] & 0x07;
	103	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
	104	tm->tm_year = bcd2bin(regs[6]);
c421ce72	105	tm->tm_year += 100;
796b7abb	106
0a6b8886	107	return 0;
796b7abb SA	108	}
796b7abb SA	109
965271df	110	static int pcf85063_rtc_set_time(struct device dev, struct rtc_time tm)
796b7abb	111	{
e89b60d0	112	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
31d4d33e	113	int rc;
0d981f81	114	u8 regs[7];
796b7abb	115
31d4d33e JB	116	/*
	117	* to accurately set the time, reset the divider chain and keep it in
	118	* reset state until all time/date registers are written
	119	*/
e89b60d0	120	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
9f08c9ed	121	PCF85063_REG_CTRL1_EXT_TEST \|
e89b60d0 AB	122	PCF85063_REG_CTRL1_STOP,
	123	PCF85063_REG_CTRL1_STOP);
	124	if (rc)
31d4d33e	125	return rc;
796b7abb SA	126
796b7abb SA	127	/* hours, minutes and seconds */
31d4d33e	128	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
796b7abb	129
31d4d33e JB	130	regs[1] = bin2bcd(tm->tm_min);
31d4d33e JB	131	regs[2] = bin2bcd(tm->tm_hour);
796b7abb SA	132
796b7abb SA	133	/* Day of month, 1 - 31 */
31d4d33e	134	regs[3] = bin2bcd(tm->tm_mday);
796b7abb SA	135
796b7abb SA	136	/* Day, 0 - 6 */
31d4d33e	137	regs[4] = tm->tm_wday & 0x07;
796b7abb SA	138
796b7abb SA	139	/* month, 1 - 12 */
31d4d33e	140	regs[5] = bin2bcd(tm->tm_mon + 1);
796b7abb SA	141
796b7abb SA	142	/* year and century */
c421ce72	143	regs[6] = bin2bcd(tm->tm_year - 100);
31d4d33e	144
31d4d33e	145	/* write all registers at once */
e89b60d0 AB	146	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
	147	regs, sizeof(regs));
	148	if (rc)
31d4d33e	149	return rc;
796b7abb	150
0d981f81 CD	151	/*
	152	* Write the control register as a separate action since the size of
	153	* the register space is different between the PCF85063TP and
	154	* PCF85063A devices. The rollover point can not be used.
	155	*/
e89b60d0 AB	156	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
e89b60d0 AB	157	PCF85063_REG_CTRL1_STOP, 0);
796b7abb SA	158	}
796b7abb SA	159
05cb3a56 AB	160	static int pcf85063_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	161	{
	162	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	163	u8 buf[4];
	164	unsigned int val;
	165	int ret;
	166
	167	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
	168	buf, sizeof(buf));
	169	if (ret)
	170	return ret;
	171
a6ceee26 AS	172	alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
	173	alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
	174	alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
	175	alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);
05cb3a56 AB	176
	177	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	178	if (ret)
	179	return ret;
	180
	181	alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
	182
	183	return 0;
	184	}
	185
	186	static int pcf85063_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	187	{
	188	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	189	u8 buf[5];
	190	int ret;
	191
	192	buf[0] = bin2bcd(alrm->time.tm_sec);
	193	buf[1] = bin2bcd(alrm->time.tm_min);
	194	buf[2] = bin2bcd(alrm->time.tm_hour);
	195	buf[3] = bin2bcd(alrm->time.tm_mday);
	196	buf[4] = PCF85063_AEN; /* Do not match on week day */
	197
	198	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	199	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF, 0);
	200	if (ret)
	201	return ret;
	202
	203	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
	204	buf, sizeof(buf));
	205	if (ret)
	206	return ret;
	207
	208	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	209	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF,
	210	alrm->enabled ? PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
	211	}
	212
	213	static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
	214	unsigned int enabled)
	215	{
	216	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	217
	218	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	219	PCF85063_CTRL2_AIE,
	220	enabled ? PCF85063_CTRL2_AIE : 0);
	221	}
	222
	223	static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
	224	{
	225	struct pcf85063 *pcf85063 = dev_id;
	226	unsigned int val;
	227	int err;
	228
	229	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	230	if (err)
	231	return IRQ_NONE;
	232
	233	if (val & PCF85063_CTRL2_AF) {
	234	rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF \| RTC_AF);
	235	regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	236	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF,
	237	0);
	238	return IRQ_HANDLED;
	239	}
240
241	return IRQ_NONE;
242	}
243
85370d3d AB	244	static int pcf85063_read_offset(struct device dev, long offset)
	245	{
	246	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	247	long val;
	248	u32 reg;
	249	int ret;
	250
	251	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
	252	if (ret < 0)
	253	return ret;
	254
	255	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
	256	PCF85063_OFFSET_SIGN_BIT);
	257
	258	if (reg & PCF85063_OFFSET_MODE)
	259	offset = val PCF85063_OFFSET_STEP1;
	260	else
	261	offset = val PCF85063_OFFSET_STEP0;
	262
	263	return 0;
	264	}
	265
	266	static int pcf85063_set_offset(struct device *dev, long offset)
	267	{
	268	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	269	s8 mode0, mode1, reg;
	270	unsigned int error0, error1;
	271
	272	if (offset > PCF85063_OFFSET_STEP0 * 63)
	273	return -ERANGE;
	274	if (offset < PCF85063_OFFSET_STEP0 * -64)
	275	return -ERANGE;
	276
	277	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
	278	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
	279
	280	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
	281	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
	282	if (mode1 > 63 \|\| mode1 < -64 \|\| error0 < error1)
	283	reg = mode0 & ~PCF85063_OFFSET_MODE;
	284	else
	285	reg = mode1 \| PCF85063_OFFSET_MODE;
	286
	287	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
	288	}
	289
27ff836d AB	290	static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
	291	unsigned long arg)
	292	{
	293	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	294	int status, ret = 0;
	295
	296	switch (cmd) {
	297	case RTC_VL_READ:
	298	ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
	299	if (ret < 0)
	300	return ret;
	301
72e4ee63	302	status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;
27ff836d	303
f86dc5bd	304	return put_user(status, (unsigned int __user *)arg);
27ff836d	305
27ff836d AB	306	default:
	307	return -ENOIOCTLCMD;
	308	}
	309	}
	310
796b7abb	311	static const struct rtc_class_ops pcf85063_rtc_ops = {
05cb3a56 AB	312	.read_time = pcf85063_rtc_read_time,
05cb3a56 AB	313	.set_time = pcf85063_rtc_set_time,
85370d3d AB	314	.read_offset = pcf85063_read_offset,
85370d3d AB	315	.set_offset = pcf85063_set_offset,
05cb3a56 AB	316	.read_alarm = pcf85063_rtc_read_alarm,
	317	.set_alarm = pcf85063_rtc_set_alarm,
	318	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
27ff836d	319	.ioctl = pcf85063_ioctl,
05cb3a56 AB	320	};
05cb3a56 AB	321
fadfd092 AB	322	static int pcf85063_nvmem_read(void *priv, unsigned int offset,
	323	void *val, size_t bytes)
	324	{
	325	return regmap_read(priv, PCF85063_REG_RAM, val);
	326	}
	327
	328	static int pcf85063_nvmem_write(void *priv, unsigned int offset,
	329	void *val, size_t bytes)
	330	{
	331	return regmap_write(priv, PCF85063_REG_RAM, (u8 )val);
	332	}
	333
e89b60d0	334	static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
5b3a3ade AB	335	const struct device_node *np,
5b3a3ade AB	336	unsigned int force_cap)
bbb43838	337	{
e89b60d0 AB	338	u32 load = 7000;
e89b60d0 AB	339	u8 reg = 0;
bbb43838	340
5b3a3ade AB	341	if (force_cap)
	342	load = force_cap;
	343	else
	344	of_property_read_u32(np, "quartz-load-femtofarads", &load);
	345
bbb43838 SR	346	switch (load) {
bbb43838 SR	347	default:
e89b60d0	348	dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
bbb43838	349	load);
df561f66	350	fallthrough;
bbb43838	351	case 7000:
bbb43838 SR	352	break;
bbb43838 SR	353	case 12500:
e89b60d0	354	reg = PCF85063_REG_CTRL1_CAP_SEL;
bbb43838 SR	355	break;
	356	}
	357
e89b60d0 AB	358	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
e89b60d0 AB	359	PCF85063_REG_CTRL1_CAP_SEL, reg);
bbb43838 SR	360	}
bbb43838 SR	361
8c229ab6 MM	362	#ifdef CONFIG_COMMON_CLK
	363	/*
	364	* Handling of the clkout
	365	*/
	366
	367	#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
	368
	369	static int clkout_rates[] = {
	370	32768,
	371	16384,
	372	8192,
	373	4096,
	374	2048,
	375	1024,
	376	1,
	377	0
	378	};
	379
	380	static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
	381	unsigned long parent_rate)
	382	{
	383	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	384	unsigned int buf;
	385	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
	386
	387	if (ret < 0)
	388	return 0;
	389
	390	buf &= PCF85063_REG_CLKO_F_MASK;
	391	return clkout_rates[buf];
	392	}
	393
	394	static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
	395	unsigned long *prate)
	396	{
	397	int i;
	398
	399	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
	400	if (clkout_rates[i] <= rate)
	401	return clkout_rates[i];
	402
	403	return 0;
	404	}
	405
	406	static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
	407	unsigned long parent_rate)
	408	{
	409	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	410	int i;
	411
	412	for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
	413	if (clkout_rates[i] == rate)
	414	return regmap_update_bits(pcf85063->regmap,
	415	PCF85063_REG_CTRL2,
	416	PCF85063_REG_CLKO_F_MASK, i);
	417
	418	return -EINVAL;
	419	}
	420
	421	static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
	422	{
	423	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	424	unsigned int buf;
	425	int ret;
426
c2d12e85	427	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
8c229ab6 MM	428	if (ret < 0)
	429	return ret;
	430	buf &= PCF85063_REG_CLKO_F_MASK;
	431
	432	if (enable) {
	433	if (buf == PCF85063_REG_CLKO_F_OFF)
	434	buf = PCF85063_REG_CLKO_F_32768HZ;
	435	else
	436	return 0;
	437	} else {
	438	if (buf != PCF85063_REG_CLKO_F_OFF)
	439	buf = PCF85063_REG_CLKO_F_OFF;
	440	else
	441	return 0;
	442	}
	443
	444	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	445	PCF85063_REG_CLKO_F_MASK, buf);
	446	}
	447
	448	static int pcf85063_clkout_prepare(struct clk_hw *hw)
	449	{
	450	return pcf85063_clkout_control(hw, 1);
	451	}
	452
	453	static void pcf85063_clkout_unprepare(struct clk_hw *hw)
	454	{
	455	pcf85063_clkout_control(hw, 0);
	456	}
	457
	458	static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
	459	{
	460	struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
	461	unsigned int buf;
	462	int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
	463
	464	if (ret < 0)
	465	return 0;
	466
	467	return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
	468	}
	469
	470	static const struct clk_ops pcf85063_clkout_ops = {
	471	.prepare = pcf85063_clkout_prepare,
	472	.unprepare = pcf85063_clkout_unprepare,
	473	.is_prepared = pcf85063_clkout_is_prepared,
	474	.recalc_rate = pcf85063_clkout_recalc_rate,
	475	.round_rate = pcf85063_clkout_round_rate,
	476	.set_rate = pcf85063_clkout_set_rate,
	477	};
	478
	479	static struct clk pcf85063_clkout_register_clk(struct pcf85063 pcf85063)
	480	{
	481	struct clk *clk;
	482	struct clk_init_data init;
03531606	483	struct device_node *node = pcf85063->rtc->dev.parent->of_node;
4c8a7b80 AS	484	struct device_node *fixed_clock;
	485
	486	fixed_clock = of_get_child_by_name(node, "clock");
	487	if (fixed_clock) {
	488	/*
	489	* skip registering square wave clock when a fixed
	490	* clock has been registered. The fixed clock is
	491	* registered automatically when being referenced.
	492	*/
	493	of_node_put(fixed_clock);
	494	return NULL;
	495	}
8c229ab6 MM	496
	497	init.name = "pcf85063-clkout";
	498	init.ops = &pcf85063_clkout_ops;
	499	init.flags = 0;
	500	init.parent_names = NULL;
	501	init.num_parents = 0;
	502	pcf85063->clkout_hw.init = &init;
	503
	504	/* optional override of the clockname */
03531606	505	of_property_read_string(node, "clock-output-names", &init.name);
8c229ab6 MM	506
	507	/* register the clock */
	508	clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
	509
	510	if (!IS_ERR(clk))
03531606	511	of_clk_add_provider(node, of_clk_src_simple_get, clk);
8c229ab6 MM	512
	513	return clk;
	514	}
	515	#endif
	516
1c1b3098 MF	517	enum pcf85063_type {
	518	PCF85063,
	519	PCF85063TP,
	520	PCF85063A,
	521	RV8263,
	522	PCF85063_LAST_ID
	523	};
	524
	525	static struct pcf85063_config pcf85063_cfg[] = {
	526	[PCF85063] = {
	527	.regmap = {
	528	.reg_bits = 8,
	529	.val_bits = 8,
	530	.max_register = 0x0a,
	531	},
	532	},
	533	[PCF85063TP] = {
	534	.regmap = {
	535	.reg_bits = 8,
	536	.val_bits = 8,
	537	.max_register = 0x0a,
	538	},
	539	},
	540	[PCF85063A] = {
	541	.regmap = {
	542	.reg_bits = 8,
	543	.val_bits = 8,
	544	.max_register = 0x11,
	545	},
	546	.has_alarms = 1,
	547	},
	548	[RV8263] = {
	549	.regmap = {
	550	.reg_bits = 8,
	551	.val_bits = 8,
	552	.max_register = 0x11,
	553	},
	554	.has_alarms = 1,
	555	.force_cap_7000 = 1,
0e2e8777	556	},
e89b60d0 AB	557	};
e89b60d0 AB	558
1c1b3098 MF	559	static const struct i2c_device_id pcf85063_ids[];
1c1b3098 MF	560
0f21700a	561	static int pcf85063_probe(struct i2c_client *client)
796b7abb	562	{
e89b60d0 AB	563	struct pcf85063 *pcf85063;
e89b60d0 AB	564	unsigned int tmp;
c18b4c52	565	int err;
1c1b3098	566	const struct pcf85063_config *config;
fadfd092 AB	567	struct nvmem_config nvmem_cfg = {
	568	.name = "pcf85063_nvram",
	569	.reg_read = pcf85063_nvmem_read,
	570	.reg_write = pcf85063_nvmem_write,
	571	.type = NVMEM_TYPE_BATTERY_BACKED,
	572	.size = 1,
	573	};
796b7abb SA	574
	575	dev_dbg(&client->dev, "%s\n", __func__);
	576
e89b60d0 AB	577	pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
	578	GFP_KERNEL);
	579	if (!pcf85063)
	580	return -ENOMEM;
	581
1c1b3098 MF	582	if (client->dev.of_node) {
	583	config = of_device_get_match_data(&client->dev);
	584	if (!config)
	585	return -ENODEV;
	586	} else {
	587	enum pcf85063_type type =
	588	i2c_match_id(pcf85063_ids, client)->driver_data;
	589	if (type >= PCF85063_LAST_ID)
	590	return -ENODEV;
	591	config = &pcf85063_cfg[type];
	592	}
0e2e8777 AB	593
0e2e8777 AB	594	pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
e89b60d0 AB	595	if (IS_ERR(pcf85063->regmap))
	596	return PTR_ERR(pcf85063->regmap);
	597
	598	i2c_set_clientdata(client, pcf85063);
	599
	600	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
	601	if (err) {
c18b4c52 MK	602	dev_err(&client->dev, "RTC chip is not present\n");
	603	return err;
	604	}
	605
e89b60d0 AB	606	pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
	607	if (IS_ERR(pcf85063->rtc))
	608	return PTR_ERR(pcf85063->rtc);
	609
5b3a3ade AB	610	err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
5b3a3ade AB	611	config->force_cap_7000 ? 7000 : 0);
bbb43838 SR	612	if (err < 0)
	613	dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
	614	err);
	615
e89b60d0 AB	616	pcf85063->rtc->ops = &pcf85063_rtc_ops;
	617	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	618	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
a9f2d5bb	619	set_bit(RTC_FEATURE_ALARM_RES_2S, pcf85063->rtc->features);
11316c24	620	clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
d4eaffe2	621	clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
05cb3a56 AB	622
05cb3a56 AB	623	if (config->has_alarms && client->irq > 0) {
7e815272 AB	624	unsigned long irqflags = IRQF_TRIGGER_LOW;
	625
	626	if (dev_fwnode(&client->dev))
	627	irqflags = 0;
	628
05cb3a56 AB	629	err = devm_request_threaded_irq(&client->dev, client->irq,
05cb3a56 AB	630	NULL, pcf85063_rtc_handle_irq,
7e815272	631	irqflags \| IRQF_ONESHOT,
05cb3a56 AB	632	"pcf85063", pcf85063);
	633	if (err) {
	634	dev_warn(&pcf85063->rtc->dev,
	635	"unable to request IRQ, alarms disabled\n");
	636	} else {
d4eaffe2	637	set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
05cb3a56 AB	638	device_init_wakeup(&client->dev, true);
	639	err = dev_pm_set_wake_irq(&client->dev, client->irq);
	640	if (err)
	641	dev_err(&pcf85063->rtc->dev,
	642	"failed to enable irq wake\n");
	643	}
	644	}
796b7abb	645
fadfd092	646	nvmem_cfg.priv = pcf85063->regmap;
3a905c2d	647	devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
fadfd092	648
8c229ab6 MM	649	#ifdef CONFIG_COMMON_CLK
	650	/* register clk in common clk framework */
	651	pcf85063_clkout_register_clk(pcf85063);
	652	#endif
	653
fdcfd854	654	return devm_rtc_register_device(pcf85063->rtc);
796b7abb SA	655	}
796b7abb SA	656
1c1b3098	657	static const struct i2c_device_id pcf85063_ids[] = {
aabfe05a	658	{ "pca85073a", PCF85063A },
1c1b3098 MF	659	{ "pcf85063", PCF85063 },
	660	{ "pcf85063tp", PCF85063TP },
	661	{ "pcf85063a", PCF85063A },
	662	{ "rv8263", RV8263 },
	663	{}
c8ecbc78	664	};
1c1b3098	665	MODULE_DEVICE_TABLE(i2c, pcf85063_ids);
c8ecbc78	666
1c1b3098	667	#ifdef CONFIG_OF
796b7abb	668	static const struct of_device_id pcf85063_of_match[] = {
aabfe05a	669	{ .compatible = "nxp,pca85073a", .data = &pcf85063_cfg[PCF85063A] },
1c1b3098 MF	670	{ .compatible = "nxp,pcf85063", .data = &pcf85063_cfg[PCF85063] },
	671	{ .compatible = "nxp,pcf85063tp", .data = &pcf85063_cfg[PCF85063TP] },
	672	{ .compatible = "nxp,pcf85063a", .data = &pcf85063_cfg[PCF85063A] },
	673	{ .compatible = "microcrystal,rv8263", .data = &pcf85063_cfg[RV8263] },
796b7abb SA	674	{}
	675	};
	676	MODULE_DEVICE_TABLE(of, pcf85063_of_match);
	677	#endif
	678
	679	static struct i2c_driver pcf85063_driver = {
	680	.driver = {
	681	.name = "rtc-pcf85063",
796b7abb SA	682	.of_match_table = of_match_ptr(pcf85063_of_match),
796b7abb SA	683	},
0f21700a	684	.probe_new = pcf85063_probe,
1c1b3098	685	.id_table = pcf85063_ids,
796b7abb SA	686	};
	687
	688	module_i2c_driver(pcf85063_driver);
	689
	690	MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
	691	MODULE_DESCRIPTION("PCF85063 RTC driver");
	692	MODULE_LICENSE("GPL");