[linux-2.6-block.git] / drivers / rtc / rtc-pcf85063.c

// SPDX-License-Identifier: GPL-2.0
/*
 * An I2C driver for the PCF85063 RTC
 * Copyright 2014 Rose Technology
 *
 * Author: Søren Andersen <san@rosetechnology.dk>
 * Maintainers: http://www.nslu2-linux.org/
 *
 * Copyright (C) 2019 Micro Crystal AG
 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
 */
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>

/*
 * Information for this driver was pulled from the following datasheets.
 *
 *  http://www.nxp.com/documents/data_sheet/PCF85063A.pdf
 *  http://www.nxp.com/documents/data_sheet/PCF85063TP.pdf
 *
 *  PCF85063A -- Rev. 6 — 18 November 2015
 *  PCF85063TP -- Rev. 4 — 6 May 2015
 *
 *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
 *  RV8263 -- Rev. 1.0 — January 2019
 */

#define PCF85063_REG_CTRL1		0x00 /* status */
#define PCF85063_REG_CTRL1_CAP_SEL	BIT(0)
#define PCF85063_REG_CTRL1_STOP		BIT(5)

#define PCF85063_REG_CTRL2		0x01
#define PCF85063_CTRL2_AF		BIT(6)
#define PCF85063_CTRL2_AIE		BIT(7)

#define PCF85063_REG_OFFSET		0x02
#define PCF85063_OFFSET_SIGN_BIT	6	/* 2's complement sign bit */
#define PCF85063_OFFSET_MODE		BIT(7)
#define PCF85063_OFFSET_STEP0		4340
#define PCF85063_OFFSET_STEP1		4069

#define PCF85063_REG_RAM		0x03

#define PCF85063_REG_SC			0x04 /* datetime */
#define PCF85063_REG_SC_OS		0x80

#define PCF85063_REG_ALM_S		0x0b
#define PCF85063_AEN			BIT(7)

struct pcf85063_config {
	struct regmap_config regmap;
	unsigned has_alarms:1;
	unsigned force_cap_7000:1;
};

struct pcf85063 {
	struct rtc_device	*rtc;
	struct regmap		*regmap;
};

static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int rc;
	u8 regs[7];

	/*
	 * while reading, the time/date registers are blocked and not updated
	 * anymore until the access is finished. To not lose a second
	 * event, the access must be finished within one second. So, read all
	 * time/date registers in one turn.
	 */
	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
			      sizeof(regs));
	if (rc)
		return rc;

	/* if the clock has lost its power it makes no sense to use its time */
	if (regs[0] & PCF85063_REG_SC_OS) {
		dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
		return -EINVAL;
	}

	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
	tm->tm_min = bcd2bin(regs[1] & 0x7F);
	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
	tm->tm_wday = regs[4] & 0x07;
	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
	tm->tm_year = bcd2bin(regs[6]);
	tm->tm_year += 100;

	return 0;
}

static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int rc;
	u8 regs[7];

	/*
	 * to accurately set the time, reset the divider chain and keep it in
	 * reset state until all time/date registers are written
	 */
	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				PCF85063_REG_CTRL1_STOP,
				PCF85063_REG_CTRL1_STOP);
	if (rc)
		return rc;

	/* hours, minutes and seconds */
	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */

	regs[1] = bin2bcd(tm->tm_min);
	regs[2] = bin2bcd(tm->tm_hour);

	/* Day of month, 1 - 31 */
	regs[3] = bin2bcd(tm->tm_mday);

	/* Day, 0 - 6 */
	regs[4] = tm->tm_wday & 0x07;

	/* month, 1 - 12 */
	regs[5] = bin2bcd(tm->tm_mon + 1);

	/* year and century */
	regs[6] = bin2bcd(tm->tm_year - 100);

	/* write all registers at once */
	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
			       regs, sizeof(regs));
	if (rc)
		return rc;

	/*
	 * Write the control register as a separate action since the size of
	 * the register space is different between the PCF85063TP and
	 * PCF85063A devices.  The rollover point can not be used.
	 */
	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				  PCF85063_REG_CTRL1_STOP, 0);
}

static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	u8 buf[4];
	unsigned int val;
	int ret;

	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
			       buf, sizeof(buf));
	if (ret)
		return ret;

	alrm->time.tm_sec = bcd2bin(buf[0]);
	alrm->time.tm_min = bcd2bin(buf[1]);
	alrm->time.tm_hour = bcd2bin(buf[2]);
	alrm->time.tm_mday = bcd2bin(buf[3]);

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	if (ret)
		return ret;

	alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);

	return 0;
}

static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	u8 buf[5];
	int ret;

	buf[0] = bin2bcd(alrm->time.tm_sec);
	buf[1] = bin2bcd(alrm->time.tm_min);
	buf[2] = bin2bcd(alrm->time.tm_hour);
	buf[3] = bin2bcd(alrm->time.tm_mday);
	buf[4] = PCF85063_AEN; /* Do not match on week day */

	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
	if (ret)
		return ret;

	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
				buf, sizeof(buf));
	if (ret)
		return ret;

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
				  alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
}

static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
					 unsigned int enabled)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				  PCF85063_CTRL2_AIE,
				  enabled ? PCF85063_CTRL2_AIE : 0);
}

static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
{
	struct pcf85063 *pcf85063 = dev_id;
	unsigned int val;
	int err;

	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	if (err)
		return IRQ_NONE;

	if (val & PCF85063_CTRL2_AF) {
		rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
		regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
				   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
				   0);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int pcf85063_read_offset(struct device *dev, long *offset)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	long val;
	u32 reg;
	int ret;

	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
	if (ret < 0)
		return ret;

	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
			    PCF85063_OFFSET_SIGN_BIT);

	if (reg & PCF85063_OFFSET_MODE)
		*offset = val * PCF85063_OFFSET_STEP1;
	else
		*offset = val * PCF85063_OFFSET_STEP0;

	return 0;
}

static int pcf85063_set_offset(struct device *dev, long offset)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	s8 mode0, mode1, reg;
	unsigned int error0, error1;

	if (offset > PCF85063_OFFSET_STEP0 * 63)
		return -ERANGE;
	if (offset < PCF85063_OFFSET_STEP0 * -64)
		return -ERANGE;

	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);

	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
	if (mode1 > 63 || mode1 < -64 || error0 < error1)
		reg = mode0 & ~PCF85063_OFFSET_MODE;
	else
		reg = mode1 | PCF85063_OFFSET_MODE;

	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
}

static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
			  unsigned long arg)
{
	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	int status, ret = 0;

	switch (cmd) {
	case RTC_VL_READ:
		ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
		if (ret < 0)
			return ret;

		if (status & PCF85063_REG_SC_OS)
			dev_warn(&pcf85063->rtc->dev, "Voltage low, data loss detected.\n");

		status &= PCF85063_REG_SC_OS;

		if (copy_to_user((void __user *)arg, &status, sizeof(int)))
			return -EFAULT;

		return 0;

	case RTC_VL_CLR:
		ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_SC,
					 PCF85063_REG_SC_OS, 0);

		return ret;

	default:
		return -ENOIOCTLCMD;
	}
}

static const struct rtc_class_ops pcf85063_rtc_ops = {
	.read_time	= pcf85063_rtc_read_time,
	.set_time	= pcf85063_rtc_set_time,
	.read_offset	= pcf85063_read_offset,
	.set_offset	= pcf85063_set_offset,
	.ioctl		= pcf85063_ioctl,
};

static const struct rtc_class_ops pcf85063_rtc_ops_alarm = {
	.read_time	= pcf85063_rtc_read_time,
	.set_time	= pcf85063_rtc_set_time,
	.read_offset	= pcf85063_read_offset,
	.set_offset	= pcf85063_set_offset,
	.read_alarm	= pcf85063_rtc_read_alarm,
	.set_alarm	= pcf85063_rtc_set_alarm,
	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
	.ioctl		= pcf85063_ioctl,
};

static int pcf85063_nvmem_read(void *priv, unsigned int offset,
			       void *val, size_t bytes)
{
	return regmap_read(priv, PCF85063_REG_RAM, val);
}

static int pcf85063_nvmem_write(void *priv, unsigned int offset,
				void *val, size_t bytes)
{
	return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
}

static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
				     const struct device_node *np,
				     unsigned int force_cap)
{
	u32 load = 7000;
	u8 reg = 0;

	if (force_cap)
		load = force_cap;
	else
		of_property_read_u32(np, "quartz-load-femtofarads", &load);

	switch (load) {
	default:
		dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
			 load);
		/* fall through */
	case 7000:
		break;
	case 12500:
		reg = PCF85063_REG_CTRL1_CAP_SEL;
		break;
	}

	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
				  PCF85063_REG_CTRL1_CAP_SEL, reg);
}

static const struct pcf85063_config pcf85063a_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x11,
	},
	.has_alarms = 1,
};

static const struct pcf85063_config pcf85063tp_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x0a,
	},
};

static const struct pcf85063_config rv8263_config = {
	.regmap = {
		.reg_bits = 8,
		.val_bits = 8,
		.max_register = 0x11,
	},
	.has_alarms = 1,
	.force_cap_7000 = 1,
};

static int pcf85063_probe(struct i2c_client *client)
{
	struct pcf85063 *pcf85063;
	unsigned int tmp;
	int err;
	const struct pcf85063_config *config = &pcf85063tp_config;
	const void *data = of_device_get_match_data(&client->dev);
	struct nvmem_config nvmem_cfg = {
		.name = "pcf85063_nvram",
		.reg_read = pcf85063_nvmem_read,
		.reg_write = pcf85063_nvmem_write,
		.type = NVMEM_TYPE_BATTERY_BACKED,
		.size = 1,
	};

	dev_dbg(&client->dev, "%s\n", __func__);

	pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
				GFP_KERNEL);
	if (!pcf85063)
		return -ENOMEM;

	if (data)
		config = data;

	pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
	if (IS_ERR(pcf85063->regmap))
		return PTR_ERR(pcf85063->regmap);

	i2c_set_clientdata(client, pcf85063);

	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
	if (err) {
		dev_err(&client->dev, "RTC chip is not present\n");
		return err;
	}

	pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
	if (IS_ERR(pcf85063->rtc))
		return PTR_ERR(pcf85063->rtc);

	err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
					config->force_cap_7000 ? 7000 : 0);
	if (err < 0)
		dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
			 err);

	pcf85063->rtc->ops = &pcf85063_rtc_ops;
	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
	pcf85063->rtc->uie_unsupported = 1;

	if (config->has_alarms && client->irq > 0) {
		err = devm_request_threaded_irq(&client->dev, client->irq,
						NULL, pcf85063_rtc_handle_irq,
						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
						"pcf85063", pcf85063);
		if (err) {
			dev_warn(&pcf85063->rtc->dev,
				 "unable to request IRQ, alarms disabled\n");
		} else {
			pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm;
			device_init_wakeup(&client->dev, true);
			err = dev_pm_set_wake_irq(&client->dev, client->irq);
			if (err)
				dev_err(&pcf85063->rtc->dev,
					"failed to enable irq wake\n");
		}
	}

	nvmem_cfg.priv = pcf85063->regmap;
	rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);

	return rtc_register_device(pcf85063->rtc);
}

#ifdef CONFIG_OF
static const struct of_device_id pcf85063_of_match[] = {
	{ .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
	{ .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
	{ .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
	{ .compatible = "microcrystal,rv8263", .data = &rv8263_config },
	{}
};
MODULE_DEVICE_TABLE(of, pcf85063_of_match);
#endif

static struct i2c_driver pcf85063_driver = {
	.driver		= {
		.name	= "rtc-pcf85063",
		.of_match_table = of_match_ptr(pcf85063_of_match),
	},
	.probe_new	= pcf85063_probe,
};

module_i2c_driver(pcf85063_driver);

MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
MODULE_DESCRIPTION("PCF85063 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
de311aa8	1	// SPDX-License-Identifier: GPL-2.0
796b7abb SA	2	/*
	3	* An I2C driver for the PCF85063 RTC
	4	* Copyright 2014 Rose Technology
	5	*
	6	* Author: Søren Andersen <san@rosetechnology.dk>
	7	* Maintainers: http://www.nslu2-linux.org/
5b3a3ade AB	8	*
	9	* Copyright (C) 2019 Micro Crystal AG
	10	* Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
796b7abb SA	11	*/
	12	#include <linux/i2c.h>
	13	#include <linux/bcd.h>
	14	#include <linux/rtc.h>
	15	#include <linux/module.h>
e89b60d0	16	#include <linux/of_device.h>
05cb3a56	17	#include <linux/pm_wakeirq.h>
e89b60d0	18	#include <linux/regmap.h>
796b7abb	19
0d981f81 CD	20	/*
	21	* Information for this driver was pulled from the following datasheets.
	22	*
	23	* http://www.nxp.com/documents/data_sheet/PCF85063A.pdf
	24	* http://www.nxp.com/documents/data_sheet/PCF85063TP.pdf
	25	*
	26	* PCF85063A -- Rev. 6 — 18 November 2015
	27	* PCF85063TP -- Rev. 4 — 6 May 2015
5b3a3ade AB	28	*
	29	* https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
	30	* RV8263 -- Rev. 1.0 — January 2019
	31	*/
0d981f81	32
796b7abb	33	#define PCF85063_REG_CTRL1 0x00 /* status */
bbb43838	34	#define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
31d4d33e	35	#define PCF85063_REG_CTRL1_STOP BIT(5)
796b7abb	36
05cb3a56 AB	37	#define PCF85063_REG_CTRL2 0x01
	38	#define PCF85063_CTRL2_AF BIT(6)
	39	#define PCF85063_CTRL2_AIE BIT(7)
	40
85370d3d AB	41	#define PCF85063_REG_OFFSET 0x02
	42	#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
	43	#define PCF85063_OFFSET_MODE BIT(7)
	44	#define PCF85063_OFFSET_STEP0 4340
	45	#define PCF85063_OFFSET_STEP1 4069
	46
fadfd092 AB	47	#define PCF85063_REG_RAM 0x03
fadfd092 AB	48
796b7abb	49	#define PCF85063_REG_SC 0x04 /* datetime */
6cc4c8b1	50	#define PCF85063_REG_SC_OS 0x80
796b7abb	51
05cb3a56 AB	52	#define PCF85063_REG_ALM_S 0x0b
	53	#define PCF85063_AEN BIT(7)
	54
0e2e8777 AB	55	struct pcf85063_config {
0e2e8777 AB	56	struct regmap_config regmap;
05cb3a56	57	unsigned has_alarms:1;
5b3a3ade	58	unsigned force_cap_7000:1;
0e2e8777 AB	59	};
0e2e8777 AB	60
e89b60d0 AB	61	struct pcf85063 {
	62	struct rtc_device *rtc;
	63	struct regmap *regmap;
	64	};
0d981f81	65
965271df	66	static int pcf85063_rtc_read_time(struct device dev, struct rtc_time tm)
796b7abb	67	{
e89b60d0	68	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
7b576848	69	int rc;
7b576848 JB	70	u8 regs[7];
	71
	72	/*
	73	* while reading, the time/date registers are blocked and not updated
	74	* anymore until the access is finished. To not lose a second
	75	* event, the access must be finished within one second. So, read all
	76	* time/date registers in one turn.
	77	*/
e89b60d0 AB	78	rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
	79	sizeof(regs));
	80	if (rc)
	81	return rc;
796b7abb	82
6cc4c8b1 JB	83	/* if the clock has lost its power it makes no sense to use its time */
6cc4c8b1 JB	84	if (regs[0] & PCF85063_REG_SC_OS) {
e89b60d0	85	dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
6cc4c8b1 JB	86	return -EINVAL;
	87	}
	88
7b576848 JB	89	tm->tm_sec = bcd2bin(regs[0] & 0x7F);
	90	tm->tm_min = bcd2bin(regs[1] & 0x7F);
	91	tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
	92	tm->tm_mday = bcd2bin(regs[3] & 0x3F);
	93	tm->tm_wday = regs[4] & 0x07;
	94	tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
	95	tm->tm_year = bcd2bin(regs[6]);
c421ce72	96	tm->tm_year += 100;
796b7abb	97
0a6b8886	98	return 0;
796b7abb SA	99	}
796b7abb SA	100
965271df	101	static int pcf85063_rtc_set_time(struct device dev, struct rtc_time tm)
796b7abb	102	{
e89b60d0	103	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
31d4d33e	104	int rc;
0d981f81	105	u8 regs[7];
796b7abb	106
31d4d33e JB	107	/*
	108	* to accurately set the time, reset the divider chain and keep it in
	109	* reset state until all time/date registers are written
	110	*/
e89b60d0 AB	111	rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
	112	PCF85063_REG_CTRL1_STOP,
	113	PCF85063_REG_CTRL1_STOP);
	114	if (rc)
31d4d33e	115	return rc;
796b7abb SA	116
796b7abb SA	117	/* hours, minutes and seconds */
31d4d33e	118	regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
796b7abb	119
31d4d33e JB	120	regs[1] = bin2bcd(tm->tm_min);
31d4d33e JB	121	regs[2] = bin2bcd(tm->tm_hour);
796b7abb SA	122
796b7abb SA	123	/* Day of month, 1 - 31 */
31d4d33e	124	regs[3] = bin2bcd(tm->tm_mday);
796b7abb SA	125
796b7abb SA	126	/* Day, 0 - 6 */
31d4d33e	127	regs[4] = tm->tm_wday & 0x07;
796b7abb SA	128
796b7abb SA	129	/* month, 1 - 12 */
31d4d33e	130	regs[5] = bin2bcd(tm->tm_mon + 1);
796b7abb SA	131
796b7abb SA	132	/* year and century */
c421ce72	133	regs[6] = bin2bcd(tm->tm_year - 100);
31d4d33e	134
31d4d33e	135	/* write all registers at once */
e89b60d0 AB	136	rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
	137	regs, sizeof(regs));
	138	if (rc)
31d4d33e	139	return rc;
796b7abb	140
0d981f81 CD	141	/*
	142	* Write the control register as a separate action since the size of
	143	* the register space is different between the PCF85063TP and
	144	* PCF85063A devices. The rollover point can not be used.
	145	*/
e89b60d0 AB	146	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
e89b60d0 AB	147	PCF85063_REG_CTRL1_STOP, 0);
796b7abb SA	148	}
796b7abb SA	149
05cb3a56 AB	150	static int pcf85063_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	151	{
	152	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	153	u8 buf[4];
	154	unsigned int val;
	155	int ret;
	156
	157	ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
	158	buf, sizeof(buf));
	159	if (ret)
	160	return ret;
	161
	162	alrm->time.tm_sec = bcd2bin(buf[0]);
	163	alrm->time.tm_min = bcd2bin(buf[1]);
	164	alrm->time.tm_hour = bcd2bin(buf[2]);
	165	alrm->time.tm_mday = bcd2bin(buf[3]);
	166
	167	ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
	168	if (ret)
	169	return ret;
	170
	171	alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
	172
	173	return 0;
	174	}
	175
	176	static int pcf85063_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	177	{
	178	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	179	u8 buf[5];
	180	int ret;
	181
	182	buf[0] = bin2bcd(alrm->time.tm_sec);
	183	buf[1] = bin2bcd(alrm->time.tm_min);
	184	buf[2] = bin2bcd(alrm->time.tm_hour);
	185	buf[3] = bin2bcd(alrm->time.tm_mday);
	186	buf[4] = PCF85063_AEN; /* Do not match on week day */
	187
	188	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	189	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF, 0);
	190	if (ret)
	191	return ret;
	192
	193	ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
	194	buf, sizeof(buf));
	195	if (ret)
	196	return ret;
	197
	198	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	199	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF,
	200	alrm->enabled ? PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
	201	}
	202
	203	static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
	204	unsigned int enabled)
	205	{
	206	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	207
	208	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
	209	PCF85063_CTRL2_AIE,
	210	enabled ? PCF85063_CTRL2_AIE : 0);
	211	}
	212
	213	static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
214	{
215	struct pcf85063 *pcf85063 = dev_id;
216	unsigned int val;
217	int err;
218
219	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
220	if (err)
221	return IRQ_NONE;
222
223	if (val & PCF85063_CTRL2_AF) {
224	rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF \| RTC_AF);
225	regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
226	PCF85063_CTRL2_AIE \| PCF85063_CTRL2_AF,
227	0);
228	return IRQ_HANDLED;
229	}
230
231	return IRQ_NONE;
232	}
233
85370d3d AB	234	static int pcf85063_read_offset(struct device dev, long offset)
	235	{
	236	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	237	long val;
	238	u32 reg;
	239	int ret;
	240
	241	ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
	242	if (ret < 0)
	243	return ret;
	244
	245	val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
	246	PCF85063_OFFSET_SIGN_BIT);
	247
	248	if (reg & PCF85063_OFFSET_MODE)
	249	offset = val PCF85063_OFFSET_STEP1;
	250	else
	251	offset = val PCF85063_OFFSET_STEP0;
	252
	253	return 0;
	254	}
	255
	256	static int pcf85063_set_offset(struct device *dev, long offset)
	257	{
	258	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	259	s8 mode0, mode1, reg;
	260	unsigned int error0, error1;
	261
	262	if (offset > PCF85063_OFFSET_STEP0 * 63)
	263	return -ERANGE;
	264	if (offset < PCF85063_OFFSET_STEP0 * -64)
	265	return -ERANGE;
	266
	267	mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
	268	mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
	269
	270	error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
	271	error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
	272	if (mode1 > 63 \|\| mode1 < -64 \|\| error0 < error1)
	273	reg = mode0 & ~PCF85063_OFFSET_MODE;
	274	else
	275	reg = mode1 \| PCF85063_OFFSET_MODE;
	276
	277	return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
	278	}
	279
27ff836d AB	280	static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
	281	unsigned long arg)
	282	{
	283	struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
	284	int status, ret = 0;
	285
	286	switch (cmd) {
	287	case RTC_VL_READ:
	288	ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
	289	if (ret < 0)
	290	return ret;
	291
	292	if (status & PCF85063_REG_SC_OS)
	293	dev_warn(&pcf85063->rtc->dev, "Voltage low, data loss detected.\n");
	294
	295	status &= PCF85063_REG_SC_OS;
	296
	297	if (copy_to_user((void __user *)arg, &status, sizeof(int)))
	298	return -EFAULT;
	299
	300	return 0;
	301
	302	case RTC_VL_CLR:
	303	ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_SC,
	304	PCF85063_REG_SC_OS, 0);
	305
	306	return ret;
	307
	308	default:
	309	return -ENOIOCTLCMD;
	310	}
	311	}
	312
796b7abb SA	313	static const struct rtc_class_ops pcf85063_rtc_ops = {
796b7abb SA	314	.read_time = pcf85063_rtc_read_time,
85370d3d AB	315	.set_time = pcf85063_rtc_set_time,
	316	.read_offset = pcf85063_read_offset,
	317	.set_offset = pcf85063_set_offset,
27ff836d	318	.ioctl = pcf85063_ioctl,
796b7abb SA	319	};
796b7abb SA	320
05cb3a56 AB	321	static const struct rtc_class_ops pcf85063_rtc_ops_alarm = {
	322	.read_time = pcf85063_rtc_read_time,
	323	.set_time = pcf85063_rtc_set_time,
85370d3d AB	324	.read_offset = pcf85063_read_offset,
85370d3d AB	325	.set_offset = pcf85063_set_offset,
05cb3a56 AB	326	.read_alarm = pcf85063_rtc_read_alarm,
	327	.set_alarm = pcf85063_rtc_set_alarm,
	328	.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
27ff836d	329	.ioctl = pcf85063_ioctl,
05cb3a56 AB	330	};
05cb3a56 AB	331
fadfd092 AB	332	static int pcf85063_nvmem_read(void *priv, unsigned int offset,
	333	void *val, size_t bytes)
	334	{
	335	return regmap_read(priv, PCF85063_REG_RAM, val);
	336	}
	337
	338	static int pcf85063_nvmem_write(void *priv, unsigned int offset,
	339	void *val, size_t bytes)
	340	{
	341	return regmap_write(priv, PCF85063_REG_RAM, (u8 )val);
	342	}
	343
e89b60d0	344	static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
5b3a3ade AB	345	const struct device_node *np,
5b3a3ade AB	346	unsigned int force_cap)
bbb43838	347	{
e89b60d0 AB	348	u32 load = 7000;
e89b60d0 AB	349	u8 reg = 0;
bbb43838	350
5b3a3ade AB	351	if (force_cap)
	352	load = force_cap;
	353	else
	354	of_property_read_u32(np, "quartz-load-femtofarads", &load);
	355
bbb43838 SR	356	switch (load) {
bbb43838 SR	357	default:
e89b60d0	358	dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
bbb43838 SR	359	load);
	360	/* fall through */
	361	case 7000:
bbb43838 SR	362	break;
bbb43838 SR	363	case 12500:
e89b60d0	364	reg = PCF85063_REG_CTRL1_CAP_SEL;
bbb43838 SR	365	break;
	366	}
	367
e89b60d0 AB	368	return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
e89b60d0 AB	369	PCF85063_REG_CTRL1_CAP_SEL, reg);
bbb43838 SR	370	}
bbb43838 SR	371
0e2e8777 AB	372	static const struct pcf85063_config pcf85063a_config = {
	373	.regmap = {
	374	.reg_bits = 8,
	375	.val_bits = 8,
	376	.max_register = 0x11,
	377	},
05cb3a56	378	.has_alarms = 1,
0e2e8777 AB	379	};
	380
	381	static const struct pcf85063_config pcf85063tp_config = {
	382	.regmap = {
	383	.reg_bits = 8,
	384	.val_bits = 8,
	385	.max_register = 0x0a,
	386	},
e89b60d0 AB	387	};
e89b60d0 AB	388
5b3a3ade AB	389	static const struct pcf85063_config rv8263_config = {
	390	.regmap = {
	391	.reg_bits = 8,
	392	.val_bits = 8,
	393	.max_register = 0x11,
	394	},
	395	.has_alarms = 1,
	396	.force_cap_7000 = 1,
	397	};
	398
0f21700a	399	static int pcf85063_probe(struct i2c_client *client)
796b7abb	400	{
e89b60d0 AB	401	struct pcf85063 *pcf85063;
e89b60d0 AB	402	unsigned int tmp;
c18b4c52	403	int err;
0e2e8777 AB	404	const struct pcf85063_config *config = &pcf85063tp_config;
0e2e8777 AB	405	const void *data = of_device_get_match_data(&client->dev);
fadfd092 AB	406	struct nvmem_config nvmem_cfg = {
	407	.name = "pcf85063_nvram",
	408	.reg_read = pcf85063_nvmem_read,
	409	.reg_write = pcf85063_nvmem_write,
	410	.type = NVMEM_TYPE_BATTERY_BACKED,
	411	.size = 1,
	412	};
796b7abb SA	413
	414	dev_dbg(&client->dev, "%s\n", __func__);
	415
e89b60d0 AB	416	pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
	417	GFP_KERNEL);
	418	if (!pcf85063)
	419	return -ENOMEM;
	420
0e2e8777 AB	421	if (data)
	422	config = data;
	423
	424	pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
e89b60d0 AB	425	if (IS_ERR(pcf85063->regmap))
	426	return PTR_ERR(pcf85063->regmap);
	427
	428	i2c_set_clientdata(client, pcf85063);
	429
	430	err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
	431	if (err) {
c18b4c52 MK	432	dev_err(&client->dev, "RTC chip is not present\n");
	433	return err;
	434	}
	435
e89b60d0 AB	436	pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
	437	if (IS_ERR(pcf85063->rtc))
	438	return PTR_ERR(pcf85063->rtc);
	439
5b3a3ade AB	440	err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
5b3a3ade AB	441	config->force_cap_7000 ? 7000 : 0);
bbb43838 SR	442	if (err < 0)
	443	dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
	444	err);
	445
e89b60d0 AB	446	pcf85063->rtc->ops = &pcf85063_rtc_ops;
	447	pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
	448	pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
05cb3a56 AB	449	pcf85063->rtc->uie_unsupported = 1;
	450
	451	if (config->has_alarms && client->irq > 0) {
	452	err = devm_request_threaded_irq(&client->dev, client->irq,
	453	NULL, pcf85063_rtc_handle_irq,
	454	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	455	"pcf85063", pcf85063);
	456	if (err) {
	457	dev_warn(&pcf85063->rtc->dev,
	458	"unable to request IRQ, alarms disabled\n");
	459	} else {
	460	pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm;
	461	device_init_wakeup(&client->dev, true);
	462	err = dev_pm_set_wake_irq(&client->dev, client->irq);
	463	if (err)
	464	dev_err(&pcf85063->rtc->dev,
	465	"failed to enable irq wake\n");
	466	}
	467	}
796b7abb	468
fadfd092 AB	469	nvmem_cfg.priv = pcf85063->regmap;
	470	rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
	471
e89b60d0	472	return rtc_register_device(pcf85063->rtc);
796b7abb SA	473	}
796b7abb SA	474
796b7abb SA	475	#ifdef CONFIG_OF
796b7abb SA	476	static const struct of_device_id pcf85063_of_match[] = {
0e2e8777 AB	477	{ .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
	478	{ .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
	479	{ .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
5b3a3ade	480	{ .compatible = "microcrystal,rv8263", .data = &rv8263_config },
796b7abb SA	481	{}
	482	};
	483	MODULE_DEVICE_TABLE(of, pcf85063_of_match);
	484	#endif
	485
	486	static struct i2c_driver pcf85063_driver = {
	487	.driver = {
	488	.name = "rtc-pcf85063",
796b7abb SA	489	.of_match_table = of_match_ptr(pcf85063_of_match),
796b7abb SA	490	},
0f21700a	491	.probe_new = pcf85063_probe,
796b7abb SA	492	};
	493
	494	module_i2c_driver(pcf85063_driver);
	495
	496	MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
	497	MODULE_DESCRIPTION("PCF85063 RTC driver");
	498	MODULE_LICENSE("GPL");