projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'tag-chrome-platform-fixes-for-v6.3-rc4' of git://git.kernel.org/pub/scm...
[linux-2.6-block.git] / drivers / rtc / rtc-pcf2127.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
18cb6368 2/*
cee2cc21 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC
18cb6368
RC		 4 * Copyright 2013 Til-Technologies
5 *
6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
7 *
0e735eaa
BT		 8 * Watchdog and tamper functions
9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
10 *
18cb6368
RC		 11 * based on the other drivers in this same directory.
12 *
836e9ea3 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
18cb6368
RC		 14 */
15
16#include <linux/i2c.h>
9408ec1a 17#include <linux/spi/spi.h>
18cb6368
RC		 18#include <linux/bcd.h>
19#include <linux/rtc.h>
20#include <linux/slab.h>
21#include <linux/module.h>
22#include <linux/of.h>
8a914bac 23#include <linux/of_irq.h>
907b3262 24#include <linux/regmap.h>
0e735eaa 25#include <linux/watchdog.h>
18cb6368 26
bbfe3a7a
BT		 27/* Control register 1 */
28#define PCF2127_REG_CTRL1 0x00
b9ac079a 29#define PCF2127_BIT_CTRL1_POR_OVRD BIT(3)
03623b4b 30#define PCF2127_BIT_CTRL1_TSF1 BIT(4)
bbfe3a7a
BT		 31/* Control register 2 */
32#define PCF2127_REG_CTRL2 0x01
8a914bac 33#define PCF2127_BIT_CTRL2_AIE BIT(1)
03623b4b 34#define PCF2127_BIT_CTRL2_TSIE BIT(2)
8a914bac 35#define PCF2127_BIT_CTRL2_AF BIT(4)
03623b4b 36#define PCF2127_BIT_CTRL2_TSF2 BIT(5)
27006416 37#define PCF2127_BIT_CTRL2_WDTF BIT(6)
bbfe3a7a
BT		 38/* Control register 3 */
39#define PCF2127_REG_CTRL3 0x02
03623b4b
BT		 40#define PCF2127_BIT_CTRL3_BLIE BIT(0)
41#define PCF2127_BIT_CTRL3_BIE BIT(1)
bbfe3a7a 42#define PCF2127_BIT_CTRL3_BLF BIT(2)
03623b4b
BT		 43#define PCF2127_BIT_CTRL3_BF BIT(3)
44#define PCF2127_BIT_CTRL3_BTSE BIT(4)
bbfe3a7a
BT		 45/* Time and date registers */
46#define PCF2127_REG_SC 0x03
47#define PCF2127_BIT_SC_OSF BIT(7)
48#define PCF2127_REG_MN 0x04
49#define PCF2127_REG_HR 0x05
50#define PCF2127_REG_DM 0x06
51#define PCF2127_REG_DW 0x07
52#define PCF2127_REG_MO 0x08
53#define PCF2127_REG_YR 0x09
8a914bac
LB		 54/* Alarm registers */
55#define PCF2127_REG_ALARM_SC 0x0A
56#define PCF2127_REG_ALARM_MN 0x0B
57#define PCF2127_REG_ALARM_HR 0x0C
58#define PCF2127_REG_ALARM_DM 0x0D
59#define PCF2127_REG_ALARM_DW 0x0E
27006416 60#define PCF2127_BIT_ALARM_AE BIT(7)
15f57b3e
PR		 61/* CLKOUT control register */
62#define PCF2127_REG_CLKOUT 0x0f
63#define PCF2127_BIT_CLKOUT_OTPR BIT(5)
0e735eaa
BT		 64/* Watchdog registers */
65#define PCF2127_REG_WD_CTL 0x10
66#define PCF2127_BIT_WD_CTL_TF0 BIT(0)
67#define PCF2127_BIT_WD_CTL_TF1 BIT(1)
68#define PCF2127_BIT_WD_CTL_CD0 BIT(6)
69#define PCF2127_BIT_WD_CTL_CD1 BIT(7)
70#define PCF2127_REG_WD_VAL 0x11
03623b4b
BT		 71/* Tamper timestamp registers */
72#define PCF2127_REG_TS_CTRL 0x12
73#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
74#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
75#define PCF2127_REG_TS_SC 0x13
76#define PCF2127_REG_TS_MN 0x14
77#define PCF2127_REG_TS_HR 0x15
78#define PCF2127_REG_TS_DM 0x16
79#define PCF2127_REG_TS_MO 0x17
80#define PCF2127_REG_TS_YR 0x18
bbfe3a7a
BT		 81/*
82 * RAM registers
83 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
84 * battery backed and can survive a power outage.
85 * PCF2129 doesn't have this feature.
86 */
87#define PCF2127_REG_RAM_ADDR_MSB 0x1A
88#define PCF2127_REG_RAM_WRT_CMD 0x1C
89#define PCF2127_REG_RAM_RD_CMD 0x1D
d6c3029f 90
0e735eaa
BT		 91/* Watchdog timer value constants */
92#define PCF2127_WD_VAL_STOP 0
93#define PCF2127_WD_VAL_MIN 2
94#define PCF2127_WD_VAL_MAX 255
95#define PCF2127_WD_VAL_DEFAULT 60
653ebd75 96
2f861984
MYK		 97/* Mask for currently enabled interrupts */
98#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
99#define PCF2127_CTRL2_IRQ_MASK ( \
100 PCF2127_BIT_CTRL2_AF | \
101 PCF2127_BIT_CTRL2_WDTF | \
102 PCF2127_BIT_CTRL2_TSF2)
103
18cb6368
RC		 104struct pcf2127 {
105 struct rtc_device *rtc;
0e735eaa 106 struct watchdog_device wdd;
907b3262 107 struct regmap *regmap;
2f861984
MYK		 108 time64_t ts;
109 bool ts_valid;
110 bool irq_enabled;
18cb6368
RC		 111};
112
113/*
114 * In the routines that deal directly with the pcf2127 hardware, we use
115 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
116 */
907b3262 117static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
18cb6368 118{
907b3262
AM		 119 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
120 unsigned char buf[10];
121 int ret;
18cb6368 122
7f43020e
BT		 123 /*
124 * Avoid reading CTRL2 register as it causes WD_VAL register
125 * value to reset to 0 which means watchdog is stopped.
126 */
127 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL3,
128 (buf + PCF2127_REG_CTRL3),
129 ARRAY_SIZE(buf) - PCF2127_REG_CTRL3);
907b3262
AM		 130 if (ret) {
131 dev_err(dev, "%s: read error\n", __func__);
132 return ret;
18cb6368
RC		 133 }
134
bbfe3a7a 135 if (buf[PCF2127_REG_CTRL3] & PCF2127_BIT_CTRL3_BLF)
907b3262 136 dev_info(dev,
653ebd75 137 "low voltage detected, check/replace RTC battery.\n");
653ebd75 138
bbfe3a7a
BT		 139 /* Clock integrity is not guaranteed when OSF flag is set. */
140 if (buf[PCF2127_REG_SC] & PCF2127_BIT_SC_OSF) {
653ebd75
AS		 141 /*
142 * no need clear the flag here,
143 * it will be cleared once the new date is saved
144 */
907b3262 145 dev_warn(dev,
653ebd75
AS		 146 "oscillator stop detected, date/time is not reliable\n");
147 return -EINVAL;
18cb6368
RC		 148 }
149
907b3262 150 dev_dbg(dev,
7f43020e 151 "%s: raw data is cr3=%02x, sec=%02x, min=%02x, hr=%02x, "
18cb6368 152 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
7f43020e
BT		 153 __func__, buf[PCF2127_REG_CTRL3], buf[PCF2127_REG_SC],
154 buf[PCF2127_REG_MN], buf[PCF2127_REG_HR],
155 buf[PCF2127_REG_DM], buf[PCF2127_REG_DW],
156 buf[PCF2127_REG_MO], buf[PCF2127_REG_YR]);
18cb6368
RC		 157
158 tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
159 tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
160 tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F); /* rtc hr 0-23 */
161 tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
162 tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
163 tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
164 tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]);
b139bb5c 165 tm->tm_year += 100;
18cb6368 166
907b3262 167 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
18cb6368
RC		 168 "mday=%d, mon=%d, year=%d, wday=%d\n",
169 __func__,
170 tm->tm_sec, tm->tm_min, tm->tm_hour,
171 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
172
22652ba7 173 return 0;
18cb6368
RC		 174}
175
907b3262 176static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
18cb6368 177{
907b3262
AM		 178 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
179 unsigned char buf[7];
18cb6368
RC		 180 int i = 0, err;
181
907b3262 182 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
18cb6368
RC		 183 "mday=%d, mon=%d, year=%d, wday=%d\n",
184 __func__,
185 tm->tm_sec, tm->tm_min, tm->tm_hour,
186 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
187
18cb6368 188 /* hours, minutes and seconds */
653ebd75 189 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
18cb6368
RC		 190 buf[i++] = bin2bcd(tm->tm_min);
191 buf[i++] = bin2bcd(tm->tm_hour);
192 buf[i++] = bin2bcd(tm->tm_mday);
193 buf[i++] = tm->tm_wday & 0x07;
194
195 /* month, 1 - 12 */
196 buf[i++] = bin2bcd(tm->tm_mon + 1);
197
198 /* year */
b139bb5c 199 buf[i++] = bin2bcd(tm->tm_year - 100);
18cb6368
RC		 200
201 /* write register's data */
907b3262
AM		 202 err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i);
203 if (err) {
204 dev_err(dev,
18cb6368 205 "%s: err=%d", __func__, err);
907b3262 206 return err;
18cb6368
RC		 207 }
208
209 return 0;
210}
211
18cb6368
RC		 212static int pcf2127_rtc_ioctl(struct device *dev,
213 unsigned int cmd, unsigned long arg)
214{
907b3262 215 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
7d65cf8c 216 int val, touser = 0;
f97cfddc 217 int ret;
18cb6368
RC		 218
219 switch (cmd) {
220 case RTC_VL_READ:
7d65cf8c 221 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
907b3262 222 if (ret)
f97cfddc
UKK		 223 return ret;
224
7d65cf8c
AB		 225 if (val & PCF2127_BIT_CTRL3_BLF)
226 touser |= RTC_VL_BACKUP_LOW;
227
228 if (val & PCF2127_BIT_CTRL3_BF)
229 touser |= RTC_VL_BACKUP_SWITCH;
18cb6368 230
af427311 231 return put_user(touser, (unsigned int __user *)arg);
7d65cf8c
AB		 232
233 case RTC_VL_CLR:
234 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
235 PCF2127_BIT_CTRL3_BF, 0);
236
18cb6368
RC		 237 default:
238 return -ENOIOCTLCMD;
239 }
240}
18cb6368 241
d6c3029f
UKK		 242static int pcf2127_nvmem_read(void *priv, unsigned int offset,
243 void *val, size_t bytes)
244{
245 struct pcf2127 *pcf2127 = priv;
246 int ret;
247 unsigned char offsetbuf[] = { offset >> 8, offset };
248
bbfe3a7a 249 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
d6c3029f
UKK		 250 offsetbuf, 2);
251 if (ret)
252 return ret;
253
ba1c30bf
DC		 254 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
255 val, bytes);
d6c3029f
UKK		 256}
257
258static int pcf2127_nvmem_write(void *priv, unsigned int offset,
259 void *val, size_t bytes)
260{
261 struct pcf2127 *pcf2127 = priv;
262 int ret;
263 unsigned char offsetbuf[] = { offset >> 8, offset };
264
bbfe3a7a 265 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
d6c3029f
UKK		 266 offsetbuf, 2);
267 if (ret)
268 return ret;
269
ba1c30bf
DC		 270 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
271 val, bytes);
d6c3029f
UKK		 272}
273
0e735eaa
BT		 274/* watchdog driver */
275
276static int pcf2127_wdt_ping(struct watchdog_device *wdd)
277{
278 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
279
280 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout);
281}
282
283/*
284 * Restart watchdog timer if feature is active.
285 *
286 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
287 * since register also contain control/status flags for other features.
288 * Always call this function after reading CTRL2 register.
289 */
290static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
291{
292 int ret = 0;
293
294 if (watchdog_active(wdd)) {
295 ret = pcf2127_wdt_ping(wdd);
296 if (ret)
297 dev_err(wdd->parent,
298 "%s: watchdog restart failed, ret=%d\n",
299 __func__, ret);
300 }
301
302 return ret;
303}
304
305static int pcf2127_wdt_start(struct watchdog_device *wdd)
306{
307 return pcf2127_wdt_ping(wdd);
308}
309
310static int pcf2127_wdt_stop(struct watchdog_device *wdd)
311{
312 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
313
314 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL,
315 PCF2127_WD_VAL_STOP);
316}
317
318static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
319 unsigned int new_timeout)
320{
321 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
322 new_timeout, wdd->timeout);
323
324 wdd->timeout = new_timeout;
325
326 return pcf2127_wdt_active_ping(wdd);
327}
328
329static const struct watchdog_info pcf2127_wdt_info = {
330 .identity = "NXP PCF2127/PCF2129 Watchdog",
331 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
332};
333
334static const struct watchdog_ops pcf2127_watchdog_ops = {
335 .owner = THIS_MODULE,
336 .start = pcf2127_wdt_start,
337 .stop = pcf2127_wdt_stop,
338 .ping = pcf2127_wdt_ping,
339 .set_timeout = pcf2127_wdt_set_timeout,
340};
341
5d78533a
UKK		 342static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
343{
344 u32 wdd_timeout;
345 int ret;
346
71ac1345
UKK		 347 if (!IS_ENABLED(CONFIG_WATCHDOG) ||
348 !device_property_read_bool(dev, "reset-source"))
5d78533a
UKK		 349 return 0;
350
351 pcf2127->wdd.parent = dev;
352 pcf2127->wdd.info = &pcf2127_wdt_info;
353 pcf2127->wdd.ops = &pcf2127_watchdog_ops;
354 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN;
355 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX;
356 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT;
357 pcf2127->wdd.min_hw_heartbeat_ms = 500;
358 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
359
360 watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
361
362 /* Test if watchdog timer is started by bootloader */
363 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout);
364 if (ret)
365 return ret;
366
367 if (wdd_timeout)
368 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
369
370 return devm_watchdog_register_device(dev, &pcf2127->wdd);
371}
372
8a914bac
LB		 373/* Alarm */
374static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
375{
376 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
73ce0530
HV		 377 u8 buf[5];
378 unsigned int ctrl2;
8a914bac
LB		 379 int ret;
380
381 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
382 if (ret)
383 return ret;
384
385 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
386 if (ret)
387 return ret;
388
389 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
390 sizeof(buf));
391 if (ret)
392 return ret;
393
394 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
395 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
396
397 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
398 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
399 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
400 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
8a914bac
LB		 401
402 return 0;
403}
404
405static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
406{
407 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
408 int ret;
409
410 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
411 PCF2127_BIT_CTRL2_AIE,
412 enable ? PCF2127_BIT_CTRL2_AIE : 0);
413 if (ret)
414 return ret;
415
416 return pcf2127_wdt_active_ping(&pcf2127->wdd);
417}
418
419static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
420{
421 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
422 uint8_t buf[5];
423 int ret;
424
425 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
426 PCF2127_BIT_CTRL2_AF, 0);
427 if (ret)
428 return ret;
429
430 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
431 if (ret)
432 return ret;
433
434 buf[0] = bin2bcd(alrm->time.tm_sec);
435 buf[1] = bin2bcd(alrm->time.tm_min);
436 buf[2] = bin2bcd(alrm->time.tm_hour);
437 buf[3] = bin2bcd(alrm->time.tm_mday);
27006416 438 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
8a914bac
LB		 439
440 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
441 sizeof(buf));
442 if (ret)
443 return ret;
444
445 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
446}
447
2f861984
MYK		 448/*
449 * This function reads ctrl2 register, caller is responsible for calling
450 * pcf2127_wdt_active_ping()
451 */
452static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts)
453{
454 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
455 struct rtc_time tm;
456 int ret;
457 unsigned char data[25];
458
459 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data,
460 sizeof(data));
461 if (ret) {
462 dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
463 return ret;
464 }
465
466 dev_dbg(dev,
467 "%s: raw data is cr1=%02x, cr2=%02x, cr3=%02x, ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
468 __func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2],
469 data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC],
470 data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR],
471 data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO],
472 data[PCF2127_REG_TS_YR]);
473
474 tm.tm_sec = bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F);
475 tm.tm_min = bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F);
476 tm.tm_hour = bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F);
477 tm.tm_mday = bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F);
478 /* TS_MO register (month) value range: 1-12 */
479 tm.tm_mon = bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1;
480 tm.tm_year = bcd2bin(data[PCF2127_REG_TS_YR]);
481 if (tm.tm_year < 70)
482 tm.tm_year += 100; /* assume we are in 1970...2069 */
483
484 ret = rtc_valid_tm(&tm);
485 if (ret) {
486 dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
487 return ret;
488 }
489
490 *ts = rtc_tm_to_time64(&tm);
491 return 0;
492};
493
494static void pcf2127_rtc_ts_snapshot(struct device *dev)
495{
496 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
497 int ret;
498
499 /* Let userspace read the first timestamp */
500 if (pcf2127->ts_valid)
501 return;
502
503 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts);
504 if (!ret)
505 pcf2127->ts_valid = true;
506}
507
8a914bac
LB		 508static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
509{
510 struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
2f861984 511 unsigned int ctrl1, ctrl2;
8a914bac
LB		 512 int ret = 0;
513
2f861984
MYK		 514 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
515 if (ret)
516 return IRQ_NONE;
517
8a914bac
LB		 518 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
519 if (ret)
520 return IRQ_NONE;
521
2f861984 522 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
27006416 523 return IRQ_NONE;
8a914bac 524
2f861984
MYK		 525 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
526 pcf2127_rtc_ts_snapshot(dev);
527
528 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
529 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
530 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
531
532 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
533 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
534 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
8a914bac 535
2f861984
MYK		 536 if (ctrl2 & PCF2127_BIT_CTRL2_AF)
537 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
27006416
AB		 538
539 pcf2127_wdt_active_ping(&pcf2127->wdd);
8a914bac
LB		 540
541 return IRQ_HANDLED;
542}
543
25cbe9c8 544static const struct rtc_class_ops pcf2127_rtc_ops = {
8a914bac
LB		 545 .ioctl = pcf2127_rtc_ioctl,
546 .read_time = pcf2127_rtc_read_time,
547 .set_time = pcf2127_rtc_set_time,
548 .read_alarm = pcf2127_rtc_read_alarm,
549 .set_alarm = pcf2127_rtc_set_alarm,
550 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
551};
552
03623b4b
BT		 553/* sysfs interface */
554
555static ssize_t timestamp0_store(struct device *dev,
556 struct device_attribute *attr,
557 const char *buf, size_t count)
558{
559 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
560 int ret;
561
2f861984
MYK		 562 if (pcf2127->irq_enabled) {
563 pcf2127->ts_valid = false;
564 } else {
565 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
566 PCF2127_BIT_CTRL1_TSF1, 0);
567 if (ret) {
568 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret);
569 return ret;
570 }
03623b4b 571
2f861984
MYK		 572 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
573 PCF2127_BIT_CTRL2_TSF2, 0);
574 if (ret) {
575 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret);
576 return ret;
577 }
03623b4b 578
2f861984
MYK		 579 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
580 if (ret)
581 return ret;
582 }
03623b4b
BT		 583
584 return count;
585};
586
587static ssize_t timestamp0_show(struct device *dev,
588 struct device_attribute *attr, char *buf)
589{
590 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
2f861984 591 unsigned int ctrl1, ctrl2;
03623b4b 592 int ret;
2f861984
MYK		 593 time64_t ts;
594
595 if (pcf2127->irq_enabled) {
596 if (!pcf2127->ts_valid)
597 return 0;
598 ts = pcf2127->ts;
599 } else {
600 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
601 if (ret)
602 return 0;
03623b4b 603
2f861984
MYK		 604 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
605 if (ret)
606 return 0;
03623b4b 607
2f861984
MYK		 608 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) &&
609 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2))
610 return 0;
03623b4b 611
2f861984
MYK		 612 ret = pcf2127_rtc_ts_read(dev->parent, &ts);
613 if (ret)
614 return 0;
03623b4b 615
2f861984
MYK		 616 ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
617 if (ret)
618 return ret;
619 }
620 return sprintf(buf, "%llu\n", (unsigned long long)ts);
03623b4b
BT		 621};
622
623static DEVICE_ATTR_RW(timestamp0);
624
625static struct attribute *pcf2127_attrs[] = {
626 &dev_attr_timestamp0.attr,
627 NULL
628};
629
630static const struct attribute_group pcf2127_attr_group = {
631 .attrs = pcf2127_attrs,
632};
633
907b3262 634static int pcf2127_probe(struct device *dev, struct regmap *regmap,
2843d565 635 int alarm_irq, const char *name, bool is_pcf2127)
18cb6368
RC		 636{
637 struct pcf2127 *pcf2127;
d6c3029f 638 int ret = 0;
15f57b3e 639 unsigned int val;
18cb6368 640
907b3262 641 dev_dbg(dev, "%s\n", __func__);
18cb6368 642
907b3262 643 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
18cb6368
RC		 644 if (!pcf2127)
645 return -ENOMEM;
646
907b3262 647 pcf2127->regmap = regmap;
18cb6368 648
907b3262
AM		 649 dev_set_drvdata(dev, pcf2127);
650
e788771c 651 pcf2127->rtc = devm_rtc_allocate_device(dev);
d6c3029f
UKK		 652 if (IS_ERR(pcf2127->rtc))
653 return PTR_ERR(pcf2127->rtc);
654
e788771c 655 pcf2127->rtc->ops = &pcf2127_rtc_ops;
b139bb5c
AB		 656 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
657 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
658 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
bda10273 659 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features);
689fafd5 660 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features);
25cbe9c8 661 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
e788771c 662
35425baf 663 if (alarm_irq > 0) {
d4785b46
HV		 664 unsigned long flags;
665
666 /*
667 * If flags = 0, devm_request_threaded_irq() will use IRQ flags
668 * obtained from device tree.
669 */
670 if (dev_fwnode(dev))
671 flags = 0;
672 else
673 flags = IRQF_TRIGGER_LOW;
674
27006416
AB		 675 ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
676 pcf2127_rtc_irq,
d4785b46 677 flags | IRQF_ONESHOT,
27006416 678 dev_name(dev), dev);
8a914bac
LB		 679 if (ret) {
680 dev_err(dev, "failed to request alarm irq\n");
681 return ret;
682 }
2f861984 683 pcf2127->irq_enabled = true;
8a914bac
LB		 684 }
685
35425baf 686 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
8a914bac 687 device_init_wakeup(dev, true);
25cbe9c8 688 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
8a914bac
LB		 689 }
690
2843d565 691 if (is_pcf2127) {
d6c3029f
UKK		 692 struct nvmem_config nvmem_cfg = {
693 .priv = pcf2127,
694 .reg_read = pcf2127_nvmem_read,
695 .reg_write = pcf2127_nvmem_write,
696 .size = 512,
697 };
698
3a905c2d 699 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
d6c3029f 700 }
18cb6368 701
b9ac079a
PR		 702 /*
703 * The "Power-On Reset Override" facility prevents the RTC to do a reset
704 * after power on. For normal operation the PORO must be disabled.
705 */
706 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
707 PCF2127_BIT_CTRL1_POR_OVRD);
708
15f57b3e
PR		 709 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val);
710 if (ret < 0)
711 return ret;
712
713 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) {
714 ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT,
715 PCF2127_BIT_CLKOUT_OTPR);
716 if (ret < 0)
717 return ret;
718
719 msleep(100);
720 }
721
0e735eaa
BT		 722 /*
723 * Watchdog timer enabled and reset pin /RST activated when timed out.
724 * Select 1Hz clock source for watchdog timer.
0e735eaa 725 * Note: Countdown timer disabled and not available.
2843d565
BL		 726 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
727 * of register watchdg_tim_ctl. The bit[6] is labeled
728 * as T. Bits labeled as T must always be written with
729 * logic 0.
0e735eaa
BT		 730 */
731 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
732 PCF2127_BIT_WD_CTL_CD1 |
733 PCF2127_BIT_WD_CTL_CD0 |
734 PCF2127_BIT_WD_CTL_TF1 |
735 PCF2127_BIT_WD_CTL_TF0,
736 PCF2127_BIT_WD_CTL_CD1 |
2843d565 737 (is_pcf2127 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
0e735eaa
BT		 738 PCF2127_BIT_WD_CTL_TF1);
739 if (ret) {
740 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
741 return ret;
742 }
743
5d78533a 744 pcf2127_watchdog_init(dev, pcf2127);
0e735eaa 745
03623b4b
BT		 746 /*
747 * Disable battery low/switch-over timestamp and interrupts.
748 * Clear battery interrupt flags which can block new trigger events.
749 * Note: This is the default chip behaviour but added to ensure
750 * correct tamper timestamp and interrupt function.
751 */
752 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
753 PCF2127_BIT_CTRL3_BTSE |
03623b4b
BT		 754 PCF2127_BIT_CTRL3_BIE |
755 PCF2127_BIT_CTRL3_BLIE, 0);
756 if (ret) {
757 dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
758 __func__);
759 return ret;
760 }
761
762 /*
763 * Enable timestamp function and store timestamp of first trigger
7b69b54a 764 * event until TSF1 and TSF2 interrupt flags are cleared.
03623b4b
BT		 765 */
766 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
767 PCF2127_BIT_TS_CTRL_TSOFF |
768 PCF2127_BIT_TS_CTRL_TSM,
769 PCF2127_BIT_TS_CTRL_TSM);
770 if (ret) {
771 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n",
772 __func__);
773 return ret;
774 }
775
776 /*
777 * Enable interrupt generation when TSF1 or TSF2 timestamp flags
778 * are set. Interrupt signal is an open-drain output and can be
779 * left floating if unused.
780 */
781 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
782 PCF2127_BIT_CTRL2_TSIE,
783 PCF2127_BIT_CTRL2_TSIE);
784 if (ret) {
785 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n",
786 __func__);
787 return ret;
788 }
789
790 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group);
791 if (ret) {
792 dev_err(dev, "%s: tamper sysfs registering failed\n",
793 __func__);
794 return ret;
795 }
796
fdcfd854 797 return devm_rtc_register_device(pcf2127->rtc);
18cb6368
RC		 798}
799
18cb6368
RC		 800#ifdef CONFIG_OF
801static const struct of_device_id pcf2127_of_match[] = {
802 { .compatible = "nxp,pcf2127" },
cee2cc21 803 { .compatible = "nxp,pcf2129" },
985b30db 804 { .compatible = "nxp,pca2129" },
18cb6368
RC		 805 {}
806};
807MODULE_DEVICE_TABLE(of, pcf2127_of_match);
808#endif
809
9408ec1a
AM		 810#if IS_ENABLED(CONFIG_I2C)
811
907b3262
AM		 812static int pcf2127_i2c_write(void *context, const void *data, size_t count)
813{
814 struct device *dev = context;
815 struct i2c_client *client = to_i2c_client(dev);
816 int ret;
817
818 ret = i2c_master_send(client, data, count);
819 if (ret != count)
820 return ret < 0 ? ret : -EIO;
821
822 return 0;
823}
824
825static int pcf2127_i2c_gather_write(void *context,
826 const void *reg, size_t reg_size,
827 const void *val, size_t val_size)
828{
829 struct device *dev = context;
830 struct i2c_client *client = to_i2c_client(dev);
831 int ret;
832 void *buf;
833
834 if (WARN_ON(reg_size != 1))
835 return -EINVAL;
836
837 buf = kmalloc(val_size + 1, GFP_KERNEL);
838 if (!buf)
839 return -ENOMEM;
840
841 memcpy(buf, reg, 1);
842 memcpy(buf + 1, val, val_size);
843
844 ret = i2c_master_send(client, buf, val_size + 1);
9bde0afb
XS		 845
846 kfree(buf);
847
907b3262
AM		 848 if (ret != val_size + 1)
849 return ret < 0 ? ret : -EIO;
850
851 return 0;
852}
853
854static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
855 void *val, size_t val_size)
856{
857 struct device *dev = context;
858 struct i2c_client *client = to_i2c_client(dev);
859 int ret;
860
861 if (WARN_ON(reg_size != 1))
862 return -EINVAL;
863
864 ret = i2c_master_send(client, reg, 1);
865 if (ret != 1)
866 return ret < 0 ? ret : -EIO;
867
868 ret = i2c_master_recv(client, val, val_size);
869 if (ret != val_size)
870 return ret < 0 ? ret : -EIO;
871
872 return 0;
873}
874
875/*
876 * The reason we need this custom regmap_bus instead of using regmap_init_i2c()
877 * is that the STOP condition is required between set register address and
878 * read register data when reading from registers.
879 */
880static const struct regmap_bus pcf2127_i2c_regmap = {
881 .write = pcf2127_i2c_write,
882 .gather_write = pcf2127_i2c_gather_write,
883 .read = pcf2127_i2c_read,
884};
885
886static struct i2c_driver pcf2127_i2c_driver;
887
5418e595
UKK		 888static const struct i2c_device_id pcf2127_i2c_id[] = {
889 { "pcf2127", 1 },
890 { "pcf2129", 0 },
891 { "pca2129", 0 },
892 { }
893};
894MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
895
896static int pcf2127_i2c_probe(struct i2c_client *client)
907b3262 897{
5418e595 898 const struct i2c_device_id *id = i2c_match_id(pcf2127_i2c_id, client);
907b3262
AM		 899 struct regmap *regmap;
900 static const struct regmap_config config = {
901 .reg_bits = 8,
902 .val_bits = 8,
040e6dc0 903 .max_register = 0x1d,
907b3262
AM		 904 };
905
906 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
907 return -ENODEV;
908
909 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
910 &client->dev, &config);
911 if (IS_ERR(regmap)) {
912 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
913 __func__, PTR_ERR(regmap));
914 return PTR_ERR(regmap);
915 }
916
27006416 917 return pcf2127_probe(&client->dev, regmap, client->irq,
d6c3029f 918 pcf2127_i2c_driver.driver.name, id->driver_data);
907b3262
AM		 919}
920
907b3262 921static struct i2c_driver pcf2127_i2c_driver = {
18cb6368 922 .driver = {
907b3262 923 .name = "rtc-pcf2127-i2c",
18cb6368
RC		 924 .of_match_table = of_match_ptr(pcf2127_of_match),
925 },
5418e595 926 .probe_new = pcf2127_i2c_probe,
907b3262 927 .id_table = pcf2127_i2c_id,
18cb6368 928};
9408ec1a
AM		 929
930static int pcf2127_i2c_register_driver(void)
931{
932 return i2c_add_driver(&pcf2127_i2c_driver);
933}
934
935static void pcf2127_i2c_unregister_driver(void)
936{
937 i2c_del_driver(&pcf2127_i2c_driver);
938}
939
940#else
941
942static int pcf2127_i2c_register_driver(void)
943{
944 return 0;
945}
946
947static void pcf2127_i2c_unregister_driver(void)
948{
949}
950
951#endif
952
953#if IS_ENABLED(CONFIG_SPI_MASTER)
954
955static struct spi_driver pcf2127_spi_driver;
956
957static int pcf2127_spi_probe(struct spi_device *spi)
958{
959 static const struct regmap_config config = {
960 .reg_bits = 8,
961 .val_bits = 8,
962 .read_flag_mask = 0xa0,
963 .write_flag_mask = 0x20,
040e6dc0 964 .max_register = 0x1d,
9408ec1a
AM		 965 };
966 struct regmap *regmap;
967
968 regmap = devm_regmap_init_spi(spi, &config);
969 if (IS_ERR(regmap)) {
970 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
971 __func__, PTR_ERR(regmap));
972 return PTR_ERR(regmap);
973 }
974
27006416
AB		 975 return pcf2127_probe(&spi->dev, regmap, spi->irq,
976 pcf2127_spi_driver.driver.name,
d6c3029f 977 spi_get_device_id(spi)->driver_data);
9408ec1a
AM		 978}
979
980static const struct spi_device_id pcf2127_spi_id[] = {
d6c3029f 981 { "pcf2127", 1 },
cee2cc21 982 { "pcf2129", 0 },
985b30db 983 { "pca2129", 0 },
9408ec1a
AM		 984 { }
985};
986MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
987
988static struct spi_driver pcf2127_spi_driver = {
989 .driver = {
990 .name = "rtc-pcf2127-spi",
991 .of_match_table = of_match_ptr(pcf2127_of_match),
992 },
993 .probe = pcf2127_spi_probe,
994 .id_table = pcf2127_spi_id,
995};
996
997static int pcf2127_spi_register_driver(void)
998{
999 return spi_register_driver(&pcf2127_spi_driver);
1000}
1001
1002static void pcf2127_spi_unregister_driver(void)
1003{
1004 spi_unregister_driver(&pcf2127_spi_driver);
1005}
1006
1007#else
1008
1009static int pcf2127_spi_register_driver(void)
1010{
1011 return 0;
1012}
1013
1014static void pcf2127_spi_unregister_driver(void)
1015{
1016}
1017
1018#endif
1019
1020static int __init pcf2127_init(void)
1021{
1022 int ret;
1023
1024 ret = pcf2127_i2c_register_driver();
1025 if (ret) {
1026 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
1027 return ret;
1028 }
1029
1030 ret = pcf2127_spi_register_driver();
1031 if (ret) {
1032 pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
1033 pcf2127_i2c_unregister_driver();
1034 }
1035
1036 return ret;
1037}
1038module_init(pcf2127_init)
1039
1040static void __exit pcf2127_exit(void)
1041{
1042 pcf2127_spi_unregister_driver();
1043 pcf2127_i2c_unregister_driver();
1044}
1045module_exit(pcf2127_exit)
18cb6368
RC		 1046
1047MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
cee2cc21 1048MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
4d8318bc 1049MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)