[linux-2.6-block.git] / drivers / rtc / rtc-pcf2123.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * An SPI driver for the Philips PCF2123 RTC
 * Copyright 2009 Cyber Switching, Inc.
 *
 * Author: Chris Verges <chrisv@cyberswitching.com>
 * Maintainers: http://www.cyberswitching.com
 *
 * based on the RS5C348 driver in this same directory.
 *
 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
 * the sysfs contributions to this driver.
 *
 * Please note that the CS is active high, so platform data
 * should look something like:
 *
 * static struct spi_board_info ek_spi_devices[] = {
 *	...
 *	{
 *		.modalias		= "rtc-pcf2123",
 *		.chip_select		= 1,
 *		.controller_data	= (void *)AT91_PIN_PA10,
 *		.max_speed_hz		= 1000 * 1000,
 *		.mode			= SPI_CS_HIGH,
 *		.bus_num		= 0,
 *	},
 *	...
 *};
 */

#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/regmap.h>

/* REGISTERS */
#define PCF2123_REG_CTRL1	(0x00)	/* Control Register 1 */
#define PCF2123_REG_CTRL2	(0x01)	/* Control Register 2 */
#define PCF2123_REG_SC		(0x02)	/* datetime */
#define PCF2123_REG_MN		(0x03)
#define PCF2123_REG_HR		(0x04)
#define PCF2123_REG_DM		(0x05)
#define PCF2123_REG_DW		(0x06)
#define PCF2123_REG_MO		(0x07)
#define PCF2123_REG_YR		(0x08)
#define PCF2123_REG_ALRM_MN	(0x09)	/* Alarm Registers */
#define PCF2123_REG_ALRM_HR	(0x0a)
#define PCF2123_REG_ALRM_DM	(0x0b)
#define PCF2123_REG_ALRM_DW	(0x0c)
#define PCF2123_REG_OFFSET	(0x0d)	/* Clock Rate Offset Register */
#define PCF2123_REG_TMR_CLKOUT	(0x0e)	/* Timer Registers */
#define PCF2123_REG_CTDWN_TMR	(0x0f)

/* PCF2123_REG_CTRL1 BITS */
#define CTRL1_CLEAR		(0)	/* Clear */
#define CTRL1_CORR_INT		BIT(1)	/* Correction irq enable */
#define CTRL1_12_HOUR		BIT(2)	/* 12 hour time */
#define CTRL1_SW_RESET	(BIT(3) | BIT(4) | BIT(6))	/* Software reset */
#define CTRL1_STOP		BIT(5)	/* Stop the clock */
#define CTRL1_EXT_TEST		BIT(7)	/* External clock test mode */

/* PCF2123_REG_CTRL2 BITS */
#define CTRL2_TIE		BIT(0)	/* Countdown timer irq enable */
#define CTRL2_AIE		BIT(1)	/* Alarm irq enable */
#define CTRL2_TF		BIT(2)	/* Countdown timer flag */
#define CTRL2_AF		BIT(3)	/* Alarm flag */
#define CTRL2_TI_TP		BIT(4)	/* Irq pin generates pulse */
#define CTRL2_MSF		BIT(5)	/* Minute or second irq flag */
#define CTRL2_SI		BIT(6)	/* Second irq enable */
#define CTRL2_MI		BIT(7)	/* Minute irq enable */

/* PCF2123_REG_SC BITS */
#define OSC_HAS_STOPPED		BIT(7)	/* Clock has been stopped */

/* PCF2123_REG_ALRM_XX BITS */
#define ALRM_ENABLE		BIT(7)	/* MN, HR, DM, or DW alarm enable */

/* PCF2123_REG_TMR_CLKOUT BITS */
#define CD_TMR_4096KHZ		(0)	/* 4096 KHz countdown timer */
#define CD_TMR_64HZ		(1)	/* 64 Hz countdown timer */
#define CD_TMR_1HZ		(2)	/* 1 Hz countdown timer */
#define CD_TMR_60th_HZ		(3)	/* 60th Hz countdown timer */
#define CD_TMR_TE		BIT(3)	/* Countdown timer enable */

/* PCF2123_REG_OFFSET BITS */
#define OFFSET_SIGN_BIT		6	/* 2's complement sign bit */
#define OFFSET_COARSE		BIT(7)	/* Coarse mode offset */
#define OFFSET_STEP		(2170)	/* Offset step in parts per billion */
#define OFFSET_MASK		GENMASK(6, 0)	/* Offset value */

/* READ/WRITE ADDRESS BITS */
#define PCF2123_WRITE		BIT(4)
#define PCF2123_READ		(BIT(4) | BIT(7))


static struct spi_driver pcf2123_driver;

struct pcf2123_plat_data {
	struct rtc_device *rtc;
	struct regmap *map;
};

static const struct regmap_config pcf2123_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.read_flag_mask = PCF2123_READ,
	.write_flag_mask = PCF2123_WRITE,
	.max_register = PCF2123_REG_CTDWN_TMR,
};

static int pcf2123_read_offset(struct device *dev, long *offset)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	int ret, val;
	unsigned int reg;

	ret = regmap_read(pdata->map, PCF2123_REG_OFFSET, &reg);
	if (ret)
		return ret;

	val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);

	if (reg & OFFSET_COARSE)
		val *= 2;

	*offset = ((long)val) * OFFSET_STEP;

	return 0;
}

/*
 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
 * The main difference between the two is normal offset adjusts the first
 * second of n minutes every other hour, with 61, 62 and 63 being shoved
 * into the 60th minute.
 * The coarse adjustment does the same, but every hour.
 * the two overlap, with every even normal offset value corresponding
 * to a coarse offset. Based on this algorithm, it seems that despite the
 * name, coarse offset is a better fit for overlapping values.
 */
static int pcf2123_set_offset(struct device *dev, long offset)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	s8 reg;

	if (offset > OFFSET_STEP * 127)
		reg = 127;
	else if (offset < OFFSET_STEP * -128)
		reg = -128;
	else
		reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);

	/* choose fine offset only for odd values in the normal range */
	if (reg & 1 && reg <= 63 && reg >= -64) {
		/* Normal offset. Clear the coarse bit */
		reg &= ~OFFSET_COARSE;
	} else {
		/* Coarse offset. Divide by 2 and set the coarse bit */
		reg >>= 1;
		reg |= OFFSET_COARSE;
	}

	return regmap_write(pdata->map, PCF2123_REG_OFFSET, (unsigned int)reg);
}

static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	u8 rxbuf[7];
	int ret;

	ret = regmap_bulk_read(pdata->map, PCF2123_REG_SC, rxbuf,
				sizeof(rxbuf));
	if (ret)
		return ret;

	if (rxbuf[0] & OSC_HAS_STOPPED) {
		dev_info(dev, "clock was stopped. Time is not valid\n");
		return -EINVAL;
	}

	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	tm->tm_wday = rxbuf[4] & 0x07;
	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	tm->tm_year = bcd2bin(rxbuf[6]);
	if (tm->tm_year < 70)
		tm->tm_year += 100;	/* assume we are in 1970...2069 */

	dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);

	return 0;
}

static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	u8 txbuf[7];
	int ret;

	dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);

	/* Stop the counter first */
	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret)
		return ret;

	/* Set the new time */
	txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
	txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
	txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
	txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
	txbuf[4] = tm->tm_wday & 0x07;
	txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	txbuf[6] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);

	ret = regmap_bulk_write(pdata->map, PCF2123_REG_SC, txbuf,
				sizeof(txbuf));
	if (ret)
		return ret;

	/* Start the counter */
	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret)
		return ret;

	return 0;
}

static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	u8 rxbuf[4];
	int ret;
	unsigned int val = 0;

	ret = regmap_bulk_read(pdata->map, PCF2123_REG_ALRM_MN, rxbuf,
				sizeof(rxbuf));
	if (ret)
		return ret;

	alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
	alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
	alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
	alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);

	dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);

	ret = regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);
	if (ret)
		return ret;

	alm->enabled = !!(val & CTRL2_AIE);

	return 0;
}

static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	u8 txbuf[4];
	int ret;

	dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);

	/* Ensure alarm flag is clear */
	ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
	if (ret)
		return ret;

	/* Disable alarm interrupt */
	ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
	if (ret)
		return ret;

	/* Set new alarm */
	txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
	txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
	txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
	txbuf[3] = bin2bcd(alm->time.tm_wday & 0x07);

	ret = regmap_bulk_write(pdata->map, PCF2123_REG_ALRM_MN, txbuf,
				sizeof(txbuf));
	if (ret)
		return ret;

	/* Enable alarm interrupt */
	if (alm->enabled)	{
		ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2,
						CTRL2_AIE, CTRL2_AIE);
		if (ret)
			return ret;
	}

	return 0;
}

static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	struct mutex *lock = &pdata->rtc->ops_lock;
	unsigned int val = 0;
	int ret = IRQ_NONE;

	mutex_lock(lock);
	regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);

	/* Alarm? */
	if (val & CTRL2_AF) {
		ret = IRQ_HANDLED;

		/* Clear alarm flag */
		regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);

		rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
	}

	mutex_unlock(lock);

	return ret;
}

static int pcf2123_reset(struct device *dev)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	int ret;
	unsigned int val = 0;

	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
	if (ret)
		return ret;

	/* Stop the counter */
	dev_dbg(dev, "stopping RTC\n");
	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret)
		return ret;

	/* See if the counter was actually stopped */
	dev_dbg(dev, "checking for presence of RTC\n");
	ret = regmap_read(pdata->map, PCF2123_REG_CTRL1, &val);
	if (ret)
		return ret;

	dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
	if (!(val & CTRL1_STOP))
		return -ENODEV;

	/* Start the counter */
	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret)
		return ret;

	return 0;
}

static const struct rtc_class_ops pcf2123_rtc_ops = {
	.read_time	= pcf2123_rtc_read_time,
	.set_time	= pcf2123_rtc_set_time,
	.read_offset	= pcf2123_read_offset,
	.set_offset	= pcf2123_set_offset,
	.read_alarm	= pcf2123_rtc_read_alarm,
	.set_alarm	= pcf2123_rtc_set_alarm,
};

static int pcf2123_probe(struct spi_device *spi)
{
	struct rtc_device *rtc;
	struct rtc_time tm;
	struct pcf2123_plat_data *pdata;
	int ret = 0;

	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
				GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;
	spi->dev.platform_data = pdata;

	pdata->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);

	if (IS_ERR(pdata->map)) {
		dev_err(&spi->dev, "regmap init failed.\n");
		goto kfree_exit;
	}

	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
	if (ret < 0) {
		ret = pcf2123_reset(&spi->dev);
		if (ret < 0) {
			dev_err(&spi->dev, "chip not found\n");
			goto kfree_exit;
		}
	}

	dev_info(&spi->dev, "spiclk %u KHz.\n",
			(spi->max_speed_hz + 500) / 1000);

	/* Finalize the initialization */
	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
			&pcf2123_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc)) {
		dev_err(&spi->dev, "failed to register.\n");
		ret = PTR_ERR(rtc);
		goto kfree_exit;
	}

	pdata->rtc = rtc;

	/* Register alarm irq */
	if (spi->irq > 0) {
		ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
				pcf2123_rtc_irq,
				IRQF_TRIGGER_LOW | IRQF_ONESHOT,
				pcf2123_driver.driver.name, &spi->dev);
		if (!ret)
			device_init_wakeup(&spi->dev, true);
		else
			dev_err(&spi->dev, "could not request irq.\n");
	}

	/* The PCF2123's alarm only has minute accuracy. Must add timer
	 * support to this driver to generate interrupts more than once
	 * per minute.
	 */
	pdata->rtc->uie_unsupported = 1;

	return 0;

kfree_exit:
	spi->dev.platform_data = NULL;
	return ret;
}

#ifdef CONFIG_OF
static const struct of_device_id pcf2123_dt_ids[] = {
	{ .compatible = "nxp,rtc-pcf2123", },
	{ .compatible = "microcrystal,rv2123", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
#endif

static struct spi_driver pcf2123_driver = {
	.driver	= {
			.name	= "rtc-pcf2123",
			.of_match_table = of_match_ptr(pcf2123_dt_ids),
	},
	.probe	= pcf2123_probe,
};

module_spi_driver(pcf2123_driver);

MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
7f3923a1 CV	2	/*
	3	* An SPI driver for the Philips PCF2123 RTC
	4	* Copyright 2009 Cyber Switching, Inc.
	5	*
	6	* Author: Chris Verges <chrisv@cyberswitching.com>
	7	* Maintainers: http://www.cyberswitching.com
	8	*
	9	* based on the RS5C348 driver in this same directory.
	10	*
	11	* Thanks to Christian Pellegrin <chripell@fsfe.org> for
	12	* the sysfs contributions to this driver.
	13	*
7f3923a1 CV	14	* Please note that the CS is active high, so platform data
	15	* should look something like:
	16	*
	17	* static struct spi_board_info ek_spi_devices[] = {
369015fb SK	18	* ...
	19	* {
	20	* .modalias = "rtc-pcf2123",
	21	* .chip_select = 1,
	22	* .controller_data = (void *)AT91_PIN_PA10,
7f3923a1 CV	23	* .max_speed_hz = 1000 * 1000,
	24	* .mode = SPI_CS_HIGH,
	25	* .bus_num = 0,
	26	* },
	27	* ...
	28	*};
7f3923a1 CV	29	*/
	30
	31	#include <linux/bcd.h>
	32	#include <linux/delay.h>
	33	#include <linux/device.h>
	34	#include <linux/errno.h>
	35	#include <linux/init.h>
	36	#include <linux/kernel.h>
3fc70077	37	#include <linux/of.h>
7f3923a1	38	#include <linux/string.h>
5a0e3ad6	39	#include <linux/slab.h>
7f3923a1 CV	40	#include <linux/rtc.h>
7f3923a1 CV	41	#include <linux/spi/spi.h>
2113852b	42	#include <linux/module.h>
790d0339	43	#include <linux/regmap.h>
7f3923a1	44
245cb74b	45	/* REGISTERS */
7f3923a1 CV	46	#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
	47	#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
	48	#define PCF2123_REG_SC (0x02) /* datetime */
	49	#define PCF2123_REG_MN (0x03)
	50	#define PCF2123_REG_HR (0x04)
	51	#define PCF2123_REG_DM (0x05)
	52	#define PCF2123_REG_DW (0x06)
	53	#define PCF2123_REG_MO (0x07)
	54	#define PCF2123_REG_YR (0x08)
245cb74b JC	55	#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
	56	#define PCF2123_REG_ALRM_HR (0x0a)
	57	#define PCF2123_REG_ALRM_DM (0x0b)
	58	#define PCF2123_REG_ALRM_DW (0x0c)
	59	#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
	60	#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
	61	#define PCF2123_REG_CTDWN_TMR (0x0f)
	62
	63	/* PCF2123_REG_CTRL1 BITS */
	64	#define CTRL1_CLEAR (0) /* Clear */
	65	#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
	66	#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
	67	#define CTRL1_SW_RESET (BIT(3) \| BIT(4) \| BIT(6)) /* Software reset */
	68	#define CTRL1_STOP BIT(5) /* Stop the clock */
	69	#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
	70
	71	/* PCF2123_REG_CTRL2 BITS */
	72	#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
	73	#define CTRL2_AIE BIT(1) /* Alarm irq enable */
	74	#define CTRL2_TF BIT(2) /* Countdown timer flag */
	75	#define CTRL2_AF BIT(3) /* Alarm flag */
	76	#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
	77	#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
	78	#define CTRL2_SI BIT(6) /* Second irq enable */
	79	#define CTRL2_MI BIT(7) /* Minute irq enable */
	80
	81	/* PCF2123_REG_SC BITS */
	82	#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
	83
	84	/* PCF2123_REG_ALRM_XX BITS */
	85	#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
	86
	87	/* PCF2123_REG_TMR_CLKOUT BITS */
	88	#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
	89	#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
	90	#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
	91	#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
	92	#define CD_TMR_TE BIT(3) /* Countdown timer enable */
	93
	94	/* PCF2123_REG_OFFSET BITS */
82df3e04	95	#define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
245cb74b	96	#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
bae2f647	97	#define OFFSET_STEP (2170) /* Offset step in parts per billion */
790d0339	98	#define OFFSET_MASK GENMASK(6, 0) /* Offset value */
245cb74b JC	99
	100	/* READ/WRITE ADDRESS BITS */
	101	#define PCF2123_WRITE BIT(4)
	102	#define PCF2123_READ (BIT(4) \| BIT(7))
7f3923a1	103
7f3923a1 CV	104
	105	static struct spi_driver pcf2123_driver;
	106
7f3923a1 CV	107	struct pcf2123_plat_data {
7f3923a1 CV	108	struct rtc_device *rtc;
790d0339	109	struct regmap *map;
7f3923a1 CV	110	};
7f3923a1 CV	111
790d0339 DH	112	static const struct regmap_config pcf2123_regmap_config = {
	113	.reg_bits = 8,
	114	.val_bits = 8,
	115	.read_flag_mask = PCF2123_READ,
	116	.write_flag_mask = PCF2123_WRITE,
	117	.max_register = PCF2123_REG_CTDWN_TMR,
	118	};
7f3923a1	119
bae2f647	120	static int pcf2123_read_offset(struct device dev, long offset)
83ab7dad	121	{
790d0339 DH	122	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	123	int ret, val;
	124	unsigned int reg;
7f3923a1	125
790d0339	126	ret = regmap_read(pdata->map, PCF2123_REG_OFFSET, &reg);
4c5591c1 JH	127	if (ret)
	128	return ret;
	129
790d0339	130	val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
bae2f647 JC	131
bae2f647 JC	132	if (reg & OFFSET_COARSE)
790d0339	133	val *= 2;
bae2f647	134
790d0339	135	offset = ((long)val) OFFSET_STEP;
bae2f647 JC	136
	137	return 0;
	138	}
	139
	140	/*
	141	* The offset register is a 7 bit signed value with a coarse bit in bit 7.
	142	* The main difference between the two is normal offset adjusts the first
	143	* second of n minutes every other hour, with 61, 62 and 63 being shoved
	144	* into the 60th minute.
	145	* The coarse adjustment does the same, but every hour.
	146	* the two overlap, with every even normal offset value corresponding
	147	* to a coarse offset. Based on this algorithm, it seems that despite the
	148	* name, coarse offset is a better fit for overlapping values.
	149	*/
	150	static int pcf2123_set_offset(struct device *dev, long offset)
	151	{
790d0339	152	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
bae2f647 JC	153	s8 reg;
	154
	155	if (offset > OFFSET_STEP * 127)
	156	reg = 127;
	157	else if (offset < OFFSET_STEP * -128)
	158	reg = -128;
	159	else
fedc459a	160	reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
bae2f647 JC	161
	162	/* choose fine offset only for odd values in the normal range */
	163	if (reg & 1 && reg <= 63 && reg >= -64) {
	164	/* Normal offset. Clear the coarse bit */
	165	reg &= ~OFFSET_COARSE;
	166	} else {
	167	/* Coarse offset. Divide by 2 and set the coarse bit */
	168	reg >>= 1;
	169	reg \|= OFFSET_COARSE;
	170	}
	171
790d0339	172	return regmap_write(pdata->map, PCF2123_REG_OFFSET, (unsigned int)reg);
bae2f647 JC	173	}
bae2f647 JC	174
7f3923a1 CV	175	static int pcf2123_rtc_read_time(struct device dev, struct rtc_time tm)
7f3923a1 CV	176	{
790d0339	177	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
66c056d6	178	u8 rxbuf[7];
7f3923a1 CV	179	int ret;
7f3923a1 CV	180
790d0339 DH	181	ret = regmap_bulk_read(pdata->map, PCF2123_REG_SC, rxbuf,
	182	sizeof(rxbuf));
	183	if (ret)
7f3923a1	184	return ret;
7f3923a1	185
f07fa924 JC	186	if (rxbuf[0] & OSC_HAS_STOPPED) {
	187	dev_info(dev, "clock was stopped. Time is not valid\n");
	188	return -EINVAL;
	189	}
	190
7f3923a1 CV	191	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	192	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	193	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	194	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	195	tm->tm_wday = rxbuf[4] & 0x07;
	196	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	197	tm->tm_year = bcd2bin(rxbuf[6]);
	198	if (tm->tm_year < 70)
	199	tm->tm_year += 100; /* assume we are in 1970...2069 */
	200
c33850bb	201	dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
7f3923a1	202
22652ba7	203	return 0;
7f3923a1 CV	204	}
	205
	206	static int pcf2123_rtc_set_time(struct device dev, struct rtc_time tm)
	207	{
790d0339 DH	208	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
790d0339 DH	209	u8 txbuf[7];
7f3923a1 CV	210	int ret;
7f3923a1 CV	211
c33850bb	212	dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
7f3923a1 CV	213
7f3923a1 CV	214	/* Stop the counter first */
790d0339 DH	215	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
790d0339 DH	216	if (ret)
7f3923a1	217	return ret;
7f3923a1 CV	218
7f3923a1 CV	219	/* Set the new time */
790d0339 DH	220	txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
	221	txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
	222	txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
	223	txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
	224	txbuf[4] = tm->tm_wday & 0x07;
	225	txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	226	txbuf[6] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
	227
	228	ret = regmap_bulk_write(pdata->map, PCF2123_REG_SC, txbuf,
	229	sizeof(txbuf));
	230	if (ret)
7f3923a1	231	return ret;
7f3923a1 CV	232
7f3923a1 CV	233	/* Start the counter */
790d0339 DH	234	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
790d0339 DH	235	if (ret)
7f3923a1	236	return ret;
7f3923a1 CV	237
	238	return 0;
	239	}
	240
e32e60a2 DH	241	static int pcf2123_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
	242	{
	243	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	244	u8 rxbuf[4];
	245	int ret;
	246	unsigned int val = 0;
	247
	248	ret = regmap_bulk_read(pdata->map, PCF2123_REG_ALRM_MN, rxbuf,
	249	sizeof(rxbuf));
	250	if (ret)
	251	return ret;
	252
	253	alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
	254	alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
	255	alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
	256	alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
	257
	258	dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
	259
	260	ret = regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);
	261	if (ret)
	262	return ret;
	263
	264	alm->enabled = !!(val & CTRL2_AIE);
	265
	266	return 0;
	267	}
	268
	269	static int pcf2123_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
	270	{
	271	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	272	u8 txbuf[4];
	273	int ret;
	274
	275	dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
	276
	277	/* Ensure alarm flag is clear */
	278	ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
	279	if (ret)
7f3923a1	280	return ret;
7f3923a1	281
e32e60a2 DH	282	/* Disable alarm interrupt */
	283	ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
	284	if (ret)
	285	return ret;
	286
	287	/* Set new alarm */
	288	txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
	289	txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
	290	txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
	291	txbuf[3] = bin2bcd(alm->time.tm_wday & 0x07);
	292
	293	ret = regmap_bulk_write(pdata->map, PCF2123_REG_ALRM_MN, txbuf,
	294	sizeof(txbuf));
	295	if (ret)
	296	return ret;
	297
	298	/* Enable alarm interrupt */
	299	if (alm->enabled) {
	300	ret = regmap_update_bits(pdata->map, PCF2123_REG_CTRL2,
	301	CTRL2_AIE, CTRL2_AIE);
	302	if (ret)
	303	return ret;
	304	}
	305
7f3923a1 CV	306	return 0;
	307	}
	308
e32e60a2 DH	309	static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
	310	{
	311	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
	312	struct mutex *lock = &pdata->rtc->ops_lock;
	313	unsigned int val = 0;
	314	int ret = IRQ_NONE;
	315
	316	mutex_lock(lock);
	317	regmap_read(pdata->map, PCF2123_REG_CTRL2, &val);
	318
	319	/* Alarm? */
	320	if (val & CTRL2_AF) {
	321	ret = IRQ_HANDLED;
	322
	323	/* Clear alarm flag */
	324	regmap_update_bits(pdata->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
	325
	326	rtc_update_irq(pdata->rtc, 1, RTC_IRQF \| RTC_AF);
	327	}
	328
	329	mutex_unlock(lock);
	330
	331	return ret;
	332	}
	333
1e094b94 JC	334	static int pcf2123_reset(struct device *dev)
1e094b94 JC	335	{
790d0339	336	struct pcf2123_plat_data *pdata = dev_get_platdata(dev);
1e094b94	337	int ret;
790d0339	338	unsigned int val = 0;
1e094b94	339
790d0339 DH	340	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
790d0339 DH	341	if (ret)
1e094b94 JC	342	return ret;
	343
	344	/* Stop the counter */
	345	dev_dbg(dev, "stopping RTC\n");
790d0339 DH	346	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_STOP);
790d0339 DH	347	if (ret)
1e094b94 JC	348	return ret;
	349
	350	/* See if the counter was actually stopped */
	351	dev_dbg(dev, "checking for presence of RTC\n");
790d0339 DH	352	ret = regmap_read(pdata->map, PCF2123_REG_CTRL1, &val);
790d0339 DH	353	if (ret)
1e094b94 JC	354	return ret;
1e094b94 JC	355
790d0339 DH	356	dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
790d0339 DH	357	if (!(val & CTRL1_STOP))
1e094b94 JC	358	return -ENODEV;
	359
	360	/* Start the counter */
790d0339 DH	361	ret = regmap_write(pdata->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
790d0339 DH	362	if (ret)
1e094b94 JC	363	return ret;
	364
	365	return 0;
	366	}
	367
7f3923a1 CV	368	static const struct rtc_class_ops pcf2123_rtc_ops = {
	369	.read_time = pcf2123_rtc_read_time,
	370	.set_time = pcf2123_rtc_set_time,
bae2f647 JC	371	.read_offset = pcf2123_read_offset,
bae2f647 JC	372	.set_offset = pcf2123_set_offset,
e32e60a2 DH	373	.read_alarm = pcf2123_rtc_read_alarm,
e32e60a2 DH	374	.set_alarm = pcf2123_rtc_set_alarm,
7f3923a1 CV	375	};
7f3923a1 CV	376
5a167f45	377	static int pcf2123_probe(struct spi_device *spi)
7f3923a1 CV	378	{
7f3923a1 CV	379	struct rtc_device *rtc;
f07fa924	380	struct rtc_time tm;
7f3923a1	381	struct pcf2123_plat_data *pdata;
e32e60a2	382	int ret = 0;
7f3923a1	383
dd48ccc4 JH	384	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
dd48ccc4 JH	385	GFP_KERNEL);
7f3923a1 CV	386	if (!pdata)
	387	return -ENOMEM;
	388	spi->dev.platform_data = pdata;
	389
790d0339 DH	390	pdata->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
	391
	392	if (IS_ERR(pdata->map)) {
	393	dev_err(&spi->dev, "regmap init failed.\n");
	394	goto kfree_exit;
	395	}
	396
f07fa924	397	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
1e094b94	398	if (ret < 0) {
f07fa924 JC	399	ret = pcf2123_reset(&spi->dev);
	400	if (ret < 0) {
	401	dev_err(&spi->dev, "chip not found\n");
	402	goto kfree_exit;
	403	}
7f3923a1 CV	404	}
7f3923a1 CV	405
7f3923a1 CV	406	dev_info(&spi->dev, "spiclk %u KHz.\n",
	407	(spi->max_speed_hz + 500) / 1000);
	408
7f3923a1	409	/* Finalize the initialization */
dd48ccc4	410	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
7f3923a1 CV	411	&pcf2123_rtc_ops, THIS_MODULE);
	412
	413	if (IS_ERR(rtc)) {
	414	dev_err(&spi->dev, "failed to register.\n");
	415	ret = PTR_ERR(rtc);
	416	goto kfree_exit;
	417	}
	418
	419	pdata->rtc = rtc;
	420
e32e60a2 DH	421	/* Register alarm irq */
	422	if (spi->irq > 0) {
	423	ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
	424	pcf2123_rtc_irq,
	425	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	426	pcf2123_driver.driver.name, &spi->dev);
	427	if (!ret)
	428	device_init_wakeup(&spi->dev, true);
	429	else
	430	dev_err(&spi->dev, "could not request irq.\n");
7f3923a1 CV	431	}
7f3923a1 CV	432
e32e60a2 DH	433	/* The PCF2123's alarm only has minute accuracy. Must add timer
	434	* support to this driver to generate interrupts more than once
	435	* per minute.
	436	*/
	437	pdata->rtc->uie_unsupported = 1;
f3d2570a	438
7f3923a1	439	return 0;
f3d2570a	440
7f3923a1	441	kfree_exit:
7f3923a1 CV	442	spi->dev.platform_data = NULL;
	443	return ret;
	444	}
	445
3fc70077 JC	446	#ifdef CONFIG_OF
	447	static const struct of_device_id pcf2123_dt_ids[] = {
	448	{ .compatible = "nxp,rtc-pcf2123", },
3c3d7101	449	{ .compatible = "microcrystal,rv2123", },
3fc70077 JC	450	{ /* sentinel */ }
	451	};
	452	MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
	453	#endif
	454
7f3923a1 CV	455	static struct spi_driver pcf2123_driver = {
	456	.driver = {
	457	.name = "rtc-pcf2123",
3fc70077	458	.of_match_table = of_match_ptr(pcf2123_dt_ids),
7f3923a1 CV	459	},
7f3923a1 CV	460	.probe = pcf2123_probe,
7f3923a1 CV	461	};
7f3923a1 CV	462
109e9418	463	module_spi_driver(pcf2123_driver);
7f3923a1 CV	464
	465	MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
	466	MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
	467	MODULE_LICENSE("GPL");