Commit | Line | Data |
---|---|---|
db68b189 | 1 | /* |
10211ae3 | 2 | * TI OMAP Real Time Clock interface for Linux |
db68b189 DB |
3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
6 | * | |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | |
0125138d | 8 | * Copyright (C) 2014 Johan Hovold <johan@kernel.org> |
db68b189 DB |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
97ea1906 MN |
16 | #include <dt-bindings/gpio/gpio.h> |
17 | #include <linux/bcd.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/delay.h> | |
db68b189 | 20 | #include <linux/init.h> |
97ea1906 | 21 | #include <linux/io.h> |
db68b189 | 22 | #include <linux/ioport.h> |
97ea1906 MN |
23 | #include <linux/kernel.h> |
24 | #include <linux/module.h> | |
9e0344dc AM |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
97ea1906 MN |
27 | #include <linux/pinctrl/pinctrl.h> |
28 | #include <linux/pinctrl/pinconf.h> | |
29 | #include <linux/pinctrl/pinconf-generic.h> | |
30 | #include <linux/platform_device.h> | |
fc9bd902 | 31 | #include <linux/pm_runtime.h> |
97ea1906 | 32 | #include <linux/rtc.h> |
db68b189 | 33 | |
10211ae3 JH |
34 | /* |
35 | * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock | |
db68b189 DB |
36 | * with century-range alarm matching, driven by the 32kHz clock. |
37 | * | |
38 | * The main user-visible ways it differs from PC RTCs are by omitting | |
39 | * "don't care" alarm fields and sub-second periodic IRQs, and having | |
40 | * an autoadjust mechanism to calibrate to the true oscillator rate. | |
41 | * | |
42 | * Board-specific wiring options include using split power mode with | |
43 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), | |
44 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from | |
fa5b0782 SN |
45 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
46 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | |
db68b189 DB |
47 | */ |
48 | ||
db68b189 DB |
49 | /* RTC registers */ |
50 | #define OMAP_RTC_SECONDS_REG 0x00 | |
51 | #define OMAP_RTC_MINUTES_REG 0x04 | |
52 | #define OMAP_RTC_HOURS_REG 0x08 | |
53 | #define OMAP_RTC_DAYS_REG 0x0C | |
54 | #define OMAP_RTC_MONTHS_REG 0x10 | |
55 | #define OMAP_RTC_YEARS_REG 0x14 | |
56 | #define OMAP_RTC_WEEKS_REG 0x18 | |
57 | ||
58 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 | |
59 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 | |
60 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 | |
61 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c | |
62 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 | |
63 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 | |
64 | ||
65 | #define OMAP_RTC_CTRL_REG 0x40 | |
66 | #define OMAP_RTC_STATUS_REG 0x44 | |
67 | #define OMAP_RTC_INTERRUPTS_REG 0x48 | |
68 | ||
69 | #define OMAP_RTC_COMP_LSB_REG 0x4c | |
70 | #define OMAP_RTC_COMP_MSB_REG 0x50 | |
71 | #define OMAP_RTC_OSC_REG 0x54 | |
72 | ||
cab1458c AM |
73 | #define OMAP_RTC_KICK0_REG 0x6c |
74 | #define OMAP_RTC_KICK1_REG 0x70 | |
75 | ||
8af750e3 HG |
76 | #define OMAP_RTC_IRQWAKEEN 0x7c |
77 | ||
222a12fc JH |
78 | #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 |
79 | #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 | |
80 | #define OMAP_RTC_ALARM2_HOURS_REG 0x88 | |
81 | #define OMAP_RTC_ALARM2_DAYS_REG 0x8c | |
82 | #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 | |
83 | #define OMAP_RTC_ALARM2_YEARS_REG 0x94 | |
84 | ||
85 | #define OMAP_RTC_PMIC_REG 0x98 | |
86 | ||
db68b189 | 87 | /* OMAP_RTC_CTRL_REG bit fields: */ |
92adb96a SN |
88 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
89 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | |
90 | #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) | |
91 | #define OMAP_RTC_CTRL_TEST BIT(4) | |
92 | #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) | |
93 | #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) | |
94 | #define OMAP_RTC_CTRL_ROUND_30S BIT(1) | |
95 | #define OMAP_RTC_CTRL_STOP BIT(0) | |
db68b189 DB |
96 | |
97 | /* OMAP_RTC_STATUS_REG bit fields: */ | |
92adb96a | 98 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
222a12fc | 99 | #define OMAP_RTC_STATUS_ALARM2 BIT(7) |
92adb96a SN |
100 | #define OMAP_RTC_STATUS_ALARM BIT(6) |
101 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | |
102 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | |
103 | #define OMAP_RTC_STATUS_1M_EVENT BIT(3) | |
104 | #define OMAP_RTC_STATUS_1S_EVENT BIT(2) | |
105 | #define OMAP_RTC_STATUS_RUN BIT(1) | |
106 | #define OMAP_RTC_STATUS_BUSY BIT(0) | |
db68b189 DB |
107 | |
108 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | |
222a12fc | 109 | #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) |
92adb96a SN |
110 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
111 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | |
db68b189 | 112 | |
cd914bba SN |
113 | /* OMAP_RTC_OSC_REG bit fields: */ |
114 | #define OMAP_RTC_OSC_32KCLK_EN BIT(6) | |
399cf0f6 | 115 | #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3) |
3984903a | 116 | #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4) |
cd914bba | 117 | |
8af750e3 | 118 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
92adb96a | 119 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
8af750e3 | 120 | |
222a12fc JH |
121 | /* OMAP_RTC_PMIC bit fields: */ |
122 | #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) | |
97ea1906 MN |
123 | #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x) |
124 | #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x) | |
222a12fc | 125 | |
cab1458c AM |
126 | /* OMAP_RTC_KICKER values */ |
127 | #define KICK0_VALUE 0x83e70b13 | |
128 | #define KICK1_VALUE 0x95a4f1e0 | |
129 | ||
9c28bd07 LV |
130 | struct omap_rtc; |
131 | ||
2153f949 JH |
132 | struct omap_rtc_device_type { |
133 | bool has_32kclk_en; | |
2153f949 | 134 | bool has_irqwakeen; |
222a12fc | 135 | bool has_pmic_mode; |
9291e340 | 136 | bool has_power_up_reset; |
9c28bd07 LV |
137 | void (*lock)(struct omap_rtc *rtc); |
138 | void (*unlock)(struct omap_rtc *rtc); | |
2153f949 | 139 | }; |
cd914bba | 140 | |
55ba953a JH |
141 | struct omap_rtc { |
142 | struct rtc_device *rtc; | |
143 | void __iomem *base; | |
532409aa | 144 | struct clk *clk; |
55ba953a JH |
145 | int irq_alarm; |
146 | int irq_timer; | |
147 | u8 interrupts_reg; | |
222a12fc | 148 | bool is_pmic_controller; |
399cf0f6 | 149 | bool has_ext_clk; |
efce21fc | 150 | bool is_suspending; |
2153f949 | 151 | const struct omap_rtc_device_type *type; |
97ea1906 | 152 | struct pinctrl_dev *pctldev; |
55ba953a | 153 | }; |
db68b189 | 154 | |
55ba953a JH |
155 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
156 | { | |
157 | return readb(rtc->base + reg); | |
158 | } | |
cab1458c | 159 | |
c253a896 JH |
160 | static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) |
161 | { | |
162 | return readl(rtc->base + reg); | |
163 | } | |
164 | ||
55ba953a JH |
165 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
166 | { | |
167 | writeb(val, rtc->base + reg); | |
168 | } | |
db68b189 | 169 | |
55ba953a JH |
170 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) |
171 | { | |
172 | writel(val, rtc->base + reg); | |
173 | } | |
db68b189 | 174 | |
9c28bd07 LV |
175 | static void am3352_rtc_unlock(struct omap_rtc *rtc) |
176 | { | |
177 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); | |
178 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); | |
179 | } | |
180 | ||
181 | static void am3352_rtc_lock(struct omap_rtc *rtc) | |
182 | { | |
183 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); | |
184 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0); | |
185 | } | |
186 | ||
187 | static void default_rtc_unlock(struct omap_rtc *rtc) | |
188 | { | |
189 | } | |
190 | ||
191 | static void default_rtc_lock(struct omap_rtc *rtc) | |
192 | { | |
193 | } | |
194 | ||
10211ae3 JH |
195 | /* |
196 | * We rely on the rtc framework to handle locking (rtc->ops_lock), | |
db68b189 DB |
197 | * so the only other requirement is that register accesses which |
198 | * require BUSY to be clear are made with IRQs locally disabled | |
199 | */ | |
55ba953a | 200 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
db68b189 | 201 | { |
10211ae3 JH |
202 | int count; |
203 | u8 status; | |
db68b189 DB |
204 | |
205 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | |
206 | for (count = 0; count < 50; count++) { | |
55ba953a | 207 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
10211ae3 | 208 | if (!(status & OMAP_RTC_STATUS_BUSY)) |
db68b189 DB |
209 | break; |
210 | udelay(1); | |
211 | } | |
212 | /* now we have ~15 usec to read/write various registers */ | |
213 | } | |
214 | ||
55ba953a | 215 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
db68b189 | 216 | { |
10211ae3 JH |
217 | struct omap_rtc *rtc = dev_id; |
218 | unsigned long events = 0; | |
219 | u8 irq_data; | |
db68b189 | 220 | |
55ba953a | 221 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
222 | |
223 | /* alarm irq? */ | |
224 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | |
9c28bd07 | 225 | rtc->type->unlock(rtc); |
55ba953a | 226 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
9c28bd07 | 227 | rtc->type->lock(rtc); |
db68b189 DB |
228 | events |= RTC_IRQF | RTC_AF; |
229 | } | |
230 | ||
231 | /* 1/sec periodic/update irq? */ | |
232 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | |
233 | events |= RTC_IRQF | RTC_UF; | |
234 | ||
55ba953a | 235 | rtc_update_irq(rtc->rtc, 1, events); |
db68b189 DB |
236 | |
237 | return IRQ_HANDLED; | |
238 | } | |
239 | ||
16380c15 JS |
240 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
241 | { | |
55ba953a | 242 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 243 | u8 reg, irqwake_reg = 0; |
16380c15 JS |
244 | |
245 | local_irq_disable(); | |
55ba953a JH |
246 | rtc_wait_not_busy(rtc); |
247 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
2153f949 | 248 | if (rtc->type->has_irqwakeen) |
55ba953a | 249 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
250 | |
251 | if (enabled) { | |
16380c15 | 252 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
253 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
254 | } else { | |
16380c15 | 255 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
256 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
257 | } | |
55ba953a | 258 | rtc_wait_not_busy(rtc); |
9c28bd07 | 259 | rtc->type->unlock(rtc); |
55ba953a | 260 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 261 | if (rtc->type->has_irqwakeen) |
55ba953a | 262 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 263 | rtc->type->lock(rtc); |
16380c15 JS |
264 | local_irq_enable(); |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
db68b189 DB |
269 | /* this hardware doesn't support "don't care" alarm fields */ |
270 | static int tm2bcd(struct rtc_time *tm) | |
271 | { | |
272 | if (rtc_valid_tm(tm) != 0) | |
273 | return -EINVAL; | |
274 | ||
fe20ba70 AB |
275 | tm->tm_sec = bin2bcd(tm->tm_sec); |
276 | tm->tm_min = bin2bcd(tm->tm_min); | |
277 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
278 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
db68b189 | 279 | |
fe20ba70 | 280 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
db68b189 DB |
281 | |
282 | /* epoch == 1900 */ | |
283 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
284 | return -EINVAL; | |
fe20ba70 | 285 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
db68b189 DB |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static void bcd2tm(struct rtc_time *tm) | |
291 | { | |
fe20ba70 AB |
292 | tm->tm_sec = bcd2bin(tm->tm_sec); |
293 | tm->tm_min = bcd2bin(tm->tm_min); | |
294 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
295 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
296 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
db68b189 | 297 | /* epoch == 1900 */ |
fe20ba70 | 298 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
db68b189 DB |
299 | } |
300 | ||
cbbe326f | 301 | static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) |
db68b189 | 302 | { |
55ba953a JH |
303 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); |
304 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | |
305 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | |
306 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | |
307 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | |
308 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | |
cbbe326f JH |
309 | } |
310 | ||
311 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
312 | { | |
313 | struct omap_rtc *rtc = dev_get_drvdata(dev); | |
db68b189 | 314 | |
cbbe326f JH |
315 | /* we don't report wday/yday/isdst ... */ |
316 | local_irq_disable(); | |
317 | rtc_wait_not_busy(rtc); | |
318 | omap_rtc_read_time_raw(rtc, tm); | |
db68b189 DB |
319 | local_irq_enable(); |
320 | ||
321 | bcd2tm(tm); | |
10211ae3 | 322 | |
db68b189 DB |
323 | return 0; |
324 | } | |
325 | ||
326 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
327 | { | |
55ba953a JH |
328 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
329 | ||
db68b189 DB |
330 | if (tm2bcd(tm) < 0) |
331 | return -EINVAL; | |
10211ae3 | 332 | |
db68b189 | 333 | local_irq_disable(); |
55ba953a | 334 | rtc_wait_not_busy(rtc); |
db68b189 | 335 | |
9c28bd07 | 336 | rtc->type->unlock(rtc); |
55ba953a JH |
337 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
338 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); | |
339 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); | |
340 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); | |
341 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); | |
342 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); | |
9c28bd07 | 343 | rtc->type->lock(rtc); |
db68b189 DB |
344 | |
345 | local_irq_enable(); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
351 | { | |
55ba953a | 352 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
10211ae3 | 353 | u8 interrupts; |
55ba953a | 354 | |
db68b189 | 355 | local_irq_disable(); |
55ba953a | 356 | rtc_wait_not_busy(rtc); |
db68b189 | 357 | |
55ba953a JH |
358 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
359 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); | |
360 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); | |
361 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); | |
362 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); | |
363 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); | |
db68b189 DB |
364 | |
365 | local_irq_enable(); | |
366 | ||
367 | bcd2tm(&alm->time); | |
10211ae3 JH |
368 | |
369 | interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
370 | alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); | |
db68b189 DB |
371 | |
372 | return 0; | |
373 | } | |
374 | ||
375 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
376 | { | |
55ba953a | 377 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 378 | u8 reg, irqwake_reg = 0; |
db68b189 | 379 | |
db68b189 DB |
380 | if (tm2bcd(&alm->time) < 0) |
381 | return -EINVAL; | |
382 | ||
383 | local_irq_disable(); | |
55ba953a | 384 | rtc_wait_not_busy(rtc); |
db68b189 | 385 | |
9c28bd07 | 386 | rtc->type->unlock(rtc); |
55ba953a JH |
387 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
388 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); | |
389 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); | |
390 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); | |
391 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); | |
392 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); | |
db68b189 | 393 | |
55ba953a | 394 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
2153f949 | 395 | if (rtc->type->has_irqwakeen) |
55ba953a | 396 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
397 | |
398 | if (alm->enabled) { | |
db68b189 | 399 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
400 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
401 | } else { | |
db68b189 | 402 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
403 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
404 | } | |
55ba953a | 405 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 406 | if (rtc->type->has_irqwakeen) |
55ba953a | 407 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
9c28bd07 | 408 | rtc->type->lock(rtc); |
db68b189 DB |
409 | |
410 | local_irq_enable(); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
222a12fc JH |
415 | static struct omap_rtc *omap_rtc_power_off_rtc; |
416 | ||
417 | /* | |
418 | * omap_rtc_poweroff: RTC-controlled power off | |
419 | * | |
420 | * The RTC can be used to control an external PMIC via the pmic_power_en pin, | |
421 | * which can be configured to transition to OFF on ALARM2 events. | |
422 | * | |
423 | * Notes: | |
424 | * The two-second alarm offset is the shortest offset possible as the alarm | |
425 | * registers must be set before the next timer update and the offset | |
426 | * calculation is too heavy for everything to be done within a single access | |
427 | * period (~15 us). | |
428 | * | |
429 | * Called with local interrupts disabled. | |
430 | */ | |
431 | static void omap_rtc_power_off(void) | |
432 | { | |
433 | struct omap_rtc *rtc = omap_rtc_power_off_rtc; | |
434 | struct rtc_time tm; | |
435 | unsigned long now; | |
436 | u32 val; | |
437 | ||
9c28bd07 | 438 | rtc->type->unlock(rtc); |
222a12fc JH |
439 | /* enable pmic_power_en control */ |
440 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
441 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); | |
442 | ||
443 | /* set alarm two seconds from now */ | |
444 | omap_rtc_read_time_raw(rtc, &tm); | |
445 | bcd2tm(&tm); | |
446 | rtc_tm_to_time(&tm, &now); | |
447 | rtc_time_to_tm(now + 2, &tm); | |
448 | ||
449 | if (tm2bcd(&tm) < 0) { | |
450 | dev_err(&rtc->rtc->dev, "power off failed\n"); | |
451 | return; | |
452 | } | |
453 | ||
454 | rtc_wait_not_busy(rtc); | |
455 | ||
456 | rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); | |
457 | rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); | |
458 | rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); | |
459 | rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); | |
460 | rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); | |
461 | rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); | |
462 | ||
463 | /* | |
464 | * enable ALARM2 interrupt | |
465 | * | |
466 | * NOTE: this fails on AM3352 if rtc_write (writeb) is used | |
467 | */ | |
468 | val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
469 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, | |
470 | val | OMAP_RTC_INTERRUPTS_IT_ALARM2); | |
9c28bd07 | 471 | rtc->type->lock(rtc); |
222a12fc JH |
472 | |
473 | /* | |
474 | * Wait for alarm to trigger (within two seconds) and external PMIC to | |
475 | * power off the system. Add a 500 ms margin for external latencies | |
476 | * (e.g. debounce circuits). | |
477 | */ | |
478 | mdelay(2500); | |
479 | } | |
480 | ||
34c7b3ac | 481 | static const struct rtc_class_ops omap_rtc_ops = { |
db68b189 DB |
482 | .read_time = omap_rtc_read_time, |
483 | .set_time = omap_rtc_set_time, | |
484 | .read_alarm = omap_rtc_read_alarm, | |
485 | .set_alarm = omap_rtc_set_alarm, | |
16380c15 | 486 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
db68b189 DB |
487 | }; |
488 | ||
2153f949 | 489 | static const struct omap_rtc_device_type omap_rtc_default_type = { |
9291e340 | 490 | .has_power_up_reset = true, |
9c28bd07 LV |
491 | .lock = default_rtc_lock, |
492 | .unlock = default_rtc_unlock, | |
2153f949 JH |
493 | }; |
494 | ||
495 | static const struct omap_rtc_device_type omap_rtc_am3352_type = { | |
496 | .has_32kclk_en = true, | |
2153f949 | 497 | .has_irqwakeen = true, |
222a12fc | 498 | .has_pmic_mode = true, |
9c28bd07 LV |
499 | .lock = am3352_rtc_lock, |
500 | .unlock = am3352_rtc_unlock, | |
2153f949 JH |
501 | }; |
502 | ||
503 | static const struct omap_rtc_device_type omap_rtc_da830_type = { | |
9c28bd07 LV |
504 | .lock = am3352_rtc_lock, |
505 | .unlock = am3352_rtc_unlock, | |
2153f949 | 506 | }; |
9e0344dc | 507 | |
2153f949 | 508 | static const struct platform_device_id omap_rtc_id_table[] = { |
cab1458c | 509 | { |
a430ca22 | 510 | .name = "omap_rtc", |
2153f949 JH |
511 | .driver_data = (kernel_ulong_t)&omap_rtc_default_type, |
512 | }, { | |
8af750e3 | 513 | .name = "am3352-rtc", |
2153f949 JH |
514 | .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, |
515 | }, { | |
cab1458c | 516 | .name = "da830-rtc", |
2153f949 JH |
517 | .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, |
518 | }, { | |
519 | /* sentinel */ | |
520 | } | |
cab1458c | 521 | }; |
2153f949 | 522 | MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); |
cab1458c | 523 | |
9e0344dc | 524 | static const struct of_device_id omap_rtc_of_match[] = { |
2153f949 JH |
525 | { |
526 | .compatible = "ti,am3352-rtc", | |
527 | .data = &omap_rtc_am3352_type, | |
528 | }, { | |
529 | .compatible = "ti,da830-rtc", | |
530 | .data = &omap_rtc_da830_type, | |
531 | }, { | |
532 | /* sentinel */ | |
533 | } | |
9e0344dc AM |
534 | }; |
535 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | |
536 | ||
97ea1906 MN |
537 | static const struct pinctrl_pin_desc rtc_pins_desc[] = { |
538 | PINCTRL_PIN(0, "ext_wakeup0"), | |
539 | PINCTRL_PIN(1, "ext_wakeup1"), | |
540 | PINCTRL_PIN(2, "ext_wakeup2"), | |
541 | PINCTRL_PIN(3, "ext_wakeup3"), | |
542 | }; | |
543 | ||
544 | static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
545 | { | |
546 | return 0; | |
547 | } | |
548 | ||
549 | static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
550 | unsigned int group) | |
551 | { | |
552 | return NULL; | |
553 | } | |
554 | ||
555 | static const struct pinctrl_ops rtc_pinctrl_ops = { | |
556 | .get_groups_count = rtc_pinctrl_get_groups_count, | |
557 | .get_group_name = rtc_pinctrl_get_group_name, | |
558 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
559 | .dt_free_map = pinconf_generic_dt_free_map, | |
560 | }; | |
561 | ||
562 | enum rtc_pin_config_param { | |
563 | PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1, | |
564 | }; | |
565 | ||
566 | static const struct pinconf_generic_params rtc_params[] = { | |
567 | {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0}, | |
568 | }; | |
569 | ||
570 | #ifdef CONFIG_DEBUG_FS | |
571 | static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = { | |
572 | PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false), | |
573 | }; | |
574 | #endif | |
575 | ||
576 | static int rtc_pinconf_get(struct pinctrl_dev *pctldev, | |
577 | unsigned int pin, unsigned long *config) | |
578 | { | |
579 | struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); | |
580 | unsigned int param = pinconf_to_config_param(*config); | |
581 | u32 val; | |
582 | u16 arg = 0; | |
583 | ||
584 | rtc->type->unlock(rtc); | |
585 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
586 | rtc->type->lock(rtc); | |
587 | ||
588 | switch (param) { | |
589 | case PIN_CONFIG_INPUT_ENABLE: | |
590 | if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin))) | |
591 | return -EINVAL; | |
592 | break; | |
593 | case PIN_CONFIG_ACTIVE_HIGH: | |
594 | if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin)) | |
595 | return -EINVAL; | |
596 | break; | |
597 | default: | |
598 | return -ENOTSUPP; | |
599 | }; | |
600 | ||
601 | *config = pinconf_to_config_packed(param, arg); | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | static int rtc_pinconf_set(struct pinctrl_dev *pctldev, | |
607 | unsigned int pin, unsigned long *configs, | |
608 | unsigned int num_configs) | |
609 | { | |
610 | struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); | |
611 | u32 val; | |
612 | unsigned int param; | |
58957d2e | 613 | u32 param_val; |
97ea1906 MN |
614 | int i; |
615 | ||
616 | rtc->type->unlock(rtc); | |
617 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
618 | rtc->type->lock(rtc); | |
619 | ||
620 | /* active low by default */ | |
621 | val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin); | |
622 | ||
623 | for (i = 0; i < num_configs; i++) { | |
624 | param = pinconf_to_config_param(configs[i]); | |
625 | param_val = pinconf_to_config_argument(configs[i]); | |
626 | ||
627 | switch (param) { | |
628 | case PIN_CONFIG_INPUT_ENABLE: | |
629 | if (param_val) | |
630 | val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin); | |
631 | else | |
632 | val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin); | |
633 | break; | |
634 | case PIN_CONFIG_ACTIVE_HIGH: | |
635 | val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin); | |
636 | break; | |
637 | default: | |
638 | dev_err(&rtc->rtc->dev, "Property %u not supported\n", | |
639 | param); | |
640 | return -ENOTSUPP; | |
641 | } | |
642 | } | |
643 | ||
644 | rtc->type->unlock(rtc); | |
645 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val); | |
646 | rtc->type->lock(rtc); | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static const struct pinconf_ops rtc_pinconf_ops = { | |
652 | .is_generic = true, | |
653 | .pin_config_get = rtc_pinconf_get, | |
654 | .pin_config_set = rtc_pinconf_set, | |
655 | }; | |
656 | ||
657 | static struct pinctrl_desc rtc_pinctrl_desc = { | |
658 | .pins = rtc_pins_desc, | |
659 | .npins = ARRAY_SIZE(rtc_pins_desc), | |
660 | .pctlops = &rtc_pinctrl_ops, | |
661 | .confops = &rtc_pinconf_ops, | |
662 | .custom_params = rtc_params, | |
663 | .num_custom_params = ARRAY_SIZE(rtc_params), | |
664 | #ifdef CONFIG_DEBUG_FS | |
665 | .custom_conf_items = rtc_conf_items, | |
666 | #endif | |
667 | .owner = THIS_MODULE, | |
668 | }; | |
669 | ||
5d9094b6 | 670 | static int omap_rtc_probe(struct platform_device *pdev) |
db68b189 | 671 | { |
10211ae3 JH |
672 | struct omap_rtc *rtc; |
673 | struct resource *res; | |
674 | u8 reg, mask, new_ctrl; | |
cab1458c | 675 | const struct platform_device_id *id_entry; |
9e0344dc | 676 | const struct of_device_id *of_id; |
437b37a6 | 677 | int ret; |
9e0344dc | 678 | |
55ba953a JH |
679 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
680 | if (!rtc) | |
681 | return -ENOMEM; | |
682 | ||
9e0344dc | 683 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
2153f949 JH |
684 | if (of_id) { |
685 | rtc->type = of_id->data; | |
222a12fc JH |
686 | rtc->is_pmic_controller = rtc->type->has_pmic_mode && |
687 | of_property_read_bool(pdev->dev.of_node, | |
094d3ee3 | 688 | "system-power-controller"); |
2153f949 JH |
689 | } else { |
690 | id_entry = platform_get_device_id(pdev); | |
691 | rtc->type = (void *)id_entry->driver_data; | |
337b600f SN |
692 | } |
693 | ||
55ba953a JH |
694 | rtc->irq_timer = platform_get_irq(pdev, 0); |
695 | if (rtc->irq_timer <= 0) | |
db68b189 | 696 | return -ENOENT; |
db68b189 | 697 | |
55ba953a JH |
698 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
699 | if (rtc->irq_alarm <= 0) | |
db68b189 | 700 | return -ENOENT; |
db68b189 | 701 | |
399cf0f6 K |
702 | rtc->clk = devm_clk_get(&pdev->dev, "ext-clk"); |
703 | if (!IS_ERR(rtc->clk)) | |
704 | rtc->has_ext_clk = true; | |
705 | else | |
706 | rtc->clk = devm_clk_get(&pdev->dev, "int-clk"); | |
532409aa K |
707 | |
708 | if (!IS_ERR(rtc->clk)) | |
709 | clk_prepare_enable(rtc->clk); | |
710 | ||
db68b189 | 711 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
55ba953a JH |
712 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
713 | if (IS_ERR(rtc->base)) | |
714 | return PTR_ERR(rtc->base); | |
715 | ||
716 | platform_set_drvdata(pdev, rtc); | |
8cfde8c1 | 717 | |
fc9bd902 VH |
718 | /* Enable the clock/module so that we can access the registers */ |
719 | pm_runtime_enable(&pdev->dev); | |
720 | pm_runtime_get_sync(&pdev->dev); | |
721 | ||
9c28bd07 | 722 | rtc->type->unlock(rtc); |
cab1458c | 723 | |
1ed8b5d2 JH |
724 | /* |
725 | * disable interrupts | |
726 | * | |
727 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | |
db68b189 | 728 | */ |
55ba953a | 729 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 730 | |
cd914bba | 731 | /* enable RTC functional clock */ |
2153f949 | 732 | if (rtc->type->has_32kclk_en) { |
55ba953a JH |
733 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); |
734 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | |
735 | reg | OMAP_RTC_OSC_32KCLK_EN); | |
44c63a57 | 736 | } |
cd914bba | 737 | |
db68b189 | 738 | /* clear old status */ |
55ba953a | 739 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
9291e340 JH |
740 | |
741 | mask = OMAP_RTC_STATUS_ALARM; | |
742 | ||
222a12fc JH |
743 | if (rtc->type->has_pmic_mode) |
744 | mask |= OMAP_RTC_STATUS_ALARM2; | |
745 | ||
9291e340 JH |
746 | if (rtc->type->has_power_up_reset) { |
747 | mask |= OMAP_RTC_STATUS_POWER_UP; | |
748 | if (reg & OMAP_RTC_STATUS_POWER_UP) | |
749 | dev_info(&pdev->dev, "RTC power up reset detected\n"); | |
db68b189 | 750 | } |
9291e340 JH |
751 | |
752 | if (reg & mask) | |
753 | rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); | |
db68b189 | 754 | |
db68b189 | 755 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
55ba953a | 756 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
10211ae3 | 757 | if (reg & OMAP_RTC_CTRL_STOP) |
397b630a | 758 | dev_info(&pdev->dev, "already running\n"); |
db68b189 DB |
759 | |
760 | /* force to 24 hour mode */ | |
10211ae3 | 761 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); |
db68b189 DB |
762 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
763 | ||
10211ae3 JH |
764 | /* |
765 | * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | |
db68b189 | 766 | * |
fa5b0782 SN |
767 | * - Device wake-up capability setting should come through chip |
768 | * init logic. OMAP1 boards should initialize the "wakeup capable" | |
769 | * flag in the platform device if the board is wired right for | |
770 | * being woken up by RTC alarm. For OMAP-L138, this capability | |
771 | * is built into the SoC by the "Deep Sleep" capability. | |
db68b189 DB |
772 | * |
773 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, | |
774 | * rather than nPWRON_RESET, should forcibly enable split | |
775 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT | |
776 | * is write-only, and always reads as zero...) | |
777 | */ | |
db68b189 | 778 | |
10211ae3 | 779 | if (new_ctrl & OMAP_RTC_CTRL_SPLIT) |
397b630a | 780 | dev_info(&pdev->dev, "split power mode\n"); |
db68b189 DB |
781 | |
782 | if (reg != new_ctrl) | |
55ba953a | 783 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); |
db68b189 | 784 | |
399cf0f6 K |
785 | /* |
786 | * If we have the external clock then switch to it so we can keep | |
787 | * ticking across suspend. | |
788 | */ | |
789 | if (rtc->has_ext_clk) { | |
790 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); | |
3984903a LV |
791 | reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE; |
792 | reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC; | |
793 | rtc_writel(rtc, OMAP_RTC_OSC_REG, reg); | |
399cf0f6 K |
794 | } |
795 | ||
9c28bd07 LV |
796 | rtc->type->lock(rtc); |
797 | ||
4390ce00 JH |
798 | device_init_wakeup(&pdev->dev, true); |
799 | ||
55ba953a | 800 | rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
4390ce00 | 801 | &omap_rtc_ops, THIS_MODULE); |
55ba953a JH |
802 | if (IS_ERR(rtc->rtc)) { |
803 | ret = PTR_ERR(rtc->rtc); | |
4390ce00 JH |
804 | goto err; |
805 | } | |
4390ce00 JH |
806 | |
807 | /* handle periodic and alarm irqs */ | |
55ba953a JH |
808 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
809 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
810 | if (ret) |
811 | goto err; | |
812 | ||
55ba953a JH |
813 | if (rtc->irq_timer != rtc->irq_alarm) { |
814 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | |
815 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
816 | if (ret) |
817 | goto err; | |
818 | } | |
819 | ||
222a12fc JH |
820 | if (rtc->is_pmic_controller) { |
821 | if (!pm_power_off) { | |
822 | omap_rtc_power_off_rtc = rtc; | |
823 | pm_power_off = omap_rtc_power_off; | |
824 | } | |
825 | } | |
826 | ||
97ea1906 MN |
827 | /* Support ext_wakeup pinconf */ |
828 | rtc_pinctrl_desc.name = dev_name(&pdev->dev); | |
829 | ||
830 | rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc); | |
831 | if (IS_ERR(rtc->pctldev)) { | |
832 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
833 | return PTR_ERR(rtc->pctldev); | |
834 | } | |
835 | ||
db68b189 DB |
836 | return 0; |
837 | ||
437b37a6 | 838 | err: |
7ecd9a3f | 839 | device_init_wakeup(&pdev->dev, false); |
9c28bd07 | 840 | rtc->type->lock(rtc); |
fc9bd902 VH |
841 | pm_runtime_put_sync(&pdev->dev); |
842 | pm_runtime_disable(&pdev->dev); | |
437b37a6 JH |
843 | |
844 | return ret; | |
db68b189 DB |
845 | } |
846 | ||
b9de1a1d | 847 | static int omap_rtc_remove(struct platform_device *pdev) |
db68b189 | 848 | { |
55ba953a | 849 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
399cf0f6 | 850 | u8 reg; |
db68b189 | 851 | |
222a12fc JH |
852 | if (pm_power_off == omap_rtc_power_off && |
853 | omap_rtc_power_off_rtc == rtc) { | |
854 | pm_power_off = NULL; | |
855 | omap_rtc_power_off_rtc = NULL; | |
856 | } | |
857 | ||
db68b189 DB |
858 | device_init_wakeup(&pdev->dev, 0); |
859 | ||
532409aa K |
860 | if (!IS_ERR(rtc->clk)) |
861 | clk_disable_unprepare(rtc->clk); | |
862 | ||
9c28bd07 | 863 | rtc->type->unlock(rtc); |
db68b189 | 864 | /* leave rtc running, but disable irqs */ |
55ba953a | 865 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 866 | |
399cf0f6 K |
867 | if (rtc->has_ext_clk) { |
868 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); | |
869 | reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC; | |
870 | rtc_write(rtc, OMAP_RTC_OSC_REG, reg); | |
871 | } | |
872 | ||
9c28bd07 | 873 | rtc->type->lock(rtc); |
fc9bd902 VH |
874 | |
875 | /* Disable the clock/module */ | |
876 | pm_runtime_put_sync(&pdev->dev); | |
877 | pm_runtime_disable(&pdev->dev); | |
878 | ||
97ea1906 MN |
879 | /* Remove ext_wakeup pinconf */ |
880 | pinctrl_unregister(rtc->pctldev); | |
881 | ||
db68b189 DB |
882 | return 0; |
883 | } | |
884 | ||
0c749eac | 885 | static int __maybe_unused omap_rtc_suspend(struct device *dev) |
db68b189 | 886 | { |
55ba953a JH |
887 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
888 | ||
889 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
db68b189 | 890 | |
9c28bd07 | 891 | rtc->type->unlock(rtc); |
10211ae3 JH |
892 | /* |
893 | * FIXME: the RTC alarm is not currently acting as a wakeup event | |
8af750e3 HG |
894 | * source on some platforms, and in fact this enable() call is just |
895 | * saving a flag that's never used... | |
db68b189 | 896 | */ |
ab7f580b | 897 | if (device_may_wakeup(dev)) |
55ba953a | 898 | enable_irq_wake(rtc->irq_alarm); |
ab7f580b | 899 | else |
55ba953a | 900 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
9c28bd07 | 901 | rtc->type->lock(rtc); |
db68b189 | 902 | |
efce21fc | 903 | rtc->is_suspending = true; |
fc9bd902 | 904 | |
db68b189 DB |
905 | return 0; |
906 | } | |
907 | ||
0c749eac | 908 | static int __maybe_unused omap_rtc_resume(struct device *dev) |
db68b189 | 909 | { |
55ba953a JH |
910 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
911 | ||
9c28bd07 | 912 | rtc->type->unlock(rtc); |
ab7f580b | 913 | if (device_may_wakeup(dev)) |
55ba953a | 914 | disable_irq_wake(rtc->irq_alarm); |
ab7f580b | 915 | else |
55ba953a | 916 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
9c28bd07 | 917 | rtc->type->lock(rtc); |
ab7f580b | 918 | |
efce21fc TK |
919 | rtc->is_suspending = false; |
920 | ||
db68b189 DB |
921 | return 0; |
922 | } | |
db68b189 | 923 | |
0c749eac | 924 | static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev) |
efce21fc TK |
925 | { |
926 | struct omap_rtc *rtc = dev_get_drvdata(dev); | |
927 | ||
928 | if (rtc->is_suspending && !rtc->has_ext_clk) | |
929 | return -EBUSY; | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
efce21fc TK |
934 | static const struct dev_pm_ops omap_rtc_pm_ops = { |
935 | SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume) | |
0c749eac | 936 | SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL) |
efce21fc | 937 | }; |
04ebc359 | 938 | |
db68b189 DB |
939 | static void omap_rtc_shutdown(struct platform_device *pdev) |
940 | { | |
55ba953a | 941 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
8ad5c722 | 942 | u8 mask; |
55ba953a | 943 | |
8ad5c722 JH |
944 | /* |
945 | * Keep the ALARM interrupt enabled to allow the system to power up on | |
946 | * alarm events. | |
947 | */ | |
9c28bd07 | 948 | rtc->type->unlock(rtc); |
8ad5c722 JH |
949 | mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
950 | mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; | |
951 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); | |
9c28bd07 | 952 | rtc->type->lock(rtc); |
db68b189 DB |
953 | } |
954 | ||
db68b189 | 955 | static struct platform_driver omap_rtc_driver = { |
5d9094b6 | 956 | .probe = omap_rtc_probe, |
b9de1a1d | 957 | .remove = omap_rtc_remove, |
db68b189 DB |
958 | .shutdown = omap_rtc_shutdown, |
959 | .driver = { | |
a430ca22 | 960 | .name = "omap_rtc", |
04ebc359 | 961 | .pm = &omap_rtc_pm_ops, |
616b7341 | 962 | .of_match_table = omap_rtc_of_match, |
db68b189 | 963 | }, |
2153f949 | 964 | .id_table = omap_rtc_id_table, |
db68b189 DB |
965 | }; |
966 | ||
5d9094b6 | 967 | module_platform_driver(omap_rtc_driver); |
db68b189 | 968 | |
a430ca22 | 969 | MODULE_ALIAS("platform:omap_rtc"); |
db68b189 DB |
970 | MODULE_AUTHOR("George G. Davis (and others)"); |
971 | MODULE_LICENSE("GPL"); |