[linux-block.git] / drivers / rtc / rtc-mxc_v2.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Real Time Clock (RTC) Driver for i.MX53
 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
 * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/rtc.h>

#define SRTC_LPPDR_INIT       0x41736166	/* init for glitch detect */

#define SRTC_LPCR_EN_LP       BIT(3)	/* lp enable */
#define SRTC_LPCR_WAE         BIT(4)	/* lp wakeup alarm enable */
#define SRTC_LPCR_ALP         BIT(7)	/* lp alarm flag */
#define SRTC_LPCR_NSA         BIT(11)	/* lp non secure access */
#define SRTC_LPCR_NVE         BIT(14)	/* lp non valid state exit bit */
#define SRTC_LPCR_IE          BIT(15)	/* lp init state exit bit */

#define SRTC_LPSR_ALP         BIT(3)	/* lp alarm flag */
#define SRTC_LPSR_NVES        BIT(14)	/* lp non-valid state exit status */
#define SRTC_LPSR_IES         BIT(15)	/* lp init state exit status */

#define SRTC_LPSCMR	0x00	/* LP Secure Counter MSB Reg */
#define SRTC_LPSCLR	0x04	/* LP Secure Counter LSB Reg */
#define SRTC_LPSAR	0x08	/* LP Secure Alarm Reg */
#define SRTC_LPCR	0x10	/* LP Control Reg */
#define SRTC_LPSR	0x14	/* LP Status Reg */
#define SRTC_LPPDR	0x18	/* LP Power Supply Glitch Detector Reg */

/* max. number of retries to read registers, 120 was max during test */
#define REG_READ_TIMEOUT 2000

struct mxc_rtc_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	struct clk *clk;
	spinlock_t lock; /* protects register access */
	int irq;
};

/*
 * This function does write synchronization for writes to the lp srtc block.
 * To take care of the asynchronous CKIL clock, all writes from the IP domain
 * will be synchronized to the CKIL domain.
 * The caller should hold the pdata->lock
 */
static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
{
	unsigned int i;

	/* Wait for 3 CKIL cycles */
	for (i = 0; i < 3; i++) {
		const u32 count = readl(ioaddr + SRTC_LPSCLR);
		unsigned int timeout = REG_READ_TIMEOUT;

		while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
			if (!--timeout) {
				dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
				return;
			}
		}
	}
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct device *dev = dev_id;
	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 lp_status;
	u32 lp_cr;

	spin_lock_irqsave(&pdata->lock, flags);
	if (clk_enable(pdata->clk)) {
		spin_unlock_irqrestore(&pdata->lock, flags);
		return IRQ_NONE;
	}

	lp_status = readl(ioaddr + SRTC_LPSR);
	lp_cr = readl(ioaddr + SRTC_LPCR);

	/* update irq data & counter */
	if (lp_status & SRTC_LPSR_ALP) {
		if (lp_cr & SRTC_LPCR_ALP)
			rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);

		/* disable further lp alarm interrupts */
		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
	}

	/* Update interrupt enables */
	writel(lp_cr, ioaddr + SRTC_LPCR);

	/* clear interrupt status */
	writel(lp_status, ioaddr + SRTC_LPSR);

	mxc_rtc_sync_lp_locked(dev, ioaddr);
	clk_disable(pdata->clk);
	spin_unlock_irqrestore(&pdata->lock, flags);
	return IRQ_HANDLED;
}

/*
 * Enable clk and aquire spinlock
 * @return  0 if successful; non-zero otherwise.
 */
static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
{
	int ret;

	spin_lock_irq(&pdata->lock);
	ret = clk_enable(pdata->clk);
	if (ret) {
		spin_unlock_irq(&pdata->lock);
		return ret;
	}
	return 0;
}

static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
{
	clk_disable(pdata->clk);
	spin_unlock_irq(&pdata->lock);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 *
 * @param  tm           contains the RTC time value upon return
 *
 * @return  0 if successful; non-zero otherwise.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	const int clk_failed = clk_enable(pdata->clk);

	if (!clk_failed) {
		const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);

		rtc_time64_to_tm(now, tm);
		clk_disable(pdata->clk);
		return 0;
	}
	return clk_failed;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 *
 * @param  tm           the time value to be set in the RTC
 *
 * @return  0 if successful; non-zero otherwise.
 */
static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	time64_t time = rtc_tm_to_time64(tm);
	int ret;

	ret = mxc_rtc_lock(pdata);
	if (ret)
		return ret;

	writel(time, pdata->ioaddr + SRTC_LPSCMR);
	mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
	return mxc_rtc_unlock(pdata);
}

/*
 * This function reads the current alarm value into the passed in \b alrm
 * argument. It updates the \b alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 *
 * @param  alrm         contains the RTC alarm value upon return
 *
 * @return  0 if successful; non-zero otherwise.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	int ret;

	ret = mxc_rtc_lock(pdata);
	if (ret)
		return ret;

	rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
	alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
	return mxc_rtc_unlock(pdata);
}

/*
 * Enable/Disable alarm interrupt
 * The caller should hold the pdata->lock
 */
static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
					    unsigned int enable)
{
	u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);

	if (enable)
		lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
	else
		lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);

	writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	int ret = mxc_rtc_lock(pdata);

	if (ret)
		return ret;

	mxc_rtc_alarm_irq_enable_locked(pdata, enable);
	return mxc_rtc_unlock(pdata);
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 *
 * @param  alrm         the alarm value to be set in the RTC
 *
 * @return  0 if successful; non-zero otherwise.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	const time64_t time = rtc_tm_to_time64(&alrm->time);
	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	int ret = mxc_rtc_lock(pdata);

	if (ret)
		return ret;

	writel((u32)time, pdata->ioaddr + SRTC_LPSAR);

	/* clear alarm interrupt status bit */
	writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
	mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);

	mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
	mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
	mxc_rtc_unlock(pdata);
	return ret;
}

static const struct rtc_class_ops mxc_rtc_ops = {
	.read_time = mxc_rtc_read_time,
	.set_time = mxc_rtc_set_time,
	.read_alarm = mxc_rtc_read_alarm,
	.set_alarm = mxc_rtc_set_alarm,
	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
};

static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
{
	unsigned int timeout = REG_READ_TIMEOUT;

	while (!(readl(ioaddr) & flag)) {
		if (!--timeout)
			return -EBUSY;
	}
	return 0;
}

static int mxc_rtc_probe(struct platform_device *pdev)
{
	struct mxc_rtc_data *pdata;
	struct resource *res;
	void __iomem *ioaddr;
	int ret = 0;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pdata->ioaddr))
		return PTR_ERR(pdata->ioaddr);

	ioaddr = pdata->ioaddr;

	pdata->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pdata->clk)) {
		dev_err(&pdev->dev, "unable to get rtc clock!\n");
		return PTR_ERR(pdata->clk);
	}

	spin_lock_init(&pdata->lock);
	pdata->irq = platform_get_irq(pdev, 0);
	if (pdata->irq < 0)
		return pdata->irq;

	device_init_wakeup(&pdev->dev, 1);
	ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
	if (ret)
		dev_err(&pdev->dev, "failed to enable irq wake\n");

	ret = clk_prepare_enable(pdata->clk);
	if (ret)
		return ret;
	/* initialize glitch detect */
	writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);

	/* clear lp interrupt status */
	writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);

	/* move out of init state */
	writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
	ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
	if (ret) {
		dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
		clk_disable_unprepare(pdata->clk);
		return ret;
	}

	/* move out of non-valid state */
	writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
		SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
	ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
	if (ret) {
		dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
		clk_disable_unprepare(pdata->clk);
		return ret;
	}

	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(pdata->rtc))
		return PTR_ERR(pdata->rtc);

	pdata->rtc->ops = &mxc_rtc_ops;
	pdata->rtc->range_max = U32_MAX;

	clk_disable(pdata->clk);
	platform_set_drvdata(pdev, pdata);
	ret =
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
			     pdev->name, &pdev->dev);
	if (ret < 0) {
		dev_err(&pdev->dev, "interrupt not available.\n");
		clk_unprepare(pdata->clk);
		return ret;
	}

	ret = rtc_register_device(pdata->rtc);
	if (ret < 0)
		clk_unprepare(pdata->clk);

	return ret;
}

static int mxc_rtc_remove(struct platform_device *pdev)
{
	struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);

	clk_disable_unprepare(pdata->clk);
	return 0;
}

static const struct of_device_id mxc_ids[] = {
	{ .compatible = "fsl,imx53-rtc", },
	{}
};

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		.name = "mxc_rtc_v2",
		.of_match_table = mxc_ids,
	},
	.probe = mxc_rtc_probe,
	.remove = mxc_rtc_remove,
};

module_platform_driver(mxc_rtc_driver);

MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
MODULE_LICENSE("GPL");
Commit	Line	Data
83c880f7 PB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Real Time Clock (RTC) Driver for i.MX53
	4	* Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
	5	* Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/io.h>
	10	#include <linux/module.h>
ac316725	11	#include <linux/mod_devicetable.h>
83c880f7	12	#include <linux/platform_device.h>
fbc5ee9a	13	#include <linux/pm_wakeirq.h>
83c880f7 PB	14	#include <linux/rtc.h>
	15
	16	#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
	17
	18	#define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
	19	#define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
	20	#define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
	21	#define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
	22	#define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
	23	#define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
	24
	25	#define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
	26	#define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
	27	#define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
	28
	29	#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
	30	#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
	31	#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
	32	#define SRTC_LPCR 0x10 /* LP Control Reg */
	33	#define SRTC_LPSR 0x14 /* LP Status Reg */
	34	#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
	35
	36	/* max. number of retries to read registers, 120 was max during test */
	37	#define REG_READ_TIMEOUT 2000
	38
	39	struct mxc_rtc_data {
	40	struct rtc_device *rtc;
	41	void __iomem *ioaddr;
	42	struct clk *clk;
	43	spinlock_t lock; /* protects register access */
	44	int irq;
	45	};
	46
	47	/*
	48	* This function does write synchronization for writes to the lp srtc block.
	49	* To take care of the asynchronous CKIL clock, all writes from the IP domain
	50	* will be synchronized to the CKIL domain.
	51	* The caller should hold the pdata->lock
	52	*/
	53	static void mxc_rtc_sync_lp_locked(struct device dev, void __iomem ioaddr)
	54	{
	55	unsigned int i;
	56
	57	/* Wait for 3 CKIL cycles */
	58	for (i = 0; i < 3; i++) {
	59	const u32 count = readl(ioaddr + SRTC_LPSCLR);
	60	unsigned int timeout = REG_READ_TIMEOUT;
	61
	62	while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
	63	if (!--timeout) {
	64	dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
	65	return;
	66	}
	67	}
	68	}
	69	}
	70
	71	/* This function is the RTC interrupt service routine. */
	72	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	73	{
	74	struct device *dev = dev_id;
	75	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	76	void __iomem *ioaddr = pdata->ioaddr;
	77	unsigned long flags;
78	u32 lp_status;
79	u32 lp_cr;
80
81	spin_lock_irqsave(&pdata->lock, flags);
82	if (clk_enable(pdata->clk)) {
83	spin_unlock_irqrestore(&pdata->lock, flags);
84	return IRQ_NONE;
85	}
86
87	lp_status = readl(ioaddr + SRTC_LPSR);
88	lp_cr = readl(ioaddr + SRTC_LPCR);
89
90	/* update irq data & counter */
91	if (lp_status & SRTC_LPSR_ALP) {
92	if (lp_cr & SRTC_LPCR_ALP)
93	rtc_update_irq(pdata->rtc, 1, RTC_AF \| RTC_IRQF);
94
95	/* disable further lp alarm interrupts */
96	lp_cr &= ~(SRTC_LPCR_ALP \| SRTC_LPCR_WAE);
97	}
98
99	/* Update interrupt enables */
100	writel(lp_cr, ioaddr + SRTC_LPCR);
101
102	/* clear interrupt status */
103	writel(lp_status, ioaddr + SRTC_LPSR);
104
105	mxc_rtc_sync_lp_locked(dev, ioaddr);
106	clk_disable(pdata->clk);
107	spin_unlock_irqrestore(&pdata->lock, flags);
108	return IRQ_HANDLED;
109	}
110
111	/*
112	* Enable clk and aquire spinlock
113	* @return 0 if successful; non-zero otherwise.
114	*/
115	static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
116	{
117	int ret;
118
119	spin_lock_irq(&pdata->lock);
120	ret = clk_enable(pdata->clk);
121	if (ret) {
122	spin_unlock_irq(&pdata->lock);
123	return ret;
124	}
125	return 0;
126	}
127
128	static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
129	{
130	clk_disable(pdata->clk);
131	spin_unlock_irq(&pdata->lock);
132	return 0;
133	}
134
135	/*
136	* This function reads the current RTC time into tm in Gregorian date.
137	*
138	* @param tm contains the RTC time value upon return
139	*
140	* @return 0 if successful; non-zero otherwise.
141	*/
142	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
143	{
144	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
145	const int clk_failed = clk_enable(pdata->clk);
146
147	if (!clk_failed) {
148	const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
149
150	rtc_time64_to_tm(now, tm);
151	clk_disable(pdata->clk);
152	return 0;
153	}
154	return clk_failed;
155	}
156
157	/*
158	* This function sets the internal RTC time based on tm in Gregorian date.
159	*
160	* @param tm the time value to be set in the RTC
161	*
162	* @return 0 if successful; non-zero otherwise.
163	*/
164	static int mxc_rtc_set_time(struct device dev, struct rtc_time tm)
165	{
166	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
167	time64_t time = rtc_tm_to_time64(tm);
168	int ret;
169
83c880f7 PB	170	ret = mxc_rtc_lock(pdata);
	171	if (ret)
	172	return ret;
	173
	174	writel(time, pdata->ioaddr + SRTC_LPSCMR);
	175	mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
	176	return mxc_rtc_unlock(pdata);
	177	}
	178
	179	/*
	180	* This function reads the current alarm value into the passed in \b alrm
	181	* argument. It updates the \b alrm's pending field value based on the whether
	182	* an alarm interrupt occurs or not.
	183	*
	184	* @param alrm contains the RTC alarm value upon return
	185	*
	186	* @return 0 if successful; non-zero otherwise.
	187	*/
	188	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	189	{
	190	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	191	void __iomem *ioaddr = pdata->ioaddr;
	192	int ret;
	193
	194	ret = mxc_rtc_lock(pdata);
	195	if (ret)
	196	return ret;
	197
7e83f03f	198	rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
83c880f7 PB	199	alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
	200	return mxc_rtc_unlock(pdata);
	201	}
	202
	203	/*
	204	* Enable/Disable alarm interrupt
	205	* The caller should hold the pdata->lock
	206	*/
	207	static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
	208	unsigned int enable)
	209	{
	210	u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
	211
	212	if (enable)
	213	lp_cr \|= (SRTC_LPCR_ALP \| SRTC_LPCR_WAE);
	214	else
	215	lp_cr &= ~(SRTC_LPCR_ALP \| SRTC_LPCR_WAE);
	216
	217	writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
	218	}
	219
	220	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	221	{
	222	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	223	int ret = mxc_rtc_lock(pdata);
	224
	225	if (ret)
	226	return ret;
	227
	228	mxc_rtc_alarm_irq_enable_locked(pdata, enable);
	229	return mxc_rtc_unlock(pdata);
	230	}
	231
	232	/*
	233	* This function sets the RTC alarm based on passed in alrm.
	234	*
	235	* @param alrm the alarm value to be set in the RTC
	236	*
	237	* @return 0 if successful; non-zero otherwise.
	238	*/
	239	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	240	{
	241	const time64_t time = rtc_tm_to_time64(&alrm->time);
	242	struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
	243	int ret = mxc_rtc_lock(pdata);
	244
	245	if (ret)
	246	return ret;
	247
83c880f7 PB	248	writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
	249
	250	/* clear alarm interrupt status bit */
	251	writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
	252	mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
	253
	254	mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
	255	mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
	256	mxc_rtc_unlock(pdata);
	257	return ret;
	258	}
	259
	260	static const struct rtc_class_ops mxc_rtc_ops = {
	261	.read_time = mxc_rtc_read_time,
	262	.set_time = mxc_rtc_set_time,
	263	.read_alarm = mxc_rtc_read_alarm,
	264	.set_alarm = mxc_rtc_set_alarm,
	265	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
	266	};
	267
588519ff	268	static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
83c880f7 PB	269	{
	270	unsigned int timeout = REG_READ_TIMEOUT;
	271
	272	while (!(readl(ioaddr) & flag)) {
	273	if (!--timeout)
	274	return -EBUSY;
	275	}
	276	return 0;
	277	}
	278
	279	static int mxc_rtc_probe(struct platform_device *pdev)
	280	{
	281	struct mxc_rtc_data *pdata;
	282	struct resource *res;
	283	void __iomem *ioaddr;
	284	int ret = 0;
	285
	286	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	287	if (!pdata)
	288	return -ENOMEM;
	289
	290	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
83c880f7 PB	291	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	292	if (IS_ERR(pdata->ioaddr))
	293	return PTR_ERR(pdata->ioaddr);
	294
	295	ioaddr = pdata->ioaddr;
	296
	297	pdata->clk = devm_clk_get(&pdev->dev, NULL);
	298	if (IS_ERR(pdata->clk)) {
	299	dev_err(&pdev->dev, "unable to get rtc clock!\n");
	300	return PTR_ERR(pdata->clk);
	301	}
	302
	303	spin_lock_init(&pdata->lock);
	304	pdata->irq = platform_get_irq(pdev, 0);
	305	if (pdata->irq < 0)
	306	return pdata->irq;
	307
	308	device_init_wakeup(&pdev->dev, 1);
fbc5ee9a AH	309	ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
	310	if (ret)
	311	dev_err(&pdev->dev, "failed to enable irq wake\n");
83c880f7 PB	312
	313	ret = clk_prepare_enable(pdata->clk);
	314	if (ret)
	315	return ret;
	316	/* initialize glitch detect */
	317	writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
	318
	319	/* clear lp interrupt status */
	320	writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
	321
	322	/* move out of init state */
	323	writel((SRTC_LPCR_IE \| SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
	324	ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
	325	if (ret) {
	326	dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
	327	clk_disable_unprepare(pdata->clk);
	328	return ret;
	329	}
	330
	331	/* move out of non-valid state */
	332	writel((SRTC_LPCR_IE \| SRTC_LPCR_NVE \| SRTC_LPCR_NSA \|
	333	SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
	334	ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
	335	if (ret) {
	336	dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
	337	clk_disable_unprepare(pdata->clk);
	338	return ret;
	339	}
	340
5490a1e0 AB	341	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
	342	if (IS_ERR(pdata->rtc))
	343	return PTR_ERR(pdata->rtc);
	344
	345	pdata->rtc->ops = &mxc_rtc_ops;
95fbfa14	346	pdata->rtc->range_max = U32_MAX;
5490a1e0	347
83c880f7 PB	348	clk_disable(pdata->clk);
	349	platform_set_drvdata(pdev, pdata);
	350	ret =
	351	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
	352	pdev->name, &pdev->dev);
	353	if (ret < 0) {
	354	dev_err(&pdev->dev, "interrupt not available.\n");
	355	clk_unprepare(pdata->clk);
	356	return ret;
	357	}
	358
5490a1e0 AB	359	ret = rtc_register_device(pdata->rtc);
5490a1e0 AB	360	if (ret < 0)
83c880f7	361	clk_unprepare(pdata->clk);
83c880f7	362
5490a1e0	363	return ret;
83c880f7 PB	364	}
83c880f7 PB	365
db00d38e	366	static int mxc_rtc_remove(struct platform_device *pdev)
83c880f7 PB	367	{
	368	struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
	369
	370	clk_disable_unprepare(pdata->clk);
	371	return 0;
	372	}
	373
83c880f7 PB	374	static const struct of_device_id mxc_ids[] = {
	375	{ .compatible = "fsl,imx53-rtc", },
	376	{}
	377	};
	378
	379	static struct platform_driver mxc_rtc_driver = {
	380	.driver = {
	381	.name = "mxc_rtc_v2",
	382	.of_match_table = mxc_ids,
83c880f7 PB	383	},
	384	.probe = mxc_rtc_probe,
	385	.remove = mxc_rtc_remove,
	386	};
	387
	388	module_platform_driver(mxc_rtc_driver);
	389
	390	MODULE_AUTHOR("Freescale Semiconductor, Inc.");
	391	MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
	392	MODULE_LICENSE("GPL");