[linux-block.git] / drivers / rtc / rtc-mxc.c

/*
 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>

#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)

#define RTC_SW_BIT      (1 << 0)
#define RTC_ALM_BIT     (1 << 2)
#define RTC_1HZ_BIT     (1 << 4)
#define RTC_2HZ_BIT     (1 << 7)
#define RTC_SAM0_BIT    (1 << 8)
#define RTC_SAM1_BIT    (1 << 9)
#define RTC_SAM2_BIT    (1 << 10)
#define RTC_SAM3_BIT    (1 << 11)
#define RTC_SAM4_BIT    (1 << 12)
#define RTC_SAM5_BIT    (1 << 13)
#define RTC_SAM6_BIT    (1 << 14)
#define RTC_SAM7_BIT    (1 << 15)
#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
			 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
			 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)

#define RTC_ENABLE_BIT  (1 << 7)

#define MAX_PIE_NUM     9
#define MAX_PIE_FREQ    512

#define MXC_RTC_TIME	0
#define MXC_RTC_ALARM	1

#define RTC_HOURMIN	0x00	/*  32bit rtc hour/min counter reg */
#define RTC_SECOND	0x04	/*  32bit rtc seconds counter reg */
#define RTC_ALRM_HM	0x08	/*  32bit rtc alarm hour/min reg */
#define RTC_ALRM_SEC	0x0C	/*  32bit rtc alarm seconds reg */
#define RTC_RTCCTL	0x10	/*  32bit rtc control reg */
#define RTC_RTCISR	0x14	/*  32bit rtc interrupt status reg */
#define RTC_RTCIENR	0x18	/*  32bit rtc interrupt enable reg */
#define RTC_STPWCH	0x1C	/*  32bit rtc stopwatch min reg */
#define RTC_DAYR	0x20	/*  32bit rtc days counter reg */
#define RTC_DAYALARM	0x24	/*  32bit rtc day alarm reg */
#define RTC_TEST1	0x28	/*  32bit rtc test reg 1 */
#define RTC_TEST2	0x2C	/*  32bit rtc test reg 2 */
#define RTC_TEST3	0x30	/*  32bit rtc test reg 3 */

enum imx_rtc_type {
	IMX1_RTC,
	IMX21_RTC,
};

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk_ref;
	struct clk *clk_ipg;
	struct rtc_time g_rtc_alarm;
	enum imx_rtc_type devtype;
};

static const struct platform_device_id imx_rtc_devtype[] = {
	{
		.name = "imx1-rtc",
		.driver_data = IMX1_RTC,
	}, {
		.name = "imx21-rtc",
		.driver_data = IMX21_RTC,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);

#ifdef CONFIG_OF
static const struct of_device_id imx_rtc_dt_ids[] = {
	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	{}
};
MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
#endif

static inline int is_imx1_rtc(struct rtc_plat_data *data)
{
	return data->devtype == IMX1_RTC;
}

/*
 * This function is used to obtain the RTC time or the alarm value in
 * second.
 */
static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		day = readw(ioaddr + RTC_DAYR);
		hr_min = readw(ioaddr + RTC_HOURMIN);
		sec = readw(ioaddr + RTC_SECOND);
		break;
	case MXC_RTC_ALARM:
		day = readw(ioaddr + RTC_DAYALARM);
		hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
		sec = readw(ioaddr + RTC_ALRM_SEC);
		break;
	}

	hr = hr_min >> 8;
	min = hr_min & 0xff;

	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
}

/*
 * This function sets the RTC alarm value or the time value.
 */
static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
{
	u32 tod, day, hr, min, sec, temp;
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	day = div_s64_rem(time, 86400, &tod);

	/* time is within a day now */
	hr = tod / 3600;
	tod -= hr * 3600;

	/* time is within an hour now */
	min = tod / 60;
	sec = tod - min * 60;

	temp = (hr << 8) + min;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		writew(day, ioaddr + RTC_DAYR);
		writew(sec, ioaddr + RTC_SECOND);
		writew(temp, ioaddr + RTC_HOURMIN);
		break;
	case MXC_RTC_ALARM:
		writew(day, ioaddr + RTC_DAYALARM);
		writew(sec, ioaddr + RTC_ALRM_SEC);
		writew(temp, ioaddr + RTC_ALRM_HM);
		break;
	}
}

/*
 * This function updates the RTC alarm registers and then clears all the
 * interrupt status bits.
 */
static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
{
	time64_t time;
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	time = rtc_tm_to_time64(alrm);

	/* clear all the interrupt status bits */
	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
}

static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
				unsigned int enabled)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 reg;

	spin_lock_irq(&pdata->rtc->irq_lock);
	reg = readw(ioaddr + RTC_RTCIENR);

	if (enabled)
		reg |= bit;
	else
		reg &= ~bit;

	writew(reg, ioaddr + RTC_RTCIENR);
	spin_unlock_irq(&pdata->rtc->irq_lock);
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 status;
	u32 events = 0;

	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	/* clear interrupt sources */
	writew(status, ioaddr + RTC_RTCISR);

	/* update irq data & counter */
	if (status & RTC_ALM_BIT) {
		events |= (RTC_AF | RTC_IRQF);
		/* RTC alarm should be one-shot */
		mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	}

	if (status & PIT_ALL_ON)
		events |= (RTC_PF | RTC_IRQF);

	rtc_update_irq(pdata->rtc, 1, events);
	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);

	return IRQ_HANDLED;
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	time64_t val;

	/* Avoid roll-over from reading the different registers */
	do {
		val = get_alarm_or_time(dev, MXC_RTC_TIME);
	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));

	rtc_time64_to_tm(val, tm);

	return 0;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 */
static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	/*
	 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	 */
	if (is_imx1_rtc(pdata)) {
		struct rtc_time tm;

		rtc_time64_to_tm(time, &tm);
		tm.tm_year = 70;
		time = rtc_tm_to_time64(&tm);
	}

	/* Avoid roll-over from reading the different registers */
	do {
		set_alarm_or_time(dev, MXC_RTC_TIME, time);
	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));

	return 0;
}

/*
 * This function reads the current alarm value into the passed in 'alrm'
 * argument. It updates the alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;

	return 0;
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	rtc_update_alarm(dev, &alrm->time);

	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);

	return 0;
}

/* RTC layer */
static const struct rtc_class_ops mxc_rtc_ops = {
	.read_time		= mxc_rtc_read_time,
	.set_mmss64		= mxc_rtc_set_mmss,
	.read_alarm		= mxc_rtc_read_alarm,
	.set_alarm		= mxc_rtc_set_alarm,
	.alarm_irq_enable	= mxc_rtc_alarm_irq_enable,
};

static int mxc_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	struct rtc_plat_data *pdata = NULL;
	u32 reg;
	unsigned long rate;
	int ret;
	const struct of_device_id *of_id;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	if (of_id)
		pdata->devtype = (enum imx_rtc_type)of_id->data;
	else
		pdata->devtype = pdev->id_entry->driver_data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pdata->ioaddr))
		return PTR_ERR(pdata->ioaddr);

	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(pdata->clk_ipg)) {
		dev_err(&pdev->dev, "unable to get ipg clock!\n");
		return PTR_ERR(pdata->clk_ipg);
	}

	ret = clk_prepare_enable(pdata->clk_ipg);
	if (ret)
		return ret;

	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	if (IS_ERR(pdata->clk_ref)) {
		dev_err(&pdev->dev, "unable to get ref clock!\n");
		ret = PTR_ERR(pdata->clk_ref);
		goto exit_put_clk_ipg;
	}

	ret = clk_prepare_enable(pdata->clk_ref);
	if (ret)
		goto exit_put_clk_ipg;

	rate = clk_get_rate(pdata->clk_ref);

	if (rate == 32768)
		reg = RTC_INPUT_CLK_32768HZ;
	else if (rate == 32000)
		reg = RTC_INPUT_CLK_32000HZ;
	else if (rate == 38400)
		reg = RTC_INPUT_CLK_38400HZ;
	else {
		dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
		ret = -EINVAL;
		goto exit_put_clk_ref;
	}

	reg |= RTC_ENABLE_BIT;
	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
		dev_err(&pdev->dev, "hardware module can't be enabled!\n");
		ret = -EIO;
		goto exit_put_clk_ref;
	}

	platform_set_drvdata(pdev, pdata);

	/* Configure and enable the RTC */
	pdata->irq = platform_get_irq(pdev, 0);

	if (pdata->irq >= 0 &&
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
			     IRQF_SHARED, pdev->name, pdev) < 0) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		pdata->irq = -1;
	}

	if (pdata->irq >= 0)
		device_init_wakeup(&pdev->dev, 1);

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
				  THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		goto exit_put_clk_ref;
	}

	pdata->rtc = rtc;

	return 0;

exit_put_clk_ref:
	clk_disable_unprepare(pdata->clk_ref);
exit_put_clk_ipg:
	clk_disable_unprepare(pdata->clk_ipg);

	return ret;
}

static int mxc_rtc_remove(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	clk_disable_unprepare(pdata->clk_ref);
	clk_disable_unprepare(pdata->clk_ipg);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mxc_rtc_suspend(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pdata->irq);

	return 0;
}

static int mxc_rtc_resume(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pdata->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		   .name	= "mxc_rtc",
		   .of_match_table = of_match_ptr(imx_rtc_dt_ids),
		   .pm		= &mxc_rtc_pm_ops,
	},
	.id_table = imx_rtc_devtype,
	.probe = mxc_rtc_probe,
	.remove = mxc_rtc_remove,
};

module_platform_driver(mxc_rtc_driver)

MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("RTC driver for Freescale MXC");
MODULE_LICENSE("GPL");
Commit	Line	Data
d00ed3cf DM	1	/*
	2	* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/io.h>
	13	#include <linux/rtc.h>
	14	#include <linux/module.h>
5a0e3ad6	15	#include <linux/slab.h>
d00ed3cf DM	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk.h>
cec13c26 PR	19	#include <linux/of.h>
cec13c26 PR	20	#include <linux/of_device.h>
d00ed3cf	21
d00ed3cf DM	22	#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
	23	#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
	24	#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
	25
	26	#define RTC_SW_BIT (1 << 0)
	27	#define RTC_ALM_BIT (1 << 2)
	28	#define RTC_1HZ_BIT (1 << 4)
	29	#define RTC_2HZ_BIT (1 << 7)
	30	#define RTC_SAM0_BIT (1 << 8)
	31	#define RTC_SAM1_BIT (1 << 9)
	32	#define RTC_SAM2_BIT (1 << 10)
	33	#define RTC_SAM3_BIT (1 << 11)
	34	#define RTC_SAM4_BIT (1 << 12)
	35	#define RTC_SAM5_BIT (1 << 13)
	36	#define RTC_SAM6_BIT (1 << 14)
	37	#define RTC_SAM7_BIT (1 << 15)
	38	#define PIT_ALL_ON (RTC_2HZ_BIT \| RTC_SAM0_BIT \| RTC_SAM1_BIT \| \
	39	RTC_SAM2_BIT \| RTC_SAM3_BIT \| RTC_SAM4_BIT \| \
	40	RTC_SAM5_BIT \| RTC_SAM6_BIT \| RTC_SAM7_BIT)
	41
	42	#define RTC_ENABLE_BIT (1 << 7)
	43
	44	#define MAX_PIE_NUM 9
	45	#define MAX_PIE_FREQ 512
d00ed3cf	46
d00ed3cf DM	47	#define MXC_RTC_TIME 0
	48	#define MXC_RTC_ALARM 1
	49
	50	#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
	51	#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
	52	#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
	53	#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
	54	#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
	55	#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
	56	#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
	57	#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
	58	#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
	59	#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
	60	#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
	61	#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
	62	#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
	63
bb1d34a2 SG	64	enum imx_rtc_type {
	65	IMX1_RTC,
	66	IMX21_RTC,
	67	};
	68
d00ed3cf DM	69	struct rtc_plat_data {
	70	struct rtc_device *rtc;
	71	void __iomem *ioaddr;
	72	int irq;
8f5fe778 PR	73	struct clk *clk_ref;
8f5fe778 PR	74	struct clk *clk_ipg;
d00ed3cf	75	struct rtc_time g_rtc_alarm;
bb1d34a2	76	enum imx_rtc_type devtype;
d00ed3cf DM	77	};
d00ed3cf DM	78
cd6ba00a	79	static const struct platform_device_id imx_rtc_devtype[] = {
bb1d34a2 SG	80	{
	81	.name = "imx1-rtc",
	82	.driver_data = IMX1_RTC,
	83	}, {
	84	.name = "imx21-rtc",
	85	.driver_data = IMX21_RTC,
	86	}, {
	87	/* sentinel */
	88	}
	89	};
	90	MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
	91
cec13c26 PR	92	#ifdef CONFIG_OF
	93	static const struct of_device_id imx_rtc_dt_ids[] = {
	94	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	95	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	96	{}
	97	};
	98	MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
	99	#endif
	100
bb1d34a2 SG	101	static inline int is_imx1_rtc(struct rtc_plat_data *data)
	102	{
	103	return data->devtype == IMX1_RTC;
	104	}
	105
d00ed3cf DM	106	/*
	107	* This function is used to obtain the RTC time or the alarm value in
	108	* second.
	109	*/
a015b8aa	110	static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
d00ed3cf	111	{
85368bb9	112	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	113	void __iomem *ioaddr = pdata->ioaddr;
	114	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
	115
	116	switch (time_alarm) {
	117	case MXC_RTC_TIME:
	118	day = readw(ioaddr + RTC_DAYR);
	119	hr_min = readw(ioaddr + RTC_HOURMIN);
	120	sec = readw(ioaddr + RTC_SECOND);
	121	break;
	122	case MXC_RTC_ALARM:
	123	day = readw(ioaddr + RTC_DAYALARM);
	124	hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
	125	sec = readw(ioaddr + RTC_ALRM_SEC);
	126	break;
	127	}
	128
	129	hr = hr_min >> 8;
	130	min = hr_min & 0xff;
	131
a015b8aa	132	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
d00ed3cf DM	133	}
	134
	135	/*
	136	* This function sets the RTC alarm value or the time value.
	137	*/
a015b8aa	138	static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
d00ed3cf	139	{
a015b8aa	140	u32 tod, day, hr, min, sec, temp;
85368bb9	141	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	142	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	143
a015b8aa	144	day = div_s64_rem(time, 86400, &tod);
d00ed3cf DM	145
d00ed3cf DM	146	/* time is within a day now */
a015b8aa XP	147	hr = tod / 3600;
a015b8aa XP	148	tod -= hr * 3600;
d00ed3cf DM	149
d00ed3cf DM	150	/* time is within an hour now */
a015b8aa XP	151	min = tod / 60;
a015b8aa XP	152	sec = tod - min * 60;
d00ed3cf DM	153
	154	temp = (hr << 8) + min;
	155
	156	switch (time_alarm) {
	157	case MXC_RTC_TIME:
	158	writew(day, ioaddr + RTC_DAYR);
	159	writew(sec, ioaddr + RTC_SECOND);
	160	writew(temp, ioaddr + RTC_HOURMIN);
	161	break;
	162	case MXC_RTC_ALARM:
	163	writew(day, ioaddr + RTC_DAYALARM);
	164	writew(sec, ioaddr + RTC_ALRM_SEC);
	165	writew(temp, ioaddr + RTC_ALRM_HM);
	166	break;
	167	}
	168	}
	169
	170	/*
	171	* This function updates the RTC alarm registers and then clears all the
	172	* interrupt status bits.
	173	*/
482494a8	174	static void rtc_update_alarm(struct device dev, struct rtc_time alrm)
d00ed3cf	175	{
a015b8aa	176	time64_t time;
85368bb9	177	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	178	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	179
a015b8aa	180	time = rtc_tm_to_time64(alrm);
d00ed3cf	181
d00ed3cf DM	182	/* clear all the interrupt status bits */
	183	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	184	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
c92182ee YK	185	}
	186
	187	static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
	188	unsigned int enabled)
	189	{
85368bb9	190	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
c92182ee YK	191	void __iomem *ioaddr = pdata->ioaddr;
	192	u32 reg;
	193
	194	spin_lock_irq(&pdata->rtc->irq_lock);
	195	reg = readw(ioaddr + RTC_RTCIENR);
	196
	197	if (enabled)
	198	reg \|= bit;
	199	else
	200	reg &= ~bit;
	201
	202	writew(reg, ioaddr + RTC_RTCIENR);
	203	spin_unlock_irq(&pdata->rtc->irq_lock);
d00ed3cf DM	204	}
	205
	206	/* This function is the RTC interrupt service routine. */
	207	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	208	{
	209	struct platform_device *pdev = dev_id;
	210	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	211	void __iomem *ioaddr = pdata->ioaddr;
b59f6d1f	212	unsigned long flags;
d00ed3cf DM	213	u32 status;
	214	u32 events = 0;
	215
b59f6d1f	216	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	217	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	218	/* clear interrupt sources */
	219	writew(status, ioaddr + RTC_RTCISR);
	220
d00ed3cf	221	/* update irq data & counter */
c92182ee	222	if (status & RTC_ALM_BIT) {
d00ed3cf	223	events \|= (RTC_AF \| RTC_IRQF);
c92182ee YK	224	/* RTC alarm should be one-shot */
	225	mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	226	}
d00ed3cf	227
d00ed3cf DM	228	if (status & PIT_ALL_ON)
	229	events \|= (RTC_PF \| RTC_IRQF);
	230
d00ed3cf	231	rtc_update_irq(pdata->rtc, 1, events);
b59f6d1f	232	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	233
	234	return IRQ_HANDLED;
	235	}
	236
d00ed3cf DM	237	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	238	{
	239	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	240	return 0;
	241	}
	242
d00ed3cf DM	243	/*
	244	* This function reads the current RTC time into tm in Gregorian date.
	245	*/
	246	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
	247	{
a015b8aa	248	time64_t val;
d00ed3cf DM	249
	250	/* Avoid roll-over from reading the different registers */
	251	do {
	252	val = get_alarm_or_time(dev, MXC_RTC_TIME);
	253	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
	254
a015b8aa	255	rtc_time64_to_tm(val, tm);
d00ed3cf DM	256
	257	return 0;
	258	}
	259
	260	/*
	261	* This function sets the internal RTC time based on tm in Gregorian date.
	262	*/
933623c3	263	static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
d00ed3cf	264	{
85368bb9	265	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
bb1d34a2	266
7287be1d YK	267	/*
	268	* TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	269	*/
bb1d34a2	270	if (is_imx1_rtc(pdata)) {
7287be1d YK	271	struct rtc_time tm;
7287be1d YK	272
933623c3	273	rtc_time64_to_tm(time, &tm);
7287be1d	274	tm.tm_year = 70;
933623c3	275	time = rtc_tm_to_time64(&tm);
7287be1d YK	276	}
7287be1d YK	277
d00ed3cf DM	278	/* Avoid roll-over from reading the different registers */
	279	do {
	280	set_alarm_or_time(dev, MXC_RTC_TIME, time);
	281	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
	282
	283	return 0;
	284	}
	285
	286	/*
	287	* This function reads the current alarm value into the passed in 'alrm'
	288	* argument. It updates the alrm's pending field value based on the whether
	289	* an alarm interrupt occurs or not.
	290	*/
	291	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	292	{
85368bb9	293	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	294	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	295
a015b8aa	296	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
d00ed3cf DM	297	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
	298
	299	return 0;
	300	}
	301
	302	/*
	303	* This function sets the RTC alarm based on passed in alrm.
	304	*/
	305	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	306	{
85368bb9	307	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf	308
482494a8	309	rtc_update_alarm(dev, &alrm->time);
d00ed3cf DM	310
	311	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	312	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
	313
	314	return 0;
	315	}
	316
	317	/* RTC layer */
8bc57e7f	318	static const struct rtc_class_ops mxc_rtc_ops = {
d00ed3cf	319	.read_time = mxc_rtc_read_time,
933623c3	320	.set_mmss64 = mxc_rtc_set_mmss,
d00ed3cf DM	321	.read_alarm = mxc_rtc_read_alarm,
	322	.set_alarm = mxc_rtc_set_alarm,
	323	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
d00ed3cf DM	324	};
d00ed3cf DM	325
5a167f45	326	static int mxc_rtc_probe(struct platform_device *pdev)
d00ed3cf	327	{
d00ed3cf DM	328	struct resource *res;
	329	struct rtc_device *rtc;
	330	struct rtc_plat_data *pdata = NULL;
	331	u32 reg;
c783a29e VZ	332	unsigned long rate;
c783a29e VZ	333	int ret;
cec13c26	334	const struct of_device_id *of_id;
d00ed3cf	335
c783a29e	336	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
d00ed3cf DM	337	if (!pdata)
	338	return -ENOMEM;
	339
cec13c26 PR	340	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	341	if (of_id)
	342	pdata->devtype = (enum imx_rtc_type)of_id->data;
	343	else
	344	pdata->devtype = pdev->id_entry->driver_data;
bb1d34a2	345
7c1d69ee JL	346	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	347	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	348	if (IS_ERR(pdata->ioaddr))
	349	return PTR_ERR(pdata->ioaddr);
d00ed3cf	350
8f5fe778 PR	351	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	352	if (IS_ERR(pdata->clk_ipg)) {
	353	dev_err(&pdev->dev, "unable to get ipg clock!\n");
	354	return PTR_ERR(pdata->clk_ipg);
49908e73	355	}
d00ed3cf	356
8f5fe778	357	ret = clk_prepare_enable(pdata->clk_ipg);
1b3d2243 FE	358	if (ret)
	359	return ret;
	360
8f5fe778 PR	361	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	362	if (IS_ERR(pdata->clk_ref)) {
	363	dev_err(&pdev->dev, "unable to get ref clock!\n");
	364	ret = PTR_ERR(pdata->clk_ref);
	365	goto exit_put_clk_ipg;
	366	}
	367
	368	ret = clk_prepare_enable(pdata->clk_ref);
	369	if (ret)
	370	goto exit_put_clk_ipg;
	371
	372	rate = clk_get_rate(pdata->clk_ref);
d00ed3cf DM	373
	374	if (rate == 32768)
	375	reg = RTC_INPUT_CLK_32768HZ;
	376	else if (rate == 32000)
	377	reg = RTC_INPUT_CLK_32000HZ;
	378	else if (rate == 38400)
	379	reg = RTC_INPUT_CLK_38400HZ;
	380	else {
c783a29e	381	dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
d00ed3cf	382	ret = -EINVAL;
8f5fe778	383	goto exit_put_clk_ref;
d00ed3cf DM	384	}
	385
	386	reg \|= RTC_ENABLE_BIT;
	387	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	388	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
	389	dev_err(&pdev->dev, "hardware module can't be enabled!\n");
	390	ret = -EIO;
8f5fe778	391	goto exit_put_clk_ref;
d00ed3cf DM	392	}
d00ed3cf DM	393
d00ed3cf DM	394	platform_set_drvdata(pdev, pdata);
	395
	396	/* Configure and enable the RTC */
	397	pdata->irq = platform_get_irq(pdev, 0);
	398
	399	if (pdata->irq >= 0 &&
c783a29e VZ	400	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
c783a29e VZ	401	IRQF_SHARED, pdev->name, pdev) < 0) {
d00ed3cf DM	402	dev_warn(&pdev->dev, "interrupt not available.\n");
	403	pdata->irq = -1;
	404	}
	405
4a8282d0	406	if (pdata->irq >= 0)
c92182ee YK	407	device_init_wakeup(&pdev->dev, 1);
c92182ee YK	408
033ca3ad	409	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
5f54c8a0 WS	410	THIS_MODULE);
	411	if (IS_ERR(rtc)) {
	412	ret = PTR_ERR(rtc);
8f5fe778	413	goto exit_put_clk_ref;
5f54c8a0 WS	414	}
	415
	416	pdata->rtc = rtc;
	417
d00ed3cf DM	418	return 0;
d00ed3cf DM	419
8f5fe778 PR	420	exit_put_clk_ref:
	421	clk_disable_unprepare(pdata->clk_ref);
	422	exit_put_clk_ipg:
	423	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf	424
d00ed3cf DM	425	return ret;
	426	}
	427
5a167f45	428	static int mxc_rtc_remove(struct platform_device *pdev)
d00ed3cf DM	429	{
	430	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	431
8f5fe778 PR	432	clk_disable_unprepare(pdata->clk_ref);
8f5fe778 PR	433	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf DM	434
	435	return 0;
	436	}
	437
75634cc4	438	#ifdef CONFIG_PM_SLEEP
c92182ee YK	439	static int mxc_rtc_suspend(struct device *dev)
	440	{
	441	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	442
	443	if (device_may_wakeup(dev))
	444	enable_irq_wake(pdata->irq);
	445
	446	return 0;
	447	}
	448
	449	static int mxc_rtc_resume(struct device *dev)
	450	{
	451	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	452
	453	if (device_may_wakeup(dev))
	454	disable_irq_wake(pdata->irq);
	455
	456	return 0;
	457	}
c92182ee YK	458	#endif
c92182ee YK	459
75634cc4 JH	460	static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
75634cc4 JH	461
d00ed3cf DM	462	static struct platform_driver mxc_rtc_driver = {
	463	.driver = {
	464	.name = "mxc_rtc",
cec13c26	465	.of_match_table = of_match_ptr(imx_rtc_dt_ids),
c92182ee	466	.pm = &mxc_rtc_pm_ops,
d00ed3cf	467	},
bb1d34a2	468	.id_table = imx_rtc_devtype,
be8b6d51	469	.probe = mxc_rtc_probe,
5a167f45	470	.remove = mxc_rtc_remove,
d00ed3cf DM	471	};
d00ed3cf DM	472
be8b6d51	473	module_platform_driver(mxc_rtc_driver)
d00ed3cf DM	474
	475	MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
	476	MODULE_DESCRIPTION("RTC driver for Freescale MXC");
	477	MODULE_LICENSE("GPL");
	478