[linux-2.6-block.git] / drivers / rtc / rtc-mxc.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>

#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)

#define RTC_SW_BIT      (1 << 0)
#define RTC_ALM_BIT     (1 << 2)
#define RTC_1HZ_BIT     (1 << 4)
#define RTC_2HZ_BIT     (1 << 7)
#define RTC_SAM0_BIT    (1 << 8)
#define RTC_SAM1_BIT    (1 << 9)
#define RTC_SAM2_BIT    (1 << 10)
#define RTC_SAM3_BIT    (1 << 11)
#define RTC_SAM4_BIT    (1 << 12)
#define RTC_SAM5_BIT    (1 << 13)
#define RTC_SAM6_BIT    (1 << 14)
#define RTC_SAM7_BIT    (1 << 15)
#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
			 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
			 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)

#define RTC_ENABLE_BIT  (1 << 7)

#define MAX_PIE_NUM     9
#define MAX_PIE_FREQ    512

#define MXC_RTC_TIME	0
#define MXC_RTC_ALARM	1

#define RTC_HOURMIN	0x00	/*  32bit rtc hour/min counter reg */
#define RTC_SECOND	0x04	/*  32bit rtc seconds counter reg */
#define RTC_ALRM_HM	0x08	/*  32bit rtc alarm hour/min reg */
#define RTC_ALRM_SEC	0x0C	/*  32bit rtc alarm seconds reg */
#define RTC_RTCCTL	0x10	/*  32bit rtc control reg */
#define RTC_RTCISR	0x14	/*  32bit rtc interrupt status reg */
#define RTC_RTCIENR	0x18	/*  32bit rtc interrupt enable reg */
#define RTC_STPWCH	0x1C	/*  32bit rtc stopwatch min reg */
#define RTC_DAYR	0x20	/*  32bit rtc days counter reg */
#define RTC_DAYALARM	0x24	/*  32bit rtc day alarm reg */
#define RTC_TEST1	0x28	/*  32bit rtc test reg 1 */
#define RTC_TEST2	0x2C	/*  32bit rtc test reg 2 */
#define RTC_TEST3	0x30	/*  32bit rtc test reg 3 */

enum imx_rtc_type {
	IMX1_RTC,
	IMX21_RTC,
};

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk_ref;
	struct clk *clk_ipg;
	struct rtc_time g_rtc_alarm;
	enum imx_rtc_type devtype;
};

static const struct platform_device_id imx_rtc_devtype[] = {
	{
		.name = "imx1-rtc",
		.driver_data = IMX1_RTC,
	}, {
		.name = "imx21-rtc",
		.driver_data = IMX21_RTC,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);

#ifdef CONFIG_OF
static const struct of_device_id imx_rtc_dt_ids[] = {
	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	{}
};
MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
#endif

static inline int is_imx1_rtc(struct rtc_plat_data *data)
{
	return data->devtype == IMX1_RTC;
}

/*
 * This function is used to obtain the RTC time or the alarm value in
 * second.
 */
static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		day = readw(ioaddr + RTC_DAYR);
		hr_min = readw(ioaddr + RTC_HOURMIN);
		sec = readw(ioaddr + RTC_SECOND);
		break;
	case MXC_RTC_ALARM:
		day = readw(ioaddr + RTC_DAYALARM);
		hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
		sec = readw(ioaddr + RTC_ALRM_SEC);
		break;
	}

	hr = hr_min >> 8;
	min = hr_min & 0xff;

	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
}

/*
 * This function sets the RTC alarm value or the time value.
 */
static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
{
	u32 tod, day, hr, min, sec, temp;
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	day = div_s64_rem(time, 86400, &tod);

	/* time is within a day now */
	hr = tod / 3600;
	tod -= hr * 3600;

	/* time is within an hour now */
	min = tod / 60;
	sec = tod - min * 60;

	temp = (hr << 8) + min;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		writew(day, ioaddr + RTC_DAYR);
		writew(sec, ioaddr + RTC_SECOND);
		writew(temp, ioaddr + RTC_HOURMIN);
		break;
	case MXC_RTC_ALARM:
		writew(day, ioaddr + RTC_DAYALARM);
		writew(sec, ioaddr + RTC_ALRM_SEC);
		writew(temp, ioaddr + RTC_ALRM_HM);
		break;
	}
}

/*
 * This function updates the RTC alarm registers and then clears all the
 * interrupt status bits.
 */
static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
{
	time64_t time;
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	time = rtc_tm_to_time64(alrm);

	/* clear all the interrupt status bits */
	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
}

static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
				unsigned int enabled)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 reg;

	spin_lock_irq(&pdata->rtc->irq_lock);
	reg = readw(ioaddr + RTC_RTCIENR);

	if (enabled)
		reg |= bit;
	else
		reg &= ~bit;

	writew(reg, ioaddr + RTC_RTCIENR);
	spin_unlock_irq(&pdata->rtc->irq_lock);
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 status;
	u32 events = 0;

	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	/* clear interrupt sources */
	writew(status, ioaddr + RTC_RTCISR);

	/* update irq data & counter */
	if (status & RTC_ALM_BIT) {
		events |= (RTC_AF | RTC_IRQF);
		/* RTC alarm should be one-shot */
		mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	}

	if (status & PIT_ALL_ON)
		events |= (RTC_PF | RTC_IRQF);

	rtc_update_irq(pdata->rtc, 1, events);
	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);

	return IRQ_HANDLED;
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	time64_t val;

	/* Avoid roll-over from reading the different registers */
	do {
		val = get_alarm_or_time(dev, MXC_RTC_TIME);
	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));

	rtc_time64_to_tm(val, tm);

	return 0;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 */
static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	/*
	 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	 */
	if (is_imx1_rtc(pdata)) {
		struct rtc_time tm;

		rtc_time64_to_tm(time, &tm);
		tm.tm_year = 70;
		time = rtc_tm_to_time64(&tm);
	}

	/* Avoid roll-over from reading the different registers */
	do {
		set_alarm_or_time(dev, MXC_RTC_TIME, time);
	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));

	return 0;
}

/*
 * This function reads the current alarm value into the passed in 'alrm'
 * argument. It updates the alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	void __iomem *ioaddr = pdata->ioaddr;

	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;

	return 0;
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	rtc_update_alarm(dev, &alrm->time);

	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);

	return 0;
}

/* RTC layer */
static const struct rtc_class_ops mxc_rtc_ops = {
	.read_time		= mxc_rtc_read_time,
	.set_mmss64		= mxc_rtc_set_mmss,
	.read_alarm		= mxc_rtc_read_alarm,
	.set_alarm		= mxc_rtc_set_alarm,
	.alarm_irq_enable	= mxc_rtc_alarm_irq_enable,
};

static int mxc_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	struct rtc_plat_data *pdata = NULL;
	u32 reg;
	unsigned long rate;
	int ret;
	const struct of_device_id *of_id;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	if (of_id)
		pdata->devtype = (enum imx_rtc_type)of_id->data;
	else
		pdata->devtype = pdev->id_entry->driver_data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pdata->ioaddr))
		return PTR_ERR(pdata->ioaddr);

	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(pdata->clk_ipg)) {
		dev_err(&pdev->dev, "unable to get ipg clock!\n");
		return PTR_ERR(pdata->clk_ipg);
	}

	ret = clk_prepare_enable(pdata->clk_ipg);
	if (ret)
		return ret;

	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	if (IS_ERR(pdata->clk_ref)) {
		dev_err(&pdev->dev, "unable to get ref clock!\n");
		ret = PTR_ERR(pdata->clk_ref);
		goto exit_put_clk_ipg;
	}

	ret = clk_prepare_enable(pdata->clk_ref);
	if (ret)
		goto exit_put_clk_ipg;

	rate = clk_get_rate(pdata->clk_ref);

	if (rate == 32768)
		reg = RTC_INPUT_CLK_32768HZ;
	else if (rate == 32000)
		reg = RTC_INPUT_CLK_32000HZ;
	else if (rate == 38400)
		reg = RTC_INPUT_CLK_38400HZ;
	else {
		dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
		ret = -EINVAL;
		goto exit_put_clk_ref;
	}

	reg |= RTC_ENABLE_BIT;
	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
		dev_err(&pdev->dev, "hardware module can't be enabled!\n");
		ret = -EIO;
		goto exit_put_clk_ref;
	}

	platform_set_drvdata(pdev, pdata);

	/* Configure and enable the RTC */
	pdata->irq = platform_get_irq(pdev, 0);

	if (pdata->irq >= 0 &&
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
			     IRQF_SHARED, pdev->name, pdev) < 0) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		pdata->irq = -1;
	}

	if (pdata->irq >= 0)
		device_init_wakeup(&pdev->dev, 1);

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
				  THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		goto exit_put_clk_ref;
	}

	pdata->rtc = rtc;

	return 0;

exit_put_clk_ref:
	clk_disable_unprepare(pdata->clk_ref);
exit_put_clk_ipg:
	clk_disable_unprepare(pdata->clk_ipg);

	return ret;
}

static int mxc_rtc_remove(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	clk_disable_unprepare(pdata->clk_ref);
	clk_disable_unprepare(pdata->clk_ipg);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mxc_rtc_suspend(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pdata->irq);

	return 0;
}

static int mxc_rtc_resume(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pdata->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		   .name	= "mxc_rtc",
		   .of_match_table = of_match_ptr(imx_rtc_dt_ids),
		   .pm		= &mxc_rtc_pm_ops,
	},
	.id_table = imx_rtc_devtype,
	.probe = mxc_rtc_probe,
	.remove = mxc_rtc_remove,
};

module_platform_driver(mxc_rtc_driver)

MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("RTC driver for Freescale MXC");
MODULE_LICENSE("GPL");
Commit	Line	Data
75d01b75 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
d00ed3cf DM	4
	5	#include <linux/io.h>
	6	#include <linux/rtc.h>
	7	#include <linux/module.h>
5a0e3ad6	8	#include <linux/slab.h>
d00ed3cf DM	9	#include <linux/interrupt.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/clk.h>
cec13c26 PR	12	#include <linux/of.h>
cec13c26 PR	13	#include <linux/of_device.h>
d00ed3cf	14
d00ed3cf DM	15	#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
	16	#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
	17	#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
	18
	19	#define RTC_SW_BIT (1 << 0)
	20	#define RTC_ALM_BIT (1 << 2)
	21	#define RTC_1HZ_BIT (1 << 4)
	22	#define RTC_2HZ_BIT (1 << 7)
	23	#define RTC_SAM0_BIT (1 << 8)
	24	#define RTC_SAM1_BIT (1 << 9)
	25	#define RTC_SAM2_BIT (1 << 10)
	26	#define RTC_SAM3_BIT (1 << 11)
	27	#define RTC_SAM4_BIT (1 << 12)
	28	#define RTC_SAM5_BIT (1 << 13)
	29	#define RTC_SAM6_BIT (1 << 14)
	30	#define RTC_SAM7_BIT (1 << 15)
	31	#define PIT_ALL_ON (RTC_2HZ_BIT \| RTC_SAM0_BIT \| RTC_SAM1_BIT \| \
	32	RTC_SAM2_BIT \| RTC_SAM3_BIT \| RTC_SAM4_BIT \| \
	33	RTC_SAM5_BIT \| RTC_SAM6_BIT \| RTC_SAM7_BIT)
	34
	35	#define RTC_ENABLE_BIT (1 << 7)
	36
	37	#define MAX_PIE_NUM 9
	38	#define MAX_PIE_FREQ 512
d00ed3cf	39
d00ed3cf DM	40	#define MXC_RTC_TIME 0
	41	#define MXC_RTC_ALARM 1
	42
	43	#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
	44	#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
	45	#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
	46	#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
	47	#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
	48	#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
	49	#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
	50	#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
	51	#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
	52	#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
	53	#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
	54	#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
	55	#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
	56
bb1d34a2 SG	57	enum imx_rtc_type {
	58	IMX1_RTC,
	59	IMX21_RTC,
	60	};
	61
d00ed3cf DM	62	struct rtc_plat_data {
	63	struct rtc_device *rtc;
	64	void __iomem *ioaddr;
	65	int irq;
8f5fe778 PR	66	struct clk *clk_ref;
8f5fe778 PR	67	struct clk *clk_ipg;
d00ed3cf	68	struct rtc_time g_rtc_alarm;
bb1d34a2	69	enum imx_rtc_type devtype;
d00ed3cf DM	70	};
d00ed3cf DM	71
cd6ba00a	72	static const struct platform_device_id imx_rtc_devtype[] = {
bb1d34a2 SG	73	{
	74	.name = "imx1-rtc",
	75	.driver_data = IMX1_RTC,
	76	}, {
	77	.name = "imx21-rtc",
	78	.driver_data = IMX21_RTC,
	79	}, {
	80	/* sentinel */
	81	}
	82	};
	83	MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
	84
cec13c26 PR	85	#ifdef CONFIG_OF
	86	static const struct of_device_id imx_rtc_dt_ids[] = {
	87	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	88	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	89	{}
	90	};
	91	MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
	92	#endif
	93
bb1d34a2 SG	94	static inline int is_imx1_rtc(struct rtc_plat_data *data)
	95	{
	96	return data->devtype == IMX1_RTC;
	97	}
	98
d00ed3cf DM	99	/*
	100	* This function is used to obtain the RTC time or the alarm value in
	101	* second.
	102	*/
a015b8aa	103	static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
d00ed3cf	104	{
85368bb9	105	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	106	void __iomem *ioaddr = pdata->ioaddr;
	107	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
	108
	109	switch (time_alarm) {
	110	case MXC_RTC_TIME:
	111	day = readw(ioaddr + RTC_DAYR);
	112	hr_min = readw(ioaddr + RTC_HOURMIN);
	113	sec = readw(ioaddr + RTC_SECOND);
	114	break;
	115	case MXC_RTC_ALARM:
	116	day = readw(ioaddr + RTC_DAYALARM);
	117	hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
	118	sec = readw(ioaddr + RTC_ALRM_SEC);
	119	break;
	120	}
	121
	122	hr = hr_min >> 8;
	123	min = hr_min & 0xff;
	124
a015b8aa	125	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
d00ed3cf DM	126	}
	127
	128	/*
	129	* This function sets the RTC alarm value or the time value.
	130	*/
a015b8aa	131	static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
d00ed3cf	132	{
a015b8aa	133	u32 tod, day, hr, min, sec, temp;
85368bb9	134	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	135	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	136
a015b8aa	137	day = div_s64_rem(time, 86400, &tod);
d00ed3cf DM	138
d00ed3cf DM	139	/* time is within a day now */
a015b8aa XP	140	hr = tod / 3600;
a015b8aa XP	141	tod -= hr * 3600;
d00ed3cf DM	142
d00ed3cf DM	143	/* time is within an hour now */
a015b8aa XP	144	min = tod / 60;
a015b8aa XP	145	sec = tod - min * 60;
d00ed3cf DM	146
	147	temp = (hr << 8) + min;
	148
	149	switch (time_alarm) {
	150	case MXC_RTC_TIME:
	151	writew(day, ioaddr + RTC_DAYR);
	152	writew(sec, ioaddr + RTC_SECOND);
	153	writew(temp, ioaddr + RTC_HOURMIN);
	154	break;
	155	case MXC_RTC_ALARM:
	156	writew(day, ioaddr + RTC_DAYALARM);
	157	writew(sec, ioaddr + RTC_ALRM_SEC);
	158	writew(temp, ioaddr + RTC_ALRM_HM);
	159	break;
	160	}
	161	}
	162
	163	/*
	164	* This function updates the RTC alarm registers and then clears all the
	165	* interrupt status bits.
	166	*/
482494a8	167	static void rtc_update_alarm(struct device dev, struct rtc_time alrm)
d00ed3cf	168	{
a015b8aa	169	time64_t time;
85368bb9	170	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	171	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	172
a015b8aa	173	time = rtc_tm_to_time64(alrm);
d00ed3cf	174
d00ed3cf DM	175	/* clear all the interrupt status bits */
	176	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	177	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
c92182ee YK	178	}
	179
	180	static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
	181	unsigned int enabled)
	182	{
85368bb9	183	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
c92182ee YK	184	void __iomem *ioaddr = pdata->ioaddr;
	185	u32 reg;
	186
	187	spin_lock_irq(&pdata->rtc->irq_lock);
	188	reg = readw(ioaddr + RTC_RTCIENR);
	189
	190	if (enabled)
	191	reg \|= bit;
	192	else
	193	reg &= ~bit;
	194
	195	writew(reg, ioaddr + RTC_RTCIENR);
	196	spin_unlock_irq(&pdata->rtc->irq_lock);
d00ed3cf DM	197	}
	198
	199	/* This function is the RTC interrupt service routine. */
	200	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	201	{
	202	struct platform_device *pdev = dev_id;
	203	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	204	void __iomem *ioaddr = pdata->ioaddr;
b59f6d1f	205	unsigned long flags;
d00ed3cf DM	206	u32 status;
	207	u32 events = 0;
	208
b59f6d1f	209	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	210	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	211	/* clear interrupt sources */
	212	writew(status, ioaddr + RTC_RTCISR);
	213
d00ed3cf	214	/* update irq data & counter */
c92182ee	215	if (status & RTC_ALM_BIT) {
d00ed3cf	216	events \|= (RTC_AF \| RTC_IRQF);
c92182ee YK	217	/* RTC alarm should be one-shot */
	218	mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	219	}
d00ed3cf	220
d00ed3cf DM	221	if (status & PIT_ALL_ON)
	222	events \|= (RTC_PF \| RTC_IRQF);
	223
d00ed3cf	224	rtc_update_irq(pdata->rtc, 1, events);
b59f6d1f	225	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	226
	227	return IRQ_HANDLED;
	228	}
	229
d00ed3cf DM	230	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	231	{
	232	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	233	return 0;
	234	}
	235
d00ed3cf DM	236	/*
	237	* This function reads the current RTC time into tm in Gregorian date.
	238	*/
	239	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
	240	{
a015b8aa	241	time64_t val;
d00ed3cf DM	242
	243	/* Avoid roll-over from reading the different registers */
	244	do {
	245	val = get_alarm_or_time(dev, MXC_RTC_TIME);
	246	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
	247
a015b8aa	248	rtc_time64_to_tm(val, tm);
d00ed3cf DM	249
	250	return 0;
	251	}
	252
	253	/*
	254	* This function sets the internal RTC time based on tm in Gregorian date.
	255	*/
933623c3	256	static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
d00ed3cf	257	{
85368bb9	258	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
bb1d34a2	259
7287be1d YK	260	/*
	261	* TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	262	*/
bb1d34a2	263	if (is_imx1_rtc(pdata)) {
7287be1d YK	264	struct rtc_time tm;
7287be1d YK	265
933623c3	266	rtc_time64_to_tm(time, &tm);
7287be1d	267	tm.tm_year = 70;
933623c3	268	time = rtc_tm_to_time64(&tm);
7287be1d YK	269	}
7287be1d YK	270
d00ed3cf DM	271	/* Avoid roll-over from reading the different registers */
	272	do {
	273	set_alarm_or_time(dev, MXC_RTC_TIME, time);
	274	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
	275
	276	return 0;
	277	}
	278
	279	/*
	280	* This function reads the current alarm value into the passed in 'alrm'
	281	* argument. It updates the alrm's pending field value based on the whether
	282	* an alarm interrupt occurs or not.
	283	*/
	284	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	285	{
85368bb9	286	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf DM	287	void __iomem *ioaddr = pdata->ioaddr;
d00ed3cf DM	288
a015b8aa	289	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
d00ed3cf DM	290	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
	291
	292	return 0;
	293	}
	294
	295	/*
	296	* This function sets the RTC alarm based on passed in alrm.
	297	*/
	298	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	299	{
85368bb9	300	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
d00ed3cf	301
482494a8	302	rtc_update_alarm(dev, &alrm->time);
d00ed3cf DM	303
	304	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	305	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
	306
	307	return 0;
	308	}
	309
	310	/* RTC layer */
8bc57e7f	311	static const struct rtc_class_ops mxc_rtc_ops = {
d00ed3cf	312	.read_time = mxc_rtc_read_time,
933623c3	313	.set_mmss64 = mxc_rtc_set_mmss,
d00ed3cf DM	314	.read_alarm = mxc_rtc_read_alarm,
	315	.set_alarm = mxc_rtc_set_alarm,
	316	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
d00ed3cf DM	317	};
d00ed3cf DM	318
5a167f45	319	static int mxc_rtc_probe(struct platform_device *pdev)
d00ed3cf	320	{
d00ed3cf DM	321	struct resource *res;
	322	struct rtc_device *rtc;
	323	struct rtc_plat_data *pdata = NULL;
	324	u32 reg;
c783a29e VZ	325	unsigned long rate;
c783a29e VZ	326	int ret;
cec13c26	327	const struct of_device_id *of_id;
d00ed3cf	328
c783a29e	329	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
d00ed3cf DM	330	if (!pdata)
	331	return -ENOMEM;
	332
cec13c26 PR	333	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	334	if (of_id)
	335	pdata->devtype = (enum imx_rtc_type)of_id->data;
	336	else
	337	pdata->devtype = pdev->id_entry->driver_data;
bb1d34a2	338
7c1d69ee JL	339	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	340	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	341	if (IS_ERR(pdata->ioaddr))
	342	return PTR_ERR(pdata->ioaddr);
d00ed3cf	343
8f5fe778 PR	344	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	345	if (IS_ERR(pdata->clk_ipg)) {
	346	dev_err(&pdev->dev, "unable to get ipg clock!\n");
	347	return PTR_ERR(pdata->clk_ipg);
49908e73	348	}
d00ed3cf	349
8f5fe778	350	ret = clk_prepare_enable(pdata->clk_ipg);
1b3d2243 FE	351	if (ret)
	352	return ret;
	353
8f5fe778 PR	354	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	355	if (IS_ERR(pdata->clk_ref)) {
	356	dev_err(&pdev->dev, "unable to get ref clock!\n");
	357	ret = PTR_ERR(pdata->clk_ref);
	358	goto exit_put_clk_ipg;
	359	}
	360
	361	ret = clk_prepare_enable(pdata->clk_ref);
	362	if (ret)
	363	goto exit_put_clk_ipg;
	364
	365	rate = clk_get_rate(pdata->clk_ref);
d00ed3cf DM	366
	367	if (rate == 32768)
	368	reg = RTC_INPUT_CLK_32768HZ;
	369	else if (rate == 32000)
	370	reg = RTC_INPUT_CLK_32000HZ;
	371	else if (rate == 38400)
	372	reg = RTC_INPUT_CLK_38400HZ;
	373	else {
c783a29e	374	dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
d00ed3cf	375	ret = -EINVAL;
8f5fe778	376	goto exit_put_clk_ref;
d00ed3cf DM	377	}
	378
	379	reg \|= RTC_ENABLE_BIT;
	380	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	381	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
	382	dev_err(&pdev->dev, "hardware module can't be enabled!\n");
	383	ret = -EIO;
8f5fe778	384	goto exit_put_clk_ref;
d00ed3cf DM	385	}
d00ed3cf DM	386
d00ed3cf DM	387	platform_set_drvdata(pdev, pdata);
	388
	389	/* Configure and enable the RTC */
	390	pdata->irq = platform_get_irq(pdev, 0);
	391
	392	if (pdata->irq >= 0 &&
c783a29e VZ	393	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
c783a29e VZ	394	IRQF_SHARED, pdev->name, pdev) < 0) {
d00ed3cf DM	395	dev_warn(&pdev->dev, "interrupt not available.\n");
	396	pdata->irq = -1;
	397	}
	398
4a8282d0	399	if (pdata->irq >= 0)
c92182ee YK	400	device_init_wakeup(&pdev->dev, 1);
c92182ee YK	401
033ca3ad	402	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
5f54c8a0 WS	403	THIS_MODULE);
	404	if (IS_ERR(rtc)) {
	405	ret = PTR_ERR(rtc);
8f5fe778	406	goto exit_put_clk_ref;
5f54c8a0 WS	407	}
	408
	409	pdata->rtc = rtc;
	410
d00ed3cf DM	411	return 0;
d00ed3cf DM	412
8f5fe778 PR	413	exit_put_clk_ref:
	414	clk_disable_unprepare(pdata->clk_ref);
	415	exit_put_clk_ipg:
	416	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf	417
d00ed3cf DM	418	return ret;
	419	}
	420
5a167f45	421	static int mxc_rtc_remove(struct platform_device *pdev)
d00ed3cf DM	422	{
	423	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	424
8f5fe778 PR	425	clk_disable_unprepare(pdata->clk_ref);
8f5fe778 PR	426	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf DM	427
	428	return 0;
	429	}
	430
75634cc4	431	#ifdef CONFIG_PM_SLEEP
c92182ee YK	432	static int mxc_rtc_suspend(struct device *dev)
	433	{
	434	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	435
	436	if (device_may_wakeup(dev))
	437	enable_irq_wake(pdata->irq);
	438
	439	return 0;
	440	}
	441
	442	static int mxc_rtc_resume(struct device *dev)
	443	{
	444	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	445
	446	if (device_may_wakeup(dev))
	447	disable_irq_wake(pdata->irq);
	448
	449	return 0;
	450	}
c92182ee YK	451	#endif
c92182ee YK	452
75634cc4 JH	453	static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
75634cc4 JH	454
d00ed3cf DM	455	static struct platform_driver mxc_rtc_driver = {
	456	.driver = {
	457	.name = "mxc_rtc",
cec13c26	458	.of_match_table = of_match_ptr(imx_rtc_dt_ids),
c92182ee	459	.pm = &mxc_rtc_pm_ops,
d00ed3cf	460	},
bb1d34a2	461	.id_table = imx_rtc_devtype,
be8b6d51	462	.probe = mxc_rtc_probe,
5a167f45	463	.remove = mxc_rtc_remove,
d00ed3cf DM	464	};
d00ed3cf DM	465
be8b6d51	466	module_platform_driver(mxc_rtc_driver)
d00ed3cf DM	467
	468	MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
	469	MODULE_DESCRIPTION("RTC driver for Freescale MXC");
	470	MODULE_LICENSE("GPL");
	471