[linux-2.6-block.git] / drivers / rtc / rtc-mxc.c

/*
 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>

#define RTC_INPUT_CLK_32768HZ	(0x00 << 5)
#define RTC_INPUT_CLK_32000HZ	(0x01 << 5)
#define RTC_INPUT_CLK_38400HZ	(0x02 << 5)

#define RTC_SW_BIT      (1 << 0)
#define RTC_ALM_BIT     (1 << 2)
#define RTC_1HZ_BIT     (1 << 4)
#define RTC_2HZ_BIT     (1 << 7)
#define RTC_SAM0_BIT    (1 << 8)
#define RTC_SAM1_BIT    (1 << 9)
#define RTC_SAM2_BIT    (1 << 10)
#define RTC_SAM3_BIT    (1 << 11)
#define RTC_SAM4_BIT    (1 << 12)
#define RTC_SAM5_BIT    (1 << 13)
#define RTC_SAM6_BIT    (1 << 14)
#define RTC_SAM7_BIT    (1 << 15)
#define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
			 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
			 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)

#define RTC_ENABLE_BIT  (1 << 7)

#define MAX_PIE_NUM     9
#define MAX_PIE_FREQ    512

#define MXC_RTC_TIME	0
#define MXC_RTC_ALARM	1

#define RTC_HOURMIN	0x00	/*  32bit rtc hour/min counter reg */
#define RTC_SECOND	0x04	/*  32bit rtc seconds counter reg */
#define RTC_ALRM_HM	0x08	/*  32bit rtc alarm hour/min reg */
#define RTC_ALRM_SEC	0x0C	/*  32bit rtc alarm seconds reg */
#define RTC_RTCCTL	0x10	/*  32bit rtc control reg */
#define RTC_RTCISR	0x14	/*  32bit rtc interrupt status reg */
#define RTC_RTCIENR	0x18	/*  32bit rtc interrupt enable reg */
#define RTC_STPWCH	0x1C	/*  32bit rtc stopwatch min reg */
#define RTC_DAYR	0x20	/*  32bit rtc days counter reg */
#define RTC_DAYALARM	0x24	/*  32bit rtc day alarm reg */
#define RTC_TEST1	0x28	/*  32bit rtc test reg 1 */
#define RTC_TEST2	0x2C	/*  32bit rtc test reg 2 */
#define RTC_TEST3	0x30	/*  32bit rtc test reg 3 */

enum imx_rtc_type {
	IMX1_RTC,
	IMX21_RTC,
};

struct rtc_plat_data {
	struct rtc_device *rtc;
	void __iomem *ioaddr;
	int irq;
	struct clk *clk_ref;
	struct clk *clk_ipg;
	struct rtc_time g_rtc_alarm;
	enum imx_rtc_type devtype;
};

static const struct platform_device_id imx_rtc_devtype[] = {
	{
		.name = "imx1-rtc",
		.driver_data = IMX1_RTC,
	}, {
		.name = "imx21-rtc",
		.driver_data = IMX21_RTC,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);

#ifdef CONFIG_OF
static const struct of_device_id imx_rtc_dt_ids[] = {
	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	{}
};
MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
#endif

static inline int is_imx1_rtc(struct rtc_plat_data *data)
{
	return data->devtype == IMX1_RTC;
}

/*
 * This function is used to obtain the RTC time or the alarm value in
 * second.
 */
static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		day = readw(ioaddr + RTC_DAYR);
		hr_min = readw(ioaddr + RTC_HOURMIN);
		sec = readw(ioaddr + RTC_SECOND);
		break;
	case MXC_RTC_ALARM:
		day = readw(ioaddr + RTC_DAYALARM);
		hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
		sec = readw(ioaddr + RTC_ALRM_SEC);
		break;
	}

	hr = hr_min >> 8;
	min = hr_min & 0xff;

	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
}

/*
 * This function sets the RTC alarm value or the time value.
 */
static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
{
	u32 tod, day, hr, min, sec, temp;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	day = div_s64_rem(time, 86400, &tod);

	/* time is within a day now */
	hr = tod / 3600;
	tod -= hr * 3600;

	/* time is within an hour now */
	min = tod / 60;
	sec = tod - min * 60;

	temp = (hr << 8) + min;

	switch (time_alarm) {
	case MXC_RTC_TIME:
		writew(day, ioaddr + RTC_DAYR);
		writew(sec, ioaddr + RTC_SECOND);
		writew(temp, ioaddr + RTC_HOURMIN);
		break;
	case MXC_RTC_ALARM:
		writew(day, ioaddr + RTC_DAYALARM);
		writew(sec, ioaddr + RTC_ALRM_SEC);
		writew(temp, ioaddr + RTC_ALRM_HM);
		break;
	}
}

/*
 * This function updates the RTC alarm registers and then clears all the
 * interrupt status bits.
 */
static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
{
	time64_t time;
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	time = rtc_tm_to_time64(alrm);

	/* clear all the interrupt status bits */
	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
}

static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
				unsigned int enabled)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	u32 reg;

	spin_lock_irq(&pdata->rtc->irq_lock);
	reg = readw(ioaddr + RTC_RTCIENR);

	if (enabled)
		reg |= bit;
	else
		reg &= ~bit;

	writew(reg, ioaddr + RTC_RTCIENR);
	spin_unlock_irq(&pdata->rtc->irq_lock);
}

/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = dev_id;
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;
	unsigned long flags;
	u32 status;
	u32 events = 0;

	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	/* clear interrupt sources */
	writew(status, ioaddr + RTC_RTCISR);

	/* update irq data & counter */
	if (status & RTC_ALM_BIT) {
		events |= (RTC_AF | RTC_IRQF);
		/* RTC alarm should be one-shot */
		mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	}

	if (status & PIT_ALL_ON)
		events |= (RTC_PF | RTC_IRQF);

	rtc_update_irq(pdata->rtc, 1, events);
	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);

	return IRQ_HANDLED;
}

/*
 * Clear all interrupts and release the IRQ
 */
static void mxc_rtc_release(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	spin_lock_irq(&pdata->rtc->irq_lock);

	/* Disable all rtc interrupts */
	writew(0, ioaddr + RTC_RTCIENR);

	/* Clear all interrupt status */
	writew(0xffffffff, ioaddr + RTC_RTCISR);

	spin_unlock_irq(&pdata->rtc->irq_lock);
}

static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	return 0;
}

/*
 * This function reads the current RTC time into tm in Gregorian date.
 */
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	time64_t val;

	/* Avoid roll-over from reading the different registers */
	do {
		val = get_alarm_or_time(dev, MXC_RTC_TIME);
	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));

	rtc_time64_to_tm(val, tm);

	return 0;
}

/*
 * This function sets the internal RTC time based on tm in Gregorian date.
 */
static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	/*
	 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	 */
	if (is_imx1_rtc(pdata)) {
		struct rtc_time tm;

		rtc_time64_to_tm(time, &tm);
		tm.tm_year = 70;
		time = rtc_tm_to_time64(&tm);
	}

	/* Avoid roll-over from reading the different registers */
	do {
		set_alarm_or_time(dev, MXC_RTC_TIME, time);
	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));

	return 0;
}

/*
 * This function reads the current alarm value into the passed in 'alrm'
 * argument. It updates the alrm's pending field value based on the whether
 * an alarm interrupt occurs or not.
 */
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	void __iomem *ioaddr = pdata->ioaddr;

	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;

	return 0;
}

/*
 * This function sets the RTC alarm based on passed in alrm.
 */
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	rtc_update_alarm(dev, &alrm->time);

	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);

	return 0;
}

/* RTC layer */
static const struct rtc_class_ops mxc_rtc_ops = {
	.release		= mxc_rtc_release,
	.read_time		= mxc_rtc_read_time,
	.set_mmss64		= mxc_rtc_set_mmss,
	.read_alarm		= mxc_rtc_read_alarm,
	.set_alarm		= mxc_rtc_set_alarm,
	.alarm_irq_enable	= mxc_rtc_alarm_irq_enable,
};

static int mxc_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	struct rtc_plat_data *pdata = NULL;
	u32 reg;
	unsigned long rate;
	int ret;
	const struct of_device_id *of_id;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	if (of_id)
		pdata->devtype = (enum imx_rtc_type)of_id->data;
	else
		pdata->devtype = pdev->id_entry->driver_data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pdata->ioaddr))
		return PTR_ERR(pdata->ioaddr);

	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(pdata->clk_ipg)) {
		dev_err(&pdev->dev, "unable to get ipg clock!\n");
		return PTR_ERR(pdata->clk_ipg);
	}

	ret = clk_prepare_enable(pdata->clk_ipg);
	if (ret)
		return ret;

	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	if (IS_ERR(pdata->clk_ref)) {
		dev_err(&pdev->dev, "unable to get ref clock!\n");
		ret = PTR_ERR(pdata->clk_ref);
		goto exit_put_clk_ipg;
	}

	ret = clk_prepare_enable(pdata->clk_ref);
	if (ret)
		goto exit_put_clk_ipg;

	rate = clk_get_rate(pdata->clk_ref);

	if (rate == 32768)
		reg = RTC_INPUT_CLK_32768HZ;
	else if (rate == 32000)
		reg = RTC_INPUT_CLK_32000HZ;
	else if (rate == 38400)
		reg = RTC_INPUT_CLK_38400HZ;
	else {
		dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
		ret = -EINVAL;
		goto exit_put_clk_ref;
	}

	reg |= RTC_ENABLE_BIT;
	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
		dev_err(&pdev->dev, "hardware module can't be enabled!\n");
		ret = -EIO;
		goto exit_put_clk_ref;
	}

	platform_set_drvdata(pdev, pdata);

	/* Configure and enable the RTC */
	pdata->irq = platform_get_irq(pdev, 0);

	if (pdata->irq >= 0 &&
	    devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
			     IRQF_SHARED, pdev->name, pdev) < 0) {
		dev_warn(&pdev->dev, "interrupt not available.\n");
		pdata->irq = -1;
	}

	if (pdata->irq >= 0)
		device_init_wakeup(&pdev->dev, 1);

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
				  THIS_MODULE);
	if (IS_ERR(rtc)) {
		ret = PTR_ERR(rtc);
		goto exit_put_clk_ref;
	}

	pdata->rtc = rtc;

	return 0;

exit_put_clk_ref:
	clk_disable_unprepare(pdata->clk_ref);
exit_put_clk_ipg:
	clk_disable_unprepare(pdata->clk_ipg);

	return ret;
}

static int mxc_rtc_remove(struct platform_device *pdev)
{
	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);

	clk_disable_unprepare(pdata->clk_ref);
	clk_disable_unprepare(pdata->clk_ipg);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mxc_rtc_suspend(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		enable_irq_wake(pdata->irq);

	return 0;
}

static int mxc_rtc_resume(struct device *dev)
{
	struct rtc_plat_data *pdata = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		disable_irq_wake(pdata->irq);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);

static struct platform_driver mxc_rtc_driver = {
	.driver = {
		   .name	= "mxc_rtc",
		   .of_match_table = of_match_ptr(imx_rtc_dt_ids),
		   .pm		= &mxc_rtc_pm_ops,
	},
	.id_table = imx_rtc_devtype,
	.probe = mxc_rtc_probe,
	.remove = mxc_rtc_remove,
};

module_platform_driver(mxc_rtc_driver)

MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("RTC driver for Freescale MXC");
MODULE_LICENSE("GPL");
Commit	Line	Data
d00ed3cf DM	1	/*
	2	* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	#include <linux/io.h>
	13	#include <linux/rtc.h>
	14	#include <linux/module.h>
5a0e3ad6	15	#include <linux/slab.h>
d00ed3cf DM	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk.h>
cec13c26 PR	19	#include <linux/of.h>
cec13c26 PR	20	#include <linux/of_device.h>
d00ed3cf	21
d00ed3cf DM	22	#define RTC_INPUT_CLK_32768HZ (0x00 << 5)
	23	#define RTC_INPUT_CLK_32000HZ (0x01 << 5)
	24	#define RTC_INPUT_CLK_38400HZ (0x02 << 5)
	25
	26	#define RTC_SW_BIT (1 << 0)
	27	#define RTC_ALM_BIT (1 << 2)
	28	#define RTC_1HZ_BIT (1 << 4)
	29	#define RTC_2HZ_BIT (1 << 7)
	30	#define RTC_SAM0_BIT (1 << 8)
	31	#define RTC_SAM1_BIT (1 << 9)
	32	#define RTC_SAM2_BIT (1 << 10)
	33	#define RTC_SAM3_BIT (1 << 11)
	34	#define RTC_SAM4_BIT (1 << 12)
	35	#define RTC_SAM5_BIT (1 << 13)
	36	#define RTC_SAM6_BIT (1 << 14)
	37	#define RTC_SAM7_BIT (1 << 15)
	38	#define PIT_ALL_ON (RTC_2HZ_BIT \| RTC_SAM0_BIT \| RTC_SAM1_BIT \| \
	39	RTC_SAM2_BIT \| RTC_SAM3_BIT \| RTC_SAM4_BIT \| \
	40	RTC_SAM5_BIT \| RTC_SAM6_BIT \| RTC_SAM7_BIT)
	41
	42	#define RTC_ENABLE_BIT (1 << 7)
	43
	44	#define MAX_PIE_NUM 9
	45	#define MAX_PIE_FREQ 512
d00ed3cf	46
d00ed3cf DM	47	#define MXC_RTC_TIME 0
	48	#define MXC_RTC_ALARM 1
	49
	50	#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
	51	#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
	52	#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
	53	#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
	54	#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
	55	#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
	56	#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
	57	#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
	58	#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
	59	#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
	60	#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
	61	#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
	62	#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
	63
bb1d34a2 SG	64	enum imx_rtc_type {
	65	IMX1_RTC,
	66	IMX21_RTC,
	67	};
	68
d00ed3cf DM	69	struct rtc_plat_data {
	70	struct rtc_device *rtc;
	71	void __iomem *ioaddr;
	72	int irq;
8f5fe778 PR	73	struct clk *clk_ref;
8f5fe778 PR	74	struct clk *clk_ipg;
d00ed3cf	75	struct rtc_time g_rtc_alarm;
bb1d34a2	76	enum imx_rtc_type devtype;
d00ed3cf DM	77	};
d00ed3cf DM	78
cd6ba00a	79	static const struct platform_device_id imx_rtc_devtype[] = {
bb1d34a2 SG	80	{
	81	.name = "imx1-rtc",
	82	.driver_data = IMX1_RTC,
	83	}, {
	84	.name = "imx21-rtc",
	85	.driver_data = IMX21_RTC,
	86	}, {
	87	/* sentinel */
	88	}
	89	};
	90	MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
	91
cec13c26 PR	92	#ifdef CONFIG_OF
	93	static const struct of_device_id imx_rtc_dt_ids[] = {
	94	{ .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
	95	{ .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
	96	{}
	97	};
	98	MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
	99	#endif
	100
bb1d34a2 SG	101	static inline int is_imx1_rtc(struct rtc_plat_data *data)
	102	{
	103	return data->devtype == IMX1_RTC;
	104	}
	105
d00ed3cf DM	106	/*
	107	* This function is used to obtain the RTC time or the alarm value in
	108	* second.
	109	*/
a015b8aa	110	static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
d00ed3cf DM	111	{
	112	struct platform_device *pdev = to_platform_device(dev);
	113	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	114	void __iomem *ioaddr = pdata->ioaddr;
	115	u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
	116
	117	switch (time_alarm) {
	118	case MXC_RTC_TIME:
	119	day = readw(ioaddr + RTC_DAYR);
	120	hr_min = readw(ioaddr + RTC_HOURMIN);
	121	sec = readw(ioaddr + RTC_SECOND);
	122	break;
	123	case MXC_RTC_ALARM:
	124	day = readw(ioaddr + RTC_DAYALARM);
	125	hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
	126	sec = readw(ioaddr + RTC_ALRM_SEC);
	127	break;
	128	}
	129
	130	hr = hr_min >> 8;
	131	min = hr_min & 0xff;
	132
a015b8aa	133	return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
d00ed3cf DM	134	}
	135
	136	/*
	137	* This function sets the RTC alarm value or the time value.
	138	*/
a015b8aa	139	static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
d00ed3cf	140	{
a015b8aa	141	u32 tod, day, hr, min, sec, temp;
d00ed3cf DM	142	struct platform_device *pdev = to_platform_device(dev);
	143	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	144	void __iomem *ioaddr = pdata->ioaddr;
	145
a015b8aa	146	day = div_s64_rem(time, 86400, &tod);
d00ed3cf DM	147
d00ed3cf DM	148	/* time is within a day now */
a015b8aa XP	149	hr = tod / 3600;
a015b8aa XP	150	tod -= hr * 3600;
d00ed3cf DM	151
d00ed3cf DM	152	/* time is within an hour now */
a015b8aa XP	153	min = tod / 60;
a015b8aa XP	154	sec = tod - min * 60;
d00ed3cf DM	155
	156	temp = (hr << 8) + min;
	157
	158	switch (time_alarm) {
	159	case MXC_RTC_TIME:
	160	writew(day, ioaddr + RTC_DAYR);
	161	writew(sec, ioaddr + RTC_SECOND);
	162	writew(temp, ioaddr + RTC_HOURMIN);
	163	break;
	164	case MXC_RTC_ALARM:
	165	writew(day, ioaddr + RTC_DAYALARM);
	166	writew(sec, ioaddr + RTC_ALRM_SEC);
	167	writew(temp, ioaddr + RTC_ALRM_HM);
	168	break;
	169	}
	170	}
	171
	172	/*
	173	* This function updates the RTC alarm registers and then clears all the
	174	* interrupt status bits.
	175	*/
482494a8	176	static void rtc_update_alarm(struct device dev, struct rtc_time alrm)
d00ed3cf	177	{
a015b8aa	178	time64_t time;
d00ed3cf DM	179	struct platform_device *pdev = to_platform_device(dev);
	180	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	181	void __iomem *ioaddr = pdata->ioaddr;
	182
a015b8aa	183	time = rtc_tm_to_time64(alrm);
d00ed3cf	184
d00ed3cf DM	185	/* clear all the interrupt status bits */
	186	writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
	187	set_alarm_or_time(dev, MXC_RTC_ALARM, time);
c92182ee YK	188	}
	189
	190	static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
	191	unsigned int enabled)
	192	{
	193	struct platform_device *pdev = to_platform_device(dev);
	194	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	195	void __iomem *ioaddr = pdata->ioaddr;
	196	u32 reg;
	197
	198	spin_lock_irq(&pdata->rtc->irq_lock);
	199	reg = readw(ioaddr + RTC_RTCIENR);
	200
	201	if (enabled)
	202	reg \|= bit;
	203	else
	204	reg &= ~bit;
	205
	206	writew(reg, ioaddr + RTC_RTCIENR);
	207	spin_unlock_irq(&pdata->rtc->irq_lock);
d00ed3cf DM	208	}
	209
	210	/* This function is the RTC interrupt service routine. */
	211	static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
	212	{
	213	struct platform_device *pdev = dev_id;
	214	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	215	void __iomem *ioaddr = pdata->ioaddr;
b59f6d1f	216	unsigned long flags;
d00ed3cf DM	217	u32 status;
	218	u32 events = 0;
	219
b59f6d1f	220	spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	221	status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
	222	/* clear interrupt sources */
	223	writew(status, ioaddr + RTC_RTCISR);
	224
d00ed3cf	225	/* update irq data & counter */
c92182ee	226	if (status & RTC_ALM_BIT) {
d00ed3cf	227	events \|= (RTC_AF \| RTC_IRQF);
c92182ee YK	228	/* RTC alarm should be one-shot */
	229	mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
	230	}
d00ed3cf	231
d00ed3cf DM	232	if (status & PIT_ALL_ON)
	233	events \|= (RTC_PF \| RTC_IRQF);
	234
d00ed3cf	235	rtc_update_irq(pdata->rtc, 1, events);
b59f6d1f	236	spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
d00ed3cf DM	237
	238	return IRQ_HANDLED;
	239	}
	240
	241	/*
	242	* Clear all interrupts and release the IRQ
	243	*/
	244	static void mxc_rtc_release(struct device *dev)
	245	{
	246	struct platform_device *pdev = to_platform_device(dev);
	247	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	248	void __iomem *ioaddr = pdata->ioaddr;
	249
	250	spin_lock_irq(&pdata->rtc->irq_lock);
	251
	252	/* Disable all rtc interrupts */
	253	writew(0, ioaddr + RTC_RTCIENR);
	254
	255	/* Clear all interrupt status */
	256	writew(0xffffffff, ioaddr + RTC_RTCISR);
	257
	258	spin_unlock_irq(&pdata->rtc->irq_lock);
	259	}
	260
d00ed3cf DM	261	static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	262	{
	263	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
	264	return 0;
	265	}
	266
d00ed3cf DM	267	/*
	268	* This function reads the current RTC time into tm in Gregorian date.
	269	*/
	270	static int mxc_rtc_read_time(struct device dev, struct rtc_time tm)
	271	{
a015b8aa	272	time64_t val;
d00ed3cf DM	273
	274	/* Avoid roll-over from reading the different registers */
	275	do {
	276	val = get_alarm_or_time(dev, MXC_RTC_TIME);
	277	} while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
	278
a015b8aa	279	rtc_time64_to_tm(val, tm);
d00ed3cf DM	280
	281	return 0;
	282	}
	283
	284	/*
	285	* This function sets the internal RTC time based on tm in Gregorian date.
	286	*/
933623c3	287	static int mxc_rtc_set_mmss(struct device *dev, time64_t time)
d00ed3cf	288	{
bb1d34a2 SG	289	struct platform_device *pdev = to_platform_device(dev);
	290	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	291
7287be1d YK	292	/*
	293	* TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only
	294	*/
bb1d34a2	295	if (is_imx1_rtc(pdata)) {
7287be1d YK	296	struct rtc_time tm;
7287be1d YK	297
933623c3	298	rtc_time64_to_tm(time, &tm);
7287be1d	299	tm.tm_year = 70;
933623c3	300	time = rtc_tm_to_time64(&tm);
7287be1d YK	301	}
7287be1d YK	302
d00ed3cf DM	303	/* Avoid roll-over from reading the different registers */
	304	do {
	305	set_alarm_or_time(dev, MXC_RTC_TIME, time);
	306	} while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
	307
	308	return 0;
	309	}
	310
	311	/*
	312	* This function reads the current alarm value into the passed in 'alrm'
	313	* argument. It updates the alrm's pending field value based on the whether
	314	* an alarm interrupt occurs or not.
	315	*/
	316	static int mxc_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	317	{
	318	struct platform_device *pdev = to_platform_device(dev);
	319	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	320	void __iomem *ioaddr = pdata->ioaddr;
	321
a015b8aa	322	rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
d00ed3cf DM	323	alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
	324
	325	return 0;
	326	}
	327
	328	/*
	329	* This function sets the RTC alarm based on passed in alrm.
	330	*/
	331	static int mxc_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	332	{
	333	struct platform_device *pdev = to_platform_device(dev);
	334	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
d00ed3cf	335
482494a8	336	rtc_update_alarm(dev, &alrm->time);
d00ed3cf DM	337
	338	memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
	339	mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
	340
	341	return 0;
	342	}
	343
	344	/* RTC layer */
8bc57e7f	345	static const struct rtc_class_ops mxc_rtc_ops = {
d00ed3cf DM	346	.release = mxc_rtc_release,
d00ed3cf DM	347	.read_time = mxc_rtc_read_time,
933623c3	348	.set_mmss64 = mxc_rtc_set_mmss,
d00ed3cf DM	349	.read_alarm = mxc_rtc_read_alarm,
	350	.set_alarm = mxc_rtc_set_alarm,
	351	.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
d00ed3cf DM	352	};
d00ed3cf DM	353
5a167f45	354	static int mxc_rtc_probe(struct platform_device *pdev)
d00ed3cf	355	{
d00ed3cf DM	356	struct resource *res;
	357	struct rtc_device *rtc;
	358	struct rtc_plat_data *pdata = NULL;
	359	u32 reg;
c783a29e VZ	360	unsigned long rate;
c783a29e VZ	361	int ret;
cec13c26	362	const struct of_device_id *of_id;
d00ed3cf	363
c783a29e	364	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
d00ed3cf DM	365	if (!pdata)
	366	return -ENOMEM;
	367
cec13c26 PR	368	of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
	369	if (of_id)
	370	pdata->devtype = (enum imx_rtc_type)of_id->data;
	371	else
	372	pdata->devtype = pdev->id_entry->driver_data;
bb1d34a2	373
7c1d69ee JL	374	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	375	pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	376	if (IS_ERR(pdata->ioaddr))
	377	return PTR_ERR(pdata->ioaddr);
d00ed3cf	378
8f5fe778 PR	379	pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	380	if (IS_ERR(pdata->clk_ipg)) {
	381	dev_err(&pdev->dev, "unable to get ipg clock!\n");
	382	return PTR_ERR(pdata->clk_ipg);
49908e73	383	}
d00ed3cf	384
8f5fe778	385	ret = clk_prepare_enable(pdata->clk_ipg);
1b3d2243 FE	386	if (ret)
	387	return ret;
	388
8f5fe778 PR	389	pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
	390	if (IS_ERR(pdata->clk_ref)) {
	391	dev_err(&pdev->dev, "unable to get ref clock!\n");
	392	ret = PTR_ERR(pdata->clk_ref);
	393	goto exit_put_clk_ipg;
	394	}
	395
	396	ret = clk_prepare_enable(pdata->clk_ref);
	397	if (ret)
	398	goto exit_put_clk_ipg;
	399
	400	rate = clk_get_rate(pdata->clk_ref);
d00ed3cf DM	401
	402	if (rate == 32768)
	403	reg = RTC_INPUT_CLK_32768HZ;
	404	else if (rate == 32000)
	405	reg = RTC_INPUT_CLK_32000HZ;
	406	else if (rate == 38400)
	407	reg = RTC_INPUT_CLK_38400HZ;
	408	else {
c783a29e	409	dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
d00ed3cf	410	ret = -EINVAL;
8f5fe778	411	goto exit_put_clk_ref;
d00ed3cf DM	412	}
	413
	414	reg \|= RTC_ENABLE_BIT;
	415	writew(reg, (pdata->ioaddr + RTC_RTCCTL));
	416	if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
	417	dev_err(&pdev->dev, "hardware module can't be enabled!\n");
	418	ret = -EIO;
8f5fe778	419	goto exit_put_clk_ref;
d00ed3cf DM	420	}
d00ed3cf DM	421
d00ed3cf DM	422	platform_set_drvdata(pdev, pdata);
	423
	424	/* Configure and enable the RTC */
	425	pdata->irq = platform_get_irq(pdev, 0);
	426
	427	if (pdata->irq >= 0 &&
c783a29e VZ	428	devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
c783a29e VZ	429	IRQF_SHARED, pdev->name, pdev) < 0) {
d00ed3cf DM	430	dev_warn(&pdev->dev, "interrupt not available.\n");
	431	pdata->irq = -1;
	432	}
	433
4a8282d0	434	if (pdata->irq >= 0)
c92182ee YK	435	device_init_wakeup(&pdev->dev, 1);
c92182ee YK	436
033ca3ad	437	rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
5f54c8a0 WS	438	THIS_MODULE);
	439	if (IS_ERR(rtc)) {
	440	ret = PTR_ERR(rtc);
8f5fe778	441	goto exit_put_clk_ref;
5f54c8a0 WS	442	}
	443
	444	pdata->rtc = rtc;
	445
d00ed3cf DM	446	return 0;
d00ed3cf DM	447
8f5fe778 PR	448	exit_put_clk_ref:
	449	clk_disable_unprepare(pdata->clk_ref);
	450	exit_put_clk_ipg:
	451	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf	452
d00ed3cf DM	453	return ret;
	454	}
	455
5a167f45	456	static int mxc_rtc_remove(struct platform_device *pdev)
d00ed3cf DM	457	{
	458	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
	459
8f5fe778 PR	460	clk_disable_unprepare(pdata->clk_ref);
8f5fe778 PR	461	clk_disable_unprepare(pdata->clk_ipg);
d00ed3cf DM	462
	463	return 0;
	464	}
	465
75634cc4	466	#ifdef CONFIG_PM_SLEEP
c92182ee YK	467	static int mxc_rtc_suspend(struct device *dev)
	468	{
	469	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	470
	471	if (device_may_wakeup(dev))
	472	enable_irq_wake(pdata->irq);
	473
	474	return 0;
	475	}
	476
	477	static int mxc_rtc_resume(struct device *dev)
	478	{
	479	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
	480
	481	if (device_may_wakeup(dev))
	482	disable_irq_wake(pdata->irq);
	483
	484	return 0;
	485	}
c92182ee YK	486	#endif
c92182ee YK	487
75634cc4 JH	488	static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
75634cc4 JH	489
d00ed3cf DM	490	static struct platform_driver mxc_rtc_driver = {
	491	.driver = {
	492	.name = "mxc_rtc",
cec13c26	493	.of_match_table = of_match_ptr(imx_rtc_dt_ids),
c92182ee	494	.pm = &mxc_rtc_pm_ops,
d00ed3cf	495	},
bb1d34a2	496	.id_table = imx_rtc_devtype,
be8b6d51	497	.probe = mxc_rtc_probe,
5a167f45	498	.remove = mxc_rtc_remove,
d00ed3cf DM	499	};
d00ed3cf DM	500
be8b6d51	501	module_platform_driver(mxc_rtc_driver)
d00ed3cf DM	502
	503	MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
	504	MODULE_DESCRIPTION("RTC driver for Freescale MXC");
	505	MODULE_LICENSE("GPL");
	506