Commit | Line | Data |
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d00ed3cf DM |
1 | /* |
2 | * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/io.h> | |
13 | #include <linux/rtc.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
d00ed3cf DM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/clk.h> | |
cec13c26 PR |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
d00ed3cf | 21 | |
d00ed3cf DM |
22 | #define RTC_INPUT_CLK_32768HZ (0x00 << 5) |
23 | #define RTC_INPUT_CLK_32000HZ (0x01 << 5) | |
24 | #define RTC_INPUT_CLK_38400HZ (0x02 << 5) | |
25 | ||
26 | #define RTC_SW_BIT (1 << 0) | |
27 | #define RTC_ALM_BIT (1 << 2) | |
28 | #define RTC_1HZ_BIT (1 << 4) | |
29 | #define RTC_2HZ_BIT (1 << 7) | |
30 | #define RTC_SAM0_BIT (1 << 8) | |
31 | #define RTC_SAM1_BIT (1 << 9) | |
32 | #define RTC_SAM2_BIT (1 << 10) | |
33 | #define RTC_SAM3_BIT (1 << 11) | |
34 | #define RTC_SAM4_BIT (1 << 12) | |
35 | #define RTC_SAM5_BIT (1 << 13) | |
36 | #define RTC_SAM6_BIT (1 << 14) | |
37 | #define RTC_SAM7_BIT (1 << 15) | |
38 | #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ | |
39 | RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ | |
40 | RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) | |
41 | ||
42 | #define RTC_ENABLE_BIT (1 << 7) | |
43 | ||
44 | #define MAX_PIE_NUM 9 | |
45 | #define MAX_PIE_FREQ 512 | |
46 | static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { | |
47 | { 2, RTC_2HZ_BIT }, | |
48 | { 4, RTC_SAM0_BIT }, | |
49 | { 8, RTC_SAM1_BIT }, | |
50 | { 16, RTC_SAM2_BIT }, | |
51 | { 32, RTC_SAM3_BIT }, | |
52 | { 64, RTC_SAM4_BIT }, | |
53 | { 128, RTC_SAM5_BIT }, | |
54 | { 256, RTC_SAM6_BIT }, | |
55 | { MAX_PIE_FREQ, RTC_SAM7_BIT }, | |
56 | }; | |
57 | ||
d00ed3cf DM |
58 | #define MXC_RTC_TIME 0 |
59 | #define MXC_RTC_ALARM 1 | |
60 | ||
61 | #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ | |
62 | #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ | |
63 | #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ | |
64 | #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ | |
65 | #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ | |
66 | #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ | |
67 | #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ | |
68 | #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ | |
69 | #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ | |
70 | #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ | |
71 | #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ | |
72 | #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ | |
73 | #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ | |
74 | ||
bb1d34a2 SG |
75 | enum imx_rtc_type { |
76 | IMX1_RTC, | |
77 | IMX21_RTC, | |
78 | }; | |
79 | ||
d00ed3cf DM |
80 | struct rtc_plat_data { |
81 | struct rtc_device *rtc; | |
82 | void __iomem *ioaddr; | |
83 | int irq; | |
8f5fe778 PR |
84 | struct clk *clk_ref; |
85 | struct clk *clk_ipg; | |
d00ed3cf | 86 | struct rtc_time g_rtc_alarm; |
bb1d34a2 | 87 | enum imx_rtc_type devtype; |
d00ed3cf DM |
88 | }; |
89 | ||
cd6ba00a | 90 | static const struct platform_device_id imx_rtc_devtype[] = { |
bb1d34a2 SG |
91 | { |
92 | .name = "imx1-rtc", | |
93 | .driver_data = IMX1_RTC, | |
94 | }, { | |
95 | .name = "imx21-rtc", | |
96 | .driver_data = IMX21_RTC, | |
97 | }, { | |
98 | /* sentinel */ | |
99 | } | |
100 | }; | |
101 | MODULE_DEVICE_TABLE(platform, imx_rtc_devtype); | |
102 | ||
cec13c26 PR |
103 | #ifdef CONFIG_OF |
104 | static const struct of_device_id imx_rtc_dt_ids[] = { | |
105 | { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC }, | |
106 | { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC }, | |
107 | {} | |
108 | }; | |
109 | MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids); | |
110 | #endif | |
111 | ||
bb1d34a2 SG |
112 | static inline int is_imx1_rtc(struct rtc_plat_data *data) |
113 | { | |
114 | return data->devtype == IMX1_RTC; | |
115 | } | |
116 | ||
d00ed3cf DM |
117 | /* |
118 | * This function is used to obtain the RTC time or the alarm value in | |
119 | * second. | |
120 | */ | |
a015b8aa | 121 | static time64_t get_alarm_or_time(struct device *dev, int time_alarm) |
d00ed3cf DM |
122 | { |
123 | struct platform_device *pdev = to_platform_device(dev); | |
124 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
125 | void __iomem *ioaddr = pdata->ioaddr; | |
126 | u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0; | |
127 | ||
128 | switch (time_alarm) { | |
129 | case MXC_RTC_TIME: | |
130 | day = readw(ioaddr + RTC_DAYR); | |
131 | hr_min = readw(ioaddr + RTC_HOURMIN); | |
132 | sec = readw(ioaddr + RTC_SECOND); | |
133 | break; | |
134 | case MXC_RTC_ALARM: | |
135 | day = readw(ioaddr + RTC_DAYALARM); | |
136 | hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; | |
137 | sec = readw(ioaddr + RTC_ALRM_SEC); | |
138 | break; | |
139 | } | |
140 | ||
141 | hr = hr_min >> 8; | |
142 | min = hr_min & 0xff; | |
143 | ||
a015b8aa | 144 | return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec; |
d00ed3cf DM |
145 | } |
146 | ||
147 | /* | |
148 | * This function sets the RTC alarm value or the time value. | |
149 | */ | |
a015b8aa | 150 | static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time) |
d00ed3cf | 151 | { |
a015b8aa | 152 | u32 tod, day, hr, min, sec, temp; |
d00ed3cf DM |
153 | struct platform_device *pdev = to_platform_device(dev); |
154 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
155 | void __iomem *ioaddr = pdata->ioaddr; | |
156 | ||
a015b8aa | 157 | day = div_s64_rem(time, 86400, &tod); |
d00ed3cf DM |
158 | |
159 | /* time is within a day now */ | |
a015b8aa XP |
160 | hr = tod / 3600; |
161 | tod -= hr * 3600; | |
d00ed3cf DM |
162 | |
163 | /* time is within an hour now */ | |
a015b8aa XP |
164 | min = tod / 60; |
165 | sec = tod - min * 60; | |
d00ed3cf DM |
166 | |
167 | temp = (hr << 8) + min; | |
168 | ||
169 | switch (time_alarm) { | |
170 | case MXC_RTC_TIME: | |
171 | writew(day, ioaddr + RTC_DAYR); | |
172 | writew(sec, ioaddr + RTC_SECOND); | |
173 | writew(temp, ioaddr + RTC_HOURMIN); | |
174 | break; | |
175 | case MXC_RTC_ALARM: | |
176 | writew(day, ioaddr + RTC_DAYALARM); | |
177 | writew(sec, ioaddr + RTC_ALRM_SEC); | |
178 | writew(temp, ioaddr + RTC_ALRM_HM); | |
179 | break; | |
180 | } | |
181 | } | |
182 | ||
183 | /* | |
184 | * This function updates the RTC alarm registers and then clears all the | |
185 | * interrupt status bits. | |
186 | */ | |
482494a8 | 187 | static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm) |
d00ed3cf | 188 | { |
a015b8aa | 189 | time64_t time; |
d00ed3cf DM |
190 | struct platform_device *pdev = to_platform_device(dev); |
191 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
192 | void __iomem *ioaddr = pdata->ioaddr; | |
193 | ||
a015b8aa | 194 | time = rtc_tm_to_time64(alrm); |
d00ed3cf | 195 | |
d00ed3cf DM |
196 | /* clear all the interrupt status bits */ |
197 | writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); | |
198 | set_alarm_or_time(dev, MXC_RTC_ALARM, time); | |
c92182ee YK |
199 | } |
200 | ||
201 | static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit, | |
202 | unsigned int enabled) | |
203 | { | |
204 | struct platform_device *pdev = to_platform_device(dev); | |
205 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
206 | void __iomem *ioaddr = pdata->ioaddr; | |
207 | u32 reg; | |
208 | ||
209 | spin_lock_irq(&pdata->rtc->irq_lock); | |
210 | reg = readw(ioaddr + RTC_RTCIENR); | |
211 | ||
212 | if (enabled) | |
213 | reg |= bit; | |
214 | else | |
215 | reg &= ~bit; | |
216 | ||
217 | writew(reg, ioaddr + RTC_RTCIENR); | |
218 | spin_unlock_irq(&pdata->rtc->irq_lock); | |
d00ed3cf DM |
219 | } |
220 | ||
221 | /* This function is the RTC interrupt service routine. */ | |
222 | static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) | |
223 | { | |
224 | struct platform_device *pdev = dev_id; | |
225 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
226 | void __iomem *ioaddr = pdata->ioaddr; | |
b59f6d1f | 227 | unsigned long flags; |
d00ed3cf DM |
228 | u32 status; |
229 | u32 events = 0; | |
230 | ||
b59f6d1f | 231 | spin_lock_irqsave(&pdata->rtc->irq_lock, flags); |
d00ed3cf DM |
232 | status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); |
233 | /* clear interrupt sources */ | |
234 | writew(status, ioaddr + RTC_RTCISR); | |
235 | ||
d00ed3cf | 236 | /* update irq data & counter */ |
c92182ee | 237 | if (status & RTC_ALM_BIT) { |
d00ed3cf | 238 | events |= (RTC_AF | RTC_IRQF); |
c92182ee YK |
239 | /* RTC alarm should be one-shot */ |
240 | mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0); | |
241 | } | |
d00ed3cf | 242 | |
d00ed3cf DM |
243 | if (status & PIT_ALL_ON) |
244 | events |= (RTC_PF | RTC_IRQF); | |
245 | ||
d00ed3cf | 246 | rtc_update_irq(pdata->rtc, 1, events); |
b59f6d1f | 247 | spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags); |
d00ed3cf DM |
248 | |
249 | return IRQ_HANDLED; | |
250 | } | |
251 | ||
252 | /* | |
253 | * Clear all interrupts and release the IRQ | |
254 | */ | |
255 | static void mxc_rtc_release(struct device *dev) | |
256 | { | |
257 | struct platform_device *pdev = to_platform_device(dev); | |
258 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
259 | void __iomem *ioaddr = pdata->ioaddr; | |
260 | ||
261 | spin_lock_irq(&pdata->rtc->irq_lock); | |
262 | ||
263 | /* Disable all rtc interrupts */ | |
264 | writew(0, ioaddr + RTC_RTCIENR); | |
265 | ||
266 | /* Clear all interrupt status */ | |
267 | writew(0xffffffff, ioaddr + RTC_RTCISR); | |
268 | ||
269 | spin_unlock_irq(&pdata->rtc->irq_lock); | |
270 | } | |
271 | ||
d00ed3cf DM |
272 | static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
273 | { | |
274 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled); | |
275 | return 0; | |
276 | } | |
277 | ||
d00ed3cf DM |
278 | /* |
279 | * This function reads the current RTC time into tm in Gregorian date. | |
280 | */ | |
281 | static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
282 | { | |
a015b8aa | 283 | time64_t val; |
d00ed3cf DM |
284 | |
285 | /* Avoid roll-over from reading the different registers */ | |
286 | do { | |
287 | val = get_alarm_or_time(dev, MXC_RTC_TIME); | |
288 | } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
289 | ||
a015b8aa | 290 | rtc_time64_to_tm(val, tm); |
d00ed3cf DM |
291 | |
292 | return 0; | |
293 | } | |
294 | ||
295 | /* | |
296 | * This function sets the internal RTC time based on tm in Gregorian date. | |
297 | */ | |
933623c3 | 298 | static int mxc_rtc_set_mmss(struct device *dev, time64_t time) |
d00ed3cf | 299 | { |
bb1d34a2 SG |
300 | struct platform_device *pdev = to_platform_device(dev); |
301 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
302 | ||
7287be1d YK |
303 | /* |
304 | * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only | |
305 | */ | |
bb1d34a2 | 306 | if (is_imx1_rtc(pdata)) { |
7287be1d YK |
307 | struct rtc_time tm; |
308 | ||
933623c3 | 309 | rtc_time64_to_tm(time, &tm); |
7287be1d | 310 | tm.tm_year = 70; |
933623c3 | 311 | time = rtc_tm_to_time64(&tm); |
7287be1d YK |
312 | } |
313 | ||
d00ed3cf DM |
314 | /* Avoid roll-over from reading the different registers */ |
315 | do { | |
316 | set_alarm_or_time(dev, MXC_RTC_TIME, time); | |
317 | } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | /* | |
323 | * This function reads the current alarm value into the passed in 'alrm' | |
324 | * argument. It updates the alrm's pending field value based on the whether | |
325 | * an alarm interrupt occurs or not. | |
326 | */ | |
327 | static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
328 | { | |
329 | struct platform_device *pdev = to_platform_device(dev); | |
330 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
331 | void __iomem *ioaddr = pdata->ioaddr; | |
332 | ||
a015b8aa | 333 | rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); |
d00ed3cf DM |
334 | alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | /* | |
340 | * This function sets the RTC alarm based on passed in alrm. | |
341 | */ | |
342 | static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
343 | { | |
344 | struct platform_device *pdev = to_platform_device(dev); | |
345 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
d00ed3cf | 346 | |
482494a8 | 347 | rtc_update_alarm(dev, &alrm->time); |
d00ed3cf DM |
348 | |
349 | memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); | |
350 | mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled); | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | /* RTC layer */ | |
356 | static struct rtc_class_ops mxc_rtc_ops = { | |
357 | .release = mxc_rtc_release, | |
358 | .read_time = mxc_rtc_read_time, | |
933623c3 | 359 | .set_mmss64 = mxc_rtc_set_mmss, |
d00ed3cf DM |
360 | .read_alarm = mxc_rtc_read_alarm, |
361 | .set_alarm = mxc_rtc_set_alarm, | |
362 | .alarm_irq_enable = mxc_rtc_alarm_irq_enable, | |
d00ed3cf DM |
363 | }; |
364 | ||
5a167f45 | 365 | static int mxc_rtc_probe(struct platform_device *pdev) |
d00ed3cf | 366 | { |
d00ed3cf DM |
367 | struct resource *res; |
368 | struct rtc_device *rtc; | |
369 | struct rtc_plat_data *pdata = NULL; | |
370 | u32 reg; | |
c783a29e VZ |
371 | unsigned long rate; |
372 | int ret; | |
cec13c26 | 373 | const struct of_device_id *of_id; |
d00ed3cf | 374 | |
c783a29e | 375 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
d00ed3cf DM |
376 | if (!pdata) |
377 | return -ENOMEM; | |
378 | ||
cec13c26 PR |
379 | of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev); |
380 | if (of_id) | |
381 | pdata->devtype = (enum imx_rtc_type)of_id->data; | |
382 | else | |
383 | pdata->devtype = pdev->id_entry->driver_data; | |
bb1d34a2 | 384 | |
7c1d69ee JL |
385 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
386 | pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); | |
387 | if (IS_ERR(pdata->ioaddr)) | |
388 | return PTR_ERR(pdata->ioaddr); | |
d00ed3cf | 389 | |
8f5fe778 PR |
390 | pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
391 | if (IS_ERR(pdata->clk_ipg)) { | |
392 | dev_err(&pdev->dev, "unable to get ipg clock!\n"); | |
393 | return PTR_ERR(pdata->clk_ipg); | |
49908e73 | 394 | } |
d00ed3cf | 395 | |
8f5fe778 | 396 | ret = clk_prepare_enable(pdata->clk_ipg); |
1b3d2243 FE |
397 | if (ret) |
398 | return ret; | |
399 | ||
8f5fe778 PR |
400 | pdata->clk_ref = devm_clk_get(&pdev->dev, "ref"); |
401 | if (IS_ERR(pdata->clk_ref)) { | |
402 | dev_err(&pdev->dev, "unable to get ref clock!\n"); | |
403 | ret = PTR_ERR(pdata->clk_ref); | |
404 | goto exit_put_clk_ipg; | |
405 | } | |
406 | ||
407 | ret = clk_prepare_enable(pdata->clk_ref); | |
408 | if (ret) | |
409 | goto exit_put_clk_ipg; | |
410 | ||
411 | rate = clk_get_rate(pdata->clk_ref); | |
d00ed3cf DM |
412 | |
413 | if (rate == 32768) | |
414 | reg = RTC_INPUT_CLK_32768HZ; | |
415 | else if (rate == 32000) | |
416 | reg = RTC_INPUT_CLK_32000HZ; | |
417 | else if (rate == 38400) | |
418 | reg = RTC_INPUT_CLK_38400HZ; | |
419 | else { | |
c783a29e | 420 | dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate); |
d00ed3cf | 421 | ret = -EINVAL; |
8f5fe778 | 422 | goto exit_put_clk_ref; |
d00ed3cf DM |
423 | } |
424 | ||
425 | reg |= RTC_ENABLE_BIT; | |
426 | writew(reg, (pdata->ioaddr + RTC_RTCCTL)); | |
427 | if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { | |
428 | dev_err(&pdev->dev, "hardware module can't be enabled!\n"); | |
429 | ret = -EIO; | |
8f5fe778 | 430 | goto exit_put_clk_ref; |
d00ed3cf DM |
431 | } |
432 | ||
d00ed3cf DM |
433 | platform_set_drvdata(pdev, pdata); |
434 | ||
435 | /* Configure and enable the RTC */ | |
436 | pdata->irq = platform_get_irq(pdev, 0); | |
437 | ||
438 | if (pdata->irq >= 0 && | |
c783a29e VZ |
439 | devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, |
440 | IRQF_SHARED, pdev->name, pdev) < 0) { | |
d00ed3cf DM |
441 | dev_warn(&pdev->dev, "interrupt not available.\n"); |
442 | pdata->irq = -1; | |
443 | } | |
444 | ||
4a8282d0 | 445 | if (pdata->irq >= 0) |
c92182ee YK |
446 | device_init_wakeup(&pdev->dev, 1); |
447 | ||
033ca3ad | 448 | rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops, |
5f54c8a0 WS |
449 | THIS_MODULE); |
450 | if (IS_ERR(rtc)) { | |
451 | ret = PTR_ERR(rtc); | |
8f5fe778 | 452 | goto exit_put_clk_ref; |
5f54c8a0 WS |
453 | } |
454 | ||
455 | pdata->rtc = rtc; | |
456 | ||
d00ed3cf DM |
457 | return 0; |
458 | ||
8f5fe778 PR |
459 | exit_put_clk_ref: |
460 | clk_disable_unprepare(pdata->clk_ref); | |
461 | exit_put_clk_ipg: | |
462 | clk_disable_unprepare(pdata->clk_ipg); | |
d00ed3cf | 463 | |
d00ed3cf DM |
464 | return ret; |
465 | } | |
466 | ||
5a167f45 | 467 | static int mxc_rtc_remove(struct platform_device *pdev) |
d00ed3cf DM |
468 | { |
469 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
470 | ||
8f5fe778 PR |
471 | clk_disable_unprepare(pdata->clk_ref); |
472 | clk_disable_unprepare(pdata->clk_ipg); | |
d00ed3cf DM |
473 | |
474 | return 0; | |
475 | } | |
476 | ||
75634cc4 | 477 | #ifdef CONFIG_PM_SLEEP |
c92182ee YK |
478 | static int mxc_rtc_suspend(struct device *dev) |
479 | { | |
480 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); | |
481 | ||
482 | if (device_may_wakeup(dev)) | |
483 | enable_irq_wake(pdata->irq); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int mxc_rtc_resume(struct device *dev) | |
489 | { | |
490 | struct rtc_plat_data *pdata = dev_get_drvdata(dev); | |
491 | ||
492 | if (device_may_wakeup(dev)) | |
493 | disable_irq_wake(pdata->irq); | |
494 | ||
495 | return 0; | |
496 | } | |
c92182ee YK |
497 | #endif |
498 | ||
75634cc4 JH |
499 | static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume); |
500 | ||
d00ed3cf DM |
501 | static struct platform_driver mxc_rtc_driver = { |
502 | .driver = { | |
503 | .name = "mxc_rtc", | |
cec13c26 | 504 | .of_match_table = of_match_ptr(imx_rtc_dt_ids), |
c92182ee | 505 | .pm = &mxc_rtc_pm_ops, |
d00ed3cf | 506 | }, |
bb1d34a2 | 507 | .id_table = imx_rtc_devtype, |
be8b6d51 | 508 | .probe = mxc_rtc_probe, |
5a167f45 | 509 | .remove = mxc_rtc_remove, |
d00ed3cf DM |
510 | }; |
511 | ||
be8b6d51 | 512 | module_platform_driver(mxc_rtc_driver) |
d00ed3cf DM |
513 | |
514 | MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); | |
515 | MODULE_DESCRIPTION("RTC driver for Freescale MXC"); | |
516 | MODULE_LICENSE("GPL"); | |
517 |