[linux-2.6-block.git] / drivers / rtc / rtc-mcp795.c

/*
 * SPI Driver for Microchip MCP795 RTC
 *
 * Copyright (C) Josef Gajdusek <atx@atx.name>
 *
 * based on other Linux RTC drivers
 *
 * Device datasheet:
 * http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/printk.h>
#include <linux/spi/spi.h>
#include <linux/rtc.h>
#include <linux/of.h>
#include <linux/bcd.h>
#include <linux/delay.h>

/* MCP795 Instructions, see datasheet table 3-1 */
#define MCP795_EEREAD	0x03
#define MCP795_EEWRITE	0x02
#define MCP795_EEWRDI	0x04
#define MCP795_EEWREN	0x06
#define MCP795_SRREAD	0x05
#define MCP795_SRWRITE	0x01
#define MCP795_READ	0x13
#define MCP795_WRITE	0x12
#define MCP795_UNLOCK	0x14
#define MCP795_IDWRITE	0x32
#define MCP795_IDREAD	0x33
#define MCP795_CLRWDT	0x44
#define MCP795_CLRRAM	0x54

/* MCP795 RTCC registers, see datasheet table 4-1 */
#define MCP795_REG_SECONDS	0x01
#define MCP795_REG_DAY		0x04
#define MCP795_REG_MONTH	0x06
#define MCP795_REG_CONTROL	0x08
#define MCP795_REG_ALM0_SECONDS	0x0C
#define MCP795_REG_ALM0_DAY	0x0F

#define MCP795_ST_BIT		BIT(7)
#define MCP795_24_BIT		BIT(6)
#define MCP795_LP_BIT		BIT(5)
#define MCP795_EXTOSC_BIT	BIT(3)
#define MCP795_OSCON_BIT	BIT(5)
#define MCP795_ALM0_BIT		BIT(4)
#define MCP795_ALM1_BIT		BIT(5)
#define MCP795_ALM0IF_BIT	BIT(3)
#define MCP795_ALM0C0_BIT	BIT(4)
#define MCP795_ALM0C1_BIT	BIT(5)
#define MCP795_ALM0C2_BIT	BIT(6)

#define SEC_PER_DAY		(24 * 60 * 60)

static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;
	u8 tx[2];

	tx[0] = MCP795_READ;
	tx[1] = addr;
	ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);

	if (ret)
		dev_err(dev, "Failed reading %d bytes from address %x.\n",
					count, addr);

	return ret;
}

static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;
	u8 tx[257];

	tx[0] = MCP795_WRITE;
	tx[1] = addr;
	memcpy(&tx[2], data, count);

	ret = spi_write(spi, tx, 2 + count);

	if (ret)
		dev_err(dev, "Failed to write %d bytes to address %x.\n",
					count, addr);

	return ret;
}

static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
{
	int ret;
	u8 tmp;

	ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
	if (ret)
		return ret;

	if ((tmp & mask) != state) {
		tmp = (tmp & ~mask) | state;
		ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
	}

	return ret;
}

static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
{
	int retries = 5;
	int ret;
	u8 data;

	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
	if (ret)
		return ret;
	ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
	if (ret)
		return ret;
	*extosc = !!(data & MCP795_EXTOSC_BIT);
	ret = mcp795_rtcc_set_bits(
				dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
	if (ret)
		return ret;
	/* wait for the OSCON bit to clear */
	do {
		usleep_range(700, 800);
		ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
		if (ret)
			break;
		if (!(data & MCP795_OSCON_BIT))
			break;

	} while (--retries);

	return !retries ? -EIO : ret;
}

static int mcp795_start_oscillator(struct device *dev, bool *extosc)
{
	if (extosc) {
		u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
		int ret;

		ret = mcp795_rtcc_set_bits(
			dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
		if (ret)
			return ret;
	}
	return mcp795_rtcc_set_bits(
			dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
}

/* Enable or disable Alarm 0 in RTC */
static int mcp795_update_alarm(struct device *dev, bool enable)
{
	int ret;

	dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");

	if (enable) {
		/* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
					MCP795_ALM0IF_BIT, 0);
		if (ret)
			return ret;
		/* enable alarm 0 */
		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
					MCP795_ALM0_BIT, MCP795_ALM0_BIT);
	} else {
		/* disable alarm 0 and alarm 1 */
		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
					MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
	}
	return ret;
}

static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
{
	int ret;
	u8 data[7];
	bool extosc;

	/* Stop RTC and store current value of EXTOSC bit */
	ret = mcp795_stop_oscillator(dev, &extosc);
	if (ret)
		return ret;

	/* Read first, so we can leave config bits untouched */
	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));

	if (ret)
		return ret;

	data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
	data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
	data[2] = bin2bcd(tim->tm_hour);
	data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
	data[4] = bin2bcd(tim->tm_mday);
	data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);

	if (tim->tm_year > 100)
		tim->tm_year -= 100;

	data[6] = bin2bcd(tim->tm_year);

	/* Always write the date and month using a separate Write command.
	 * This is a workaround for a know silicon issue that some combinations
	 * of date and month values may result in the date being reset to 1.
	 */
	ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
	if (ret)
		return ret;

	ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
	if (ret)
		return ret;

	/* Start back RTC and restore previous value of EXTOSC bit.
	 * There is no need to clear EXTOSC bit when the previous value was 0
	 * because it was already cleared when stopping the RTC oscillator.
	 */
	ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
	if (ret)
		return ret;

	dev_dbg(dev, "Set mcp795: %ptR\n", tim);

	return 0;
}

static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
{
	int ret;
	u8 data[7];

	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));

	if (ret)
		return ret;

	tim->tm_sec	= bcd2bin(data[0] & 0x7F);
	tim->tm_min	= bcd2bin(data[1] & 0x7F);
	tim->tm_hour	= bcd2bin(data[2] & 0x3F);
	tim->tm_wday	= bcd2bin(data[3] & 0x07) - 1;
	tim->tm_mday	= bcd2bin(data[4] & 0x3F);
	tim->tm_mon	= bcd2bin(data[5] & 0x1F) - 1;
	tim->tm_year	= bcd2bin(data[6]) + 100; /* Assume we are in 20xx */

	dev_dbg(dev, "Read from mcp795: %ptR\n", tim);

	return 0;
}

static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct rtc_time now_tm;
	time64_t now;
	time64_t later;
	u8 tmp[6];
	int ret;

	/* Read current time from RTC hardware */
	ret = mcp795_read_time(dev, &now_tm);
	if (ret)
		return ret;
	/* Get the number of seconds since 1970 */
	now = rtc_tm_to_time64(&now_tm);
	later = rtc_tm_to_time64(&alm->time);
	if (later <= now)
		return -EINVAL;
	/* make sure alarm fires within the next one year */
	if ((later - now) >=
		(SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
		return -EDOM;
	/* disable alarm */
	ret = mcp795_update_alarm(dev, false);
	if (ret)
		return ret;
	/* Read registers, so we can leave configuration bits untouched */
	ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	if (ret)
		return ret;

	alm->time.tm_year	= -1;
	alm->time.tm_isdst	= -1;
	alm->time.tm_yday	= -1;

	tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
	tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
	tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
	tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
	/* set alarm match: seconds, minutes, hour, day, date and month */
	tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
	tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
	tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);

	ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	if (ret)
		return ret;

	/* enable alarm if requested */
	if (alm->enabled) {
		ret = mcp795_update_alarm(dev, true);
		if (ret)
			return ret;
		dev_dbg(dev, "Alarm IRQ armed\n");
	}
	dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
		&alm->time, alm->time.tm_wday, &alm->time);
	return 0;
}

static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	u8 data[6];
	int ret;

	ret = mcp795_rtcc_read(
			dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
	if (ret)
		return ret;

	alm->time.tm_sec	= bcd2bin(data[0] & 0x7F);
	alm->time.tm_min	= bcd2bin(data[1] & 0x7F);
	alm->time.tm_hour	= bcd2bin(data[2] & 0x1F);
	alm->time.tm_wday	= bcd2bin(data[3] & 0x07) - 1;
	alm->time.tm_mday	= bcd2bin(data[4] & 0x3F);
	alm->time.tm_mon	= bcd2bin(data[5] & 0x1F) - 1;
	alm->time.tm_year	= -1;
	alm->time.tm_isdst	= -1;
	alm->time.tm_yday	= -1;

	dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
		&alm->time, alm->time.tm_wday, &alm->time);
	return 0;
}

static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	return mcp795_update_alarm(dev, !!enabled);
}

static irqreturn_t mcp795_irq(int irq, void *data)
{
	struct spi_device *spi = data;
	struct rtc_device *rtc = spi_get_drvdata(spi);
	struct mutex *lock = &rtc->ops_lock;
	int ret;

	mutex_lock(lock);

	/* Disable alarm.
	 * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
	 * because it is done every time when alarm is enabled.
	 */
	ret = mcp795_update_alarm(&spi->dev, false);
	if (ret)
		dev_err(&spi->dev,
			"Failed to disable alarm in IRQ (ret=%d)\n", ret);
	rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);

	mutex_unlock(lock);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops mcp795_rtc_ops = {
		.read_time = mcp795_read_time,
		.set_time = mcp795_set_time,
		.read_alarm = mcp795_read_alarm,
		.set_alarm = mcp795_set_alarm,
		.alarm_irq_enable = mcp795_alarm_irq_enable
};

static int mcp795_probe(struct spi_device *spi)
{
	struct rtc_device *rtc;
	int ret;

	spi->mode = SPI_MODE_0;
	spi->bits_per_word = 8;
	ret = spi_setup(spi);
	if (ret) {
		dev_err(&spi->dev, "Unable to setup SPI\n");
		return ret;
	}

	/* Start the oscillator but don't set the value of EXTOSC bit */
	mcp795_start_oscillator(&spi->dev, NULL);
	/* Clear the 12 hour mode flag*/
	mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);

	rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
					&mcp795_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	spi_set_drvdata(spi, rtc);

	if (spi->irq > 0) {
		dev_dbg(&spi->dev, "Alarm support enabled\n");

		/* Clear any pending alarm (ALM0IF bit) before requesting
		 * the interrupt.
		 */
		mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
					MCP795_ALM0IF_BIT, 0);
		ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
				mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				dev_name(&rtc->dev), spi);
		if (ret)
			dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
						spi->irq, ret);
		else
			device_init_wakeup(&spi->dev, true);
	}
	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id mcp795_of_match[] = {
	{ .compatible = "maxim,mcp795" },
	{ }
};
MODULE_DEVICE_TABLE(of, mcp795_of_match);
#endif

static struct spi_driver mcp795_driver = {
		.driver = {
				.name = "rtc-mcp795",
				.of_match_table = of_match_ptr(mcp795_of_match),
		},
		.probe = mcp795_probe,
};

module_spi_driver(mcp795_driver);

MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:mcp795");
Commit	Line	Data
1fcbe42c JG	1	/*
	2	* SPI Driver for Microchip MCP795 RTC
	3	*
	4	* Copyright (C) Josef Gajdusek <atx@atx.name>
	5	*
	6	* based on other Linux RTC drivers
	7	*
	8	* Device datasheet:
	9	* http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*
d3e59259	15	*/
1fcbe42c JG	16
	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/printk.h>
	21	#include <linux/spi/spi.h>
	22	#include <linux/rtc.h>
7f8a5892	23	#include <linux/of.h>
bcf18d88	24	#include <linux/bcd.h>
43d0b10f	25	#include <linux/delay.h>
1fcbe42c JG	26
	27	/* MCP795 Instructions, see datasheet table 3-1 */
	28	#define MCP795_EEREAD 0x03
	29	#define MCP795_EEWRITE 0x02
	30	#define MCP795_EEWRDI 0x04
	31	#define MCP795_EEWREN 0x06
	32	#define MCP795_SRREAD 0x05
	33	#define MCP795_SRWRITE 0x01
d3e59259	34	#define MCP795_READ 0x13
1fcbe42c JG	35	#define MCP795_WRITE 0x12
	36	#define MCP795_UNLOCK 0x14
	37	#define MCP795_IDWRITE 0x32
	38	#define MCP795_IDREAD 0x33
	39	#define MCP795_CLRWDT 0x44
	40	#define MCP795_CLRRAM 0x54
	41
43d0b10f EB	42	/* MCP795 RTCC registers, see datasheet table 4-1 */
	43	#define MCP795_REG_SECONDS 0x01
	44	#define MCP795_REG_DAY 0x04
	45	#define MCP795_REG_MONTH 0x06
	46	#define MCP795_REG_CONTROL 0x08
644d4c36 EB	47	#define MCP795_REG_ALM0_SECONDS 0x0C
644d4c36 EB	48	#define MCP795_REG_ALM0_DAY 0x0F
43d0b10f	49
d3e59259 EB	50	#define MCP795_ST_BIT BIT(7)
	51	#define MCP795_24_BIT BIT(6)
	52	#define MCP795_LP_BIT BIT(5)
43d0b10f EB	53	#define MCP795_EXTOSC_BIT BIT(3)
43d0b10f EB	54	#define MCP795_OSCON_BIT BIT(5)
644d4c36 EB	55	#define MCP795_ALM0_BIT BIT(4)
	56	#define MCP795_ALM1_BIT BIT(5)
	57	#define MCP795_ALM0IF_BIT BIT(3)
	58	#define MCP795_ALM0C0_BIT BIT(4)
	59	#define MCP795_ALM0C1_BIT BIT(5)
	60	#define MCP795_ALM0C2_BIT BIT(6)
	61
	62	#define SEC_PER_DAY (24 * 60 * 60)
1fcbe42c JG	63
	64	static int mcp795_rtcc_read(struct device dev, u8 addr, u8 buf, u8 count)
	65	{
	66	struct spi_device *spi = to_spi_device(dev);
	67	int ret;
	68	u8 tx[2];
	69
	70	tx[0] = MCP795_READ;
	71	tx[1] = addr;
	72	ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
	73
	74	if (ret)
	75	dev_err(dev, "Failed reading %d bytes from address %x.\n",
	76	count, addr);
	77
	78	return ret;
	79	}
	80
	81	static int mcp795_rtcc_write(struct device dev, u8 addr, u8 data, u8 count)
	82	{
	83	struct spi_device *spi = to_spi_device(dev);
	84	int ret;
fed9b186	85	u8 tx[257];
1fcbe42c JG	86
	87	tx[0] = MCP795_WRITE;
	88	tx[1] = addr;
	89	memcpy(&tx[2], data, count);
	90
	91	ret = spi_write(spi, tx, 2 + count);
	92
	93	if (ret)
	94	dev_err(dev, "Failed to write %d bytes to address %x.\n",
	95	count, addr);
	96
	97	return ret;
	98	}
	99
	100	static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
	101	{
	102	int ret;
	103	u8 tmp;
	104
	105	ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
	106	if (ret)
	107	return ret;
	108
	109	if ((tmp & mask) != state) {
	110	tmp = (tmp & ~mask) \| state;
	111	ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
	112	}
	113
	114	return ret;
	115	}
	116
43d0b10f EB	117	static int mcp795_stop_oscillator(struct device dev, bool extosc)
	118	{
	119	int retries = 5;
	120	int ret;
	121	u8 data;
	122
	123	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
	124	if (ret)
	125	return ret;
	126	ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
	127	if (ret)
	128	return ret;
	129	*extosc = !!(data & MCP795_EXTOSC_BIT);
	130	ret = mcp795_rtcc_set_bits(
	131	dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
	132	if (ret)
	133	return ret;
	134	/* wait for the OSCON bit to clear */
	135	do {
	136	usleep_range(700, 800);
	137	ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
	138	if (ret)
	139	break;
	140	if (!(data & MCP795_OSCON_BIT))
	141	break;
	142
	143	} while (--retries);
	144
	145	return !retries ? -EIO : ret;
	146	}
	147
	148	static int mcp795_start_oscillator(struct device dev, bool extosc)
	149	{
	150	if (extosc) {
	151	u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
	152	int ret;
	153
	154	ret = mcp795_rtcc_set_bits(
	155	dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
	156	if (ret)
	157	return ret;
	158	}
	159	return mcp795_rtcc_set_bits(
	160	dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
	161	}
	162
644d4c36 EB	163	/* Enable or disable Alarm 0 in RTC */
	164	static int mcp795_update_alarm(struct device *dev, bool enable)
	165	{
	166	int ret;
	167
	168	dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
	169
	170	if (enable) {
	171	/* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
	172	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
	173	MCP795_ALM0IF_BIT, 0);
	174	if (ret)
	175	return ret;
	176	/* enable alarm 0 */
	177	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
	178	MCP795_ALM0_BIT, MCP795_ALM0_BIT);
	179	} else {
	180	/* disable alarm 0 and alarm 1 */
	181	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
	182	MCP795_ALM0_BIT \| MCP795_ALM1_BIT, 0);
	183	}
	184	return ret;
	185	}
	186
1fcbe42c JG	187	static int mcp795_set_time(struct device dev, struct rtc_time tim)
	188	{
	189	int ret;
	190	u8 data[7];
43d0b10f EB	191	bool extosc;
	192
	193	/* Stop RTC and store current value of EXTOSC bit */
	194	ret = mcp795_stop_oscillator(dev, &extosc);
	195	if (ret)
	196	return ret;
1fcbe42c JG	197
1fcbe42c JG	198	/* Read first, so we can leave config bits untouched */
43d0b10f	199	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
1fcbe42c JG	200
	201	if (ret)
	202	return ret;
	203
bcf18d88 EB	204	data[0] = (data[0] & 0x80) \| bin2bcd(tim->tm_sec);
	205	data[1] = (data[1] & 0x80) \| bin2bcd(tim->tm_min);
	206	data[2] = bin2bcd(tim->tm_hour);
72877b51	207	data[3] = (data[3] & 0xF8) \| bin2bcd(tim->tm_wday + 1);
bcf18d88	208	data[4] = bin2bcd(tim->tm_mday);
26eeefd5	209	data[5] = (data[5] & MCP795_LP_BIT) \| bin2bcd(tim->tm_mon + 1);
1fcbe42c JG	210
	211	if (tim->tm_year > 100)
	212	tim->tm_year -= 100;
	213
bcf18d88	214	data[6] = bin2bcd(tim->tm_year);
1fcbe42c	215
43d0b10f EB	216	/* Always write the date and month using a separate Write command.
	217	* This is a workaround for a know silicon issue that some combinations
	218	* of date and month values may result in the date being reset to 1.
	219	*/
	220	ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
	221	if (ret)
	222	return ret;
	223
	224	ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
	225	if (ret)
	226	return ret;
1fcbe42c	227
43d0b10f EB	228	/* Start back RTC and restore previous value of EXTOSC bit.
	229	* There is no need to clear EXTOSC bit when the previous value was 0
	230	* because it was already cleared when stopping the RTC oscillator.
	231	*/
	232	ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
1fcbe42c JG	233	if (ret)
	234	return ret;
	235
14813760	236	dev_dbg(dev, "Set mcp795: %ptR\n", tim);
1fcbe42c JG	237
	238	return 0;
	239	}
	240
	241	static int mcp795_read_time(struct device dev, struct rtc_time tim)
	242	{
	243	int ret;
	244	u8 data[7];
	245
43d0b10f	246	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
1fcbe42c JG	247
	248	if (ret)
	249	return ret;
	250
bcf18d88 EB	251	tim->tm_sec = bcd2bin(data[0] & 0x7F);
	252	tim->tm_min = bcd2bin(data[1] & 0x7F);
	253	tim->tm_hour = bcd2bin(data[2] & 0x3F);
72877b51	254	tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
bcf18d88	255	tim->tm_mday = bcd2bin(data[4] & 0x3F);
26eeefd5	256	tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
bcf18d88	257	tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
1fcbe42c	258
14813760	259	dev_dbg(dev, "Read from mcp795: %ptR\n", tim);
1fcbe42c	260
22652ba7	261	return 0;
1fcbe42c JG	262	}
1fcbe42c JG	263
644d4c36 EB	264	static int mcp795_set_alarm(struct device dev, struct rtc_wkalrm alm)
	265	{
	266	struct rtc_time now_tm;
	267	time64_t now;
	268	time64_t later;
	269	u8 tmp[6];
	270	int ret;
	271
	272	/* Read current time from RTC hardware */
	273	ret = mcp795_read_time(dev, &now_tm);
	274	if (ret)
	275	return ret;
	276	/* Get the number of seconds since 1970 */
	277	now = rtc_tm_to_time64(&now_tm);
	278	later = rtc_tm_to_time64(&alm->time);
	279	if (later <= now)
	280	return -EINVAL;
	281	/* make sure alarm fires within the next one year */
	282	if ((later - now) >=
	283	(SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
	284	return -EDOM;
	285	/* disable alarm */
	286	ret = mcp795_update_alarm(dev, false);
	287	if (ret)
	288	return ret;
	289	/* Read registers, so we can leave configuration bits untouched */
	290	ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	291	if (ret)
	292	return ret;
	293
	294	alm->time.tm_year = -1;
	295	alm->time.tm_isdst = -1;
	296	alm->time.tm_yday = -1;
	297
	298	tmp[0] = (tmp[0] & 0x80) \| bin2bcd(alm->time.tm_sec);
	299	tmp[1] = (tmp[1] & 0x80) \| bin2bcd(alm->time.tm_min);
	300	tmp[2] = (tmp[2] & 0xE0) \| bin2bcd(alm->time.tm_hour);
	301	tmp[3] = (tmp[3] & 0x80) \| bin2bcd(alm->time.tm_wday + 1);
	302	/* set alarm match: seconds, minutes, hour, day, date and month */
	303	tmp[3] \|= (MCP795_ALM0C2_BIT \| MCP795_ALM0C1_BIT \| MCP795_ALM0C0_BIT);
	304	tmp[4] = (tmp[4] & 0xC0) \| bin2bcd(alm->time.tm_mday);
	305	tmp[5] = (tmp[5] & 0xE0) \| bin2bcd(alm->time.tm_mon + 1);
	306
	307	ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	308	if (ret)
	309	return ret;
	310
	311	/* enable alarm if requested */
	312	if (alm->enabled) {
	313	ret = mcp795_update_alarm(dev, true);
	314	if (ret)
	315	return ret;
	316	dev_dbg(dev, "Alarm IRQ armed\n");
	317	}
14813760 AS	318	dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
14813760 AS	319	&alm->time, alm->time.tm_wday, &alm->time);
644d4c36 EB	320	return 0;
	321	}
	322
	323	static int mcp795_read_alarm(struct device dev, struct rtc_wkalrm alm)
	324	{
	325	u8 data[6];
	326	int ret;
	327
	328	ret = mcp795_rtcc_read(
	329	dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
	330	if (ret)
	331	return ret;
	332
	333	alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
	334	alm->time.tm_min = bcd2bin(data[1] & 0x7F);
	335	alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
	336	alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
	337	alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
	338	alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
	339	alm->time.tm_year = -1;
	340	alm->time.tm_isdst = -1;
	341	alm->time.tm_yday = -1;
	342
14813760 AS	343	dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
14813760 AS	344	&alm->time, alm->time.tm_wday, &alm->time);
644d4c36 EB	345	return 0;
	346	}
	347
	348	static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
	349	{
	350	return mcp795_update_alarm(dev, !!enabled);
	351	}
	352
	353	static irqreturn_t mcp795_irq(int irq, void *data)
	354	{
	355	struct spi_device *spi = data;
	356	struct rtc_device *rtc = spi_get_drvdata(spi);
	357	struct mutex *lock = &rtc->ops_lock;
	358	int ret;
	359
	360	mutex_lock(lock);
	361
	362	/* Disable alarm.
	363	* There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
	364	* because it is done every time when alarm is enabled.
	365	*/
	366	ret = mcp795_update_alarm(&spi->dev, false);
	367	if (ret)
	368	dev_err(&spi->dev,
	369	"Failed to disable alarm in IRQ (ret=%d)\n", ret);
	370	rtc_update_irq(rtc, 1, RTC_AF \| RTC_IRQF);
	371
	372	mutex_unlock(lock);
	373
	374	return IRQ_HANDLED;
	375	}
	376
34c7b3ac	377	static const struct rtc_class_ops mcp795_rtc_ops = {
1fcbe42c	378	.read_time = mcp795_read_time,
644d4c36 EB	379	.set_time = mcp795_set_time,
	380	.read_alarm = mcp795_read_alarm,
	381	.set_alarm = mcp795_set_alarm,
	382	.alarm_irq_enable = mcp795_alarm_irq_enable
1fcbe42c JG	383	};
	384
	385	static int mcp795_probe(struct spi_device *spi)
	386	{
	387	struct rtc_device *rtc;
	388	int ret;
	389
	390	spi->mode = SPI_MODE_0;
	391	spi->bits_per_word = 8;
	392	ret = spi_setup(spi);
	393	if (ret) {
	394	dev_err(&spi->dev, "Unable to setup SPI\n");
	395	return ret;
	396	}
	397
43d0b10f EB	398	/* Start the oscillator but don't set the value of EXTOSC bit */
43d0b10f EB	399	mcp795_start_oscillator(&spi->dev, NULL);
1fcbe42c JG	400	/* Clear the 12 hour mode flag*/
	401	mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
	402
	403	rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
d3e59259	404	&mcp795_rtc_ops, THIS_MODULE);
1fcbe42c JG	405	if (IS_ERR(rtc))
	406	return PTR_ERR(rtc);
	407
	408	spi_set_drvdata(spi, rtc);
	409
644d4c36 EB	410	if (spi->irq > 0) {
	411	dev_dbg(&spi->dev, "Alarm support enabled\n");
	412
	413	/* Clear any pending alarm (ALM0IF bit) before requesting
	414	* the interrupt.
	415	*/
	416	mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
	417	MCP795_ALM0IF_BIT, 0);
	418	ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
	419	mcp795_irq, IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	420	dev_name(&rtc->dev), spi);
	421	if (ret)
	422	dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
	423	spi->irq, ret);
	424	else
	425	device_init_wakeup(&spi->dev, true);
	426	}
1fcbe42c JG	427	return 0;
	428	}
	429
7f8a5892 EB	430	#ifdef CONFIG_OF
	431	static const struct of_device_id mcp795_of_match[] = {
	432	{ .compatible = "maxim,mcp795" },
	433	{ }
	434	};
	435	MODULE_DEVICE_TABLE(of, mcp795_of_match);
	436	#endif
	437
1fcbe42c JG	438	static struct spi_driver mcp795_driver = {
	439	.driver = {
	440	.name = "rtc-mcp795",
7f8a5892	441	.of_match_table = of_match_ptr(mcp795_of_match),
1fcbe42c JG	442	},
	443	.probe = mcp795_probe,
	444	};
	445
	446	module_spi_driver(mcp795_driver);
	447
	448	MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
	449	MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
	450	MODULE_LICENSE("GPL");
	451	MODULE_ALIAS("spi:mcp795");