[linux-2.6-block.git] / drivers / rtc / rtc-mcp795.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * SPI Driver for Microchip MCP795 RTC
 *
 * Copyright (C) Josef Gajdusek <atx@atx.name>
 *
 * based on other Linux RTC drivers
 *
 * Device datasheet:
 * http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/printk.h>
#include <linux/spi/spi.h>
#include <linux/rtc.h>
#include <linux/of.h>
#include <linux/bcd.h>
#include <linux/delay.h>

/* MCP795 Instructions, see datasheet table 3-1 */
#define MCP795_EEREAD	0x03
#define MCP795_EEWRITE	0x02
#define MCP795_EEWRDI	0x04
#define MCP795_EEWREN	0x06
#define MCP795_SRREAD	0x05
#define MCP795_SRWRITE	0x01
#define MCP795_READ	0x13
#define MCP795_WRITE	0x12
#define MCP795_UNLOCK	0x14
#define MCP795_IDWRITE	0x32
#define MCP795_IDREAD	0x33
#define MCP795_CLRWDT	0x44
#define MCP795_CLRRAM	0x54

/* MCP795 RTCC registers, see datasheet table 4-1 */
#define MCP795_REG_SECONDS	0x01
#define MCP795_REG_DAY		0x04
#define MCP795_REG_MONTH	0x06
#define MCP795_REG_CONTROL	0x08
#define MCP795_REG_ALM0_SECONDS	0x0C
#define MCP795_REG_ALM0_DAY	0x0F

#define MCP795_ST_BIT		BIT(7)
#define MCP795_24_BIT		BIT(6)
#define MCP795_LP_BIT		BIT(5)
#define MCP795_EXTOSC_BIT	BIT(3)
#define MCP795_OSCON_BIT	BIT(5)
#define MCP795_ALM0_BIT		BIT(4)
#define MCP795_ALM1_BIT		BIT(5)
#define MCP795_ALM0IF_BIT	BIT(3)
#define MCP795_ALM0C0_BIT	BIT(4)
#define MCP795_ALM0C1_BIT	BIT(5)
#define MCP795_ALM0C2_BIT	BIT(6)

#define SEC_PER_DAY		(24 * 60 * 60)

static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;
	u8 tx[2];

	tx[0] = MCP795_READ;
	tx[1] = addr;
	ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);

	if (ret)
		dev_err(dev, "Failed reading %d bytes from address %x.\n",
					count, addr);

	return ret;
}

static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;
	u8 tx[257];

	tx[0] = MCP795_WRITE;
	tx[1] = addr;
	memcpy(&tx[2], data, count);

	ret = spi_write(spi, tx, 2 + count);

	if (ret)
		dev_err(dev, "Failed to write %d bytes to address %x.\n",
					count, addr);

	return ret;
}

static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
{
	int ret;
	u8 tmp;

	ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
	if (ret)
		return ret;

	if ((tmp & mask) != state) {
		tmp = (tmp & ~mask) | state;
		ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
	}

	return ret;
}

static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
{
	int retries = 5;
	int ret;
	u8 data;

	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
	if (ret)
		return ret;
	ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
	if (ret)
		return ret;
	*extosc = !!(data & MCP795_EXTOSC_BIT);
	ret = mcp795_rtcc_set_bits(
				dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
	if (ret)
		return ret;
	/* wait for the OSCON bit to clear */
	do {
		usleep_range(700, 800);
		ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
		if (ret)
			break;
		if (!(data & MCP795_OSCON_BIT))
			break;

	} while (--retries);

	return !retries ? -EIO : ret;
}

static int mcp795_start_oscillator(struct device *dev, bool *extosc)
{
	if (extosc) {
		u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
		int ret;

		ret = mcp795_rtcc_set_bits(
			dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
		if (ret)
			return ret;
	}
	return mcp795_rtcc_set_bits(
			dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
}

/* Enable or disable Alarm 0 in RTC */
static int mcp795_update_alarm(struct device *dev, bool enable)
{
	int ret;

	dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");

	if (enable) {
		/* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
					MCP795_ALM0IF_BIT, 0);
		if (ret)
			return ret;
		/* enable alarm 0 */
		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
					MCP795_ALM0_BIT, MCP795_ALM0_BIT);
	} else {
		/* disable alarm 0 and alarm 1 */
		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
					MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
	}
	return ret;
}

static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
{
	int ret;
	u8 data[7];
	bool extosc;

	/* Stop RTC and store current value of EXTOSC bit */
	ret = mcp795_stop_oscillator(dev, &extosc);
	if (ret)
		return ret;

	/* Read first, so we can leave config bits untouched */
	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));

	if (ret)
		return ret;

	data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
	data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
	data[2] = bin2bcd(tim->tm_hour);
	data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
	data[4] = bin2bcd(tim->tm_mday);
	data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);

	if (tim->tm_year > 100)
		tim->tm_year -= 100;

	data[6] = bin2bcd(tim->tm_year);

	/* Always write the date and month using a separate Write command.
	 * This is a workaround for a know silicon issue that some combinations
	 * of date and month values may result in the date being reset to 1.
	 */
	ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
	if (ret)
		return ret;

	ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
	if (ret)
		return ret;

	/* Start back RTC and restore previous value of EXTOSC bit.
	 * There is no need to clear EXTOSC bit when the previous value was 0
	 * because it was already cleared when stopping the RTC oscillator.
	 */
	ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
	if (ret)
		return ret;

	dev_dbg(dev, "Set mcp795: %ptR\n", tim);

	return 0;
}

static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
{
	int ret;
	u8 data[7];

	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));

	if (ret)
		return ret;

	tim->tm_sec	= bcd2bin(data[0] & 0x7F);
	tim->tm_min	= bcd2bin(data[1] & 0x7F);
	tim->tm_hour	= bcd2bin(data[2] & 0x3F);
	tim->tm_wday	= bcd2bin(data[3] & 0x07) - 1;
	tim->tm_mday	= bcd2bin(data[4] & 0x3F);
	tim->tm_mon	= bcd2bin(data[5] & 0x1F) - 1;
	tim->tm_year	= bcd2bin(data[6]) + 100; /* Assume we are in 20xx */

	dev_dbg(dev, "Read from mcp795: %ptR\n", tim);

	return 0;
}

static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct rtc_time now_tm;
	time64_t now;
	time64_t later;
	u8 tmp[6];
	int ret;

	/* Read current time from RTC hardware */
	ret = mcp795_read_time(dev, &now_tm);
	if (ret)
		return ret;
	/* Get the number of seconds since 1970 */
	now = rtc_tm_to_time64(&now_tm);
	later = rtc_tm_to_time64(&alm->time);
	if (later <= now)
		return -EINVAL;
	/* make sure alarm fires within the next one year */
	if ((later - now) >=
		(SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
		return -EDOM;
	/* disable alarm */
	ret = mcp795_update_alarm(dev, false);
	if (ret)
		return ret;
	/* Read registers, so we can leave configuration bits untouched */
	ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	if (ret)
		return ret;

	alm->time.tm_year	= -1;
	alm->time.tm_isdst	= -1;
	alm->time.tm_yday	= -1;

	tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
	tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
	tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
	tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
	/* set alarm match: seconds, minutes, hour, day, date and month */
	tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
	tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
	tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);

	ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	if (ret)
		return ret;

	/* enable alarm if requested */
	if (alm->enabled) {
		ret = mcp795_update_alarm(dev, true);
		if (ret)
			return ret;
		dev_dbg(dev, "Alarm IRQ armed\n");
	}
	dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
		&alm->time, alm->time.tm_wday, &alm->time);
	return 0;
}

static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	u8 data[6];
	int ret;

	ret = mcp795_rtcc_read(
			dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
	if (ret)
		return ret;

	alm->time.tm_sec	= bcd2bin(data[0] & 0x7F);
	alm->time.tm_min	= bcd2bin(data[1] & 0x7F);
	alm->time.tm_hour	= bcd2bin(data[2] & 0x1F);
	alm->time.tm_wday	= bcd2bin(data[3] & 0x07) - 1;
	alm->time.tm_mday	= bcd2bin(data[4] & 0x3F);
	alm->time.tm_mon	= bcd2bin(data[5] & 0x1F) - 1;
	alm->time.tm_year	= -1;
	alm->time.tm_isdst	= -1;
	alm->time.tm_yday	= -1;

	dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
		&alm->time, alm->time.tm_wday, &alm->time);
	return 0;
}

static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	return mcp795_update_alarm(dev, !!enabled);
}

static irqreturn_t mcp795_irq(int irq, void *data)
{
	struct spi_device *spi = data;
	struct rtc_device *rtc = spi_get_drvdata(spi);
	struct mutex *lock = &rtc->ops_lock;
	int ret;

	mutex_lock(lock);

	/* Disable alarm.
	 * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
	 * because it is done every time when alarm is enabled.
	 */
	ret = mcp795_update_alarm(&spi->dev, false);
	if (ret)
		dev_err(&spi->dev,
			"Failed to disable alarm in IRQ (ret=%d)\n", ret);
	rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);

	mutex_unlock(lock);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops mcp795_rtc_ops = {
		.read_time = mcp795_read_time,
		.set_time = mcp795_set_time,
		.read_alarm = mcp795_read_alarm,
		.set_alarm = mcp795_set_alarm,
		.alarm_irq_enable = mcp795_alarm_irq_enable
};

static int mcp795_probe(struct spi_device *spi)
{
	struct rtc_device *rtc;
	int ret;

	spi->mode = SPI_MODE_0;
	spi->bits_per_word = 8;
	ret = spi_setup(spi);
	if (ret) {
		dev_err(&spi->dev, "Unable to setup SPI\n");
		return ret;
	}

	/* Start the oscillator but don't set the value of EXTOSC bit */
	mcp795_start_oscillator(&spi->dev, NULL);
	/* Clear the 12 hour mode flag*/
	mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);

	rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
					&mcp795_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	spi_set_drvdata(spi, rtc);

	if (spi->irq > 0) {
		dev_dbg(&spi->dev, "Alarm support enabled\n");

		/* Clear any pending alarm (ALM0IF bit) before requesting
		 * the interrupt.
		 */
		mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
					MCP795_ALM0IF_BIT, 0);
		ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
				mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				dev_name(&rtc->dev), spi);
		if (ret)
			dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
						spi->irq, ret);
		else
			device_init_wakeup(&spi->dev, true);
	}
	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id mcp795_of_match[] = {
	{ .compatible = "maxim,mcp795" },
	{ }
};
MODULE_DEVICE_TABLE(of, mcp795_of_match);
#endif

static struct spi_driver mcp795_driver = {
		.driver = {
				.name = "rtc-mcp795",
				.of_match_table = of_match_ptr(mcp795_of_match),
		},
		.probe = mcp795_probe,
};

module_spi_driver(mcp795_driver);

MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:mcp795");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1fcbe42c JG	2	/*
	3	* SPI Driver for Microchip MCP795 RTC
	4	*
	5	* Copyright (C) Josef Gajdusek <atx@atx.name>
	6	*
	7	* based on other Linux RTC drivers
	8	*
	9	* Device datasheet:
	10	* http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
d3e59259	11	*/
1fcbe42c JG	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/device.h>
	16	#include <linux/printk.h>
	17	#include <linux/spi/spi.h>
	18	#include <linux/rtc.h>
7f8a5892	19	#include <linux/of.h>
bcf18d88	20	#include <linux/bcd.h>
43d0b10f	21	#include <linux/delay.h>
1fcbe42c JG	22
	23	/* MCP795 Instructions, see datasheet table 3-1 */
	24	#define MCP795_EEREAD 0x03
	25	#define MCP795_EEWRITE 0x02
	26	#define MCP795_EEWRDI 0x04
	27	#define MCP795_EEWREN 0x06
	28	#define MCP795_SRREAD 0x05
	29	#define MCP795_SRWRITE 0x01
d3e59259	30	#define MCP795_READ 0x13
1fcbe42c JG	31	#define MCP795_WRITE 0x12
	32	#define MCP795_UNLOCK 0x14
	33	#define MCP795_IDWRITE 0x32
	34	#define MCP795_IDREAD 0x33
	35	#define MCP795_CLRWDT 0x44
	36	#define MCP795_CLRRAM 0x54
	37
43d0b10f EB	38	/* MCP795 RTCC registers, see datasheet table 4-1 */
	39	#define MCP795_REG_SECONDS 0x01
	40	#define MCP795_REG_DAY 0x04
	41	#define MCP795_REG_MONTH 0x06
	42	#define MCP795_REG_CONTROL 0x08
644d4c36 EB	43	#define MCP795_REG_ALM0_SECONDS 0x0C
644d4c36 EB	44	#define MCP795_REG_ALM0_DAY 0x0F
43d0b10f	45
d3e59259 EB	46	#define MCP795_ST_BIT BIT(7)
	47	#define MCP795_24_BIT BIT(6)
	48	#define MCP795_LP_BIT BIT(5)
43d0b10f EB	49	#define MCP795_EXTOSC_BIT BIT(3)
43d0b10f EB	50	#define MCP795_OSCON_BIT BIT(5)
644d4c36 EB	51	#define MCP795_ALM0_BIT BIT(4)
	52	#define MCP795_ALM1_BIT BIT(5)
	53	#define MCP795_ALM0IF_BIT BIT(3)
	54	#define MCP795_ALM0C0_BIT BIT(4)
	55	#define MCP795_ALM0C1_BIT BIT(5)
	56	#define MCP795_ALM0C2_BIT BIT(6)
	57
	58	#define SEC_PER_DAY (24 * 60 * 60)
1fcbe42c JG	59
	60	static int mcp795_rtcc_read(struct device dev, u8 addr, u8 buf, u8 count)
	61	{
	62	struct spi_device *spi = to_spi_device(dev);
	63	int ret;
	64	u8 tx[2];
	65
	66	tx[0] = MCP795_READ;
	67	tx[1] = addr;
	68	ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
	69
	70	if (ret)
	71	dev_err(dev, "Failed reading %d bytes from address %x.\n",
	72	count, addr);
	73
	74	return ret;
	75	}
	76
	77	static int mcp795_rtcc_write(struct device dev, u8 addr, u8 data, u8 count)
	78	{
	79	struct spi_device *spi = to_spi_device(dev);
	80	int ret;
fed9b186	81	u8 tx[257];
1fcbe42c JG	82
	83	tx[0] = MCP795_WRITE;
	84	tx[1] = addr;
	85	memcpy(&tx[2], data, count);
	86
	87	ret = spi_write(spi, tx, 2 + count);
	88
	89	if (ret)
	90	dev_err(dev, "Failed to write %d bytes to address %x.\n",
	91	count, addr);
	92
	93	return ret;
	94	}
	95
	96	static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
	97	{
	98	int ret;
	99	u8 tmp;
	100
	101	ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
	102	if (ret)
	103	return ret;
	104
	105	if ((tmp & mask) != state) {
	106	tmp = (tmp & ~mask) \| state;
	107	ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
	108	}
	109
	110	return ret;
	111	}
	112
43d0b10f EB	113	static int mcp795_stop_oscillator(struct device dev, bool extosc)
	114	{
	115	int retries = 5;
	116	int ret;
	117	u8 data;
	118
	119	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
	120	if (ret)
	121	return ret;
	122	ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
	123	if (ret)
	124	return ret;
	125	*extosc = !!(data & MCP795_EXTOSC_BIT);
	126	ret = mcp795_rtcc_set_bits(
	127	dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
	128	if (ret)
	129	return ret;
	130	/* wait for the OSCON bit to clear */
	131	do {
	132	usleep_range(700, 800);
	133	ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
	134	if (ret)
	135	break;
	136	if (!(data & MCP795_OSCON_BIT))
	137	break;
	138
	139	} while (--retries);
	140
	141	return !retries ? -EIO : ret;
	142	}
	143
	144	static int mcp795_start_oscillator(struct device dev, bool extosc)
	145	{
	146	if (extosc) {
	147	u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
	148	int ret;
	149
	150	ret = mcp795_rtcc_set_bits(
	151	dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
	152	if (ret)
	153	return ret;
	154	}
	155	return mcp795_rtcc_set_bits(
	156	dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
	157	}
	158
644d4c36 EB	159	/* Enable or disable Alarm 0 in RTC */
	160	static int mcp795_update_alarm(struct device *dev, bool enable)
	161	{
	162	int ret;
	163
	164	dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
	165
	166	if (enable) {
	167	/* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
	168	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
	169	MCP795_ALM0IF_BIT, 0);
	170	if (ret)
	171	return ret;
	172	/* enable alarm 0 */
	173	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
	174	MCP795_ALM0_BIT, MCP795_ALM0_BIT);
	175	} else {
	176	/* disable alarm 0 and alarm 1 */
	177	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
	178	MCP795_ALM0_BIT \| MCP795_ALM1_BIT, 0);
	179	}
	180	return ret;
	181	}
	182
1fcbe42c JG	183	static int mcp795_set_time(struct device dev, struct rtc_time tim)
	184	{
	185	int ret;
	186	u8 data[7];
43d0b10f EB	187	bool extosc;
	188
	189	/* Stop RTC and store current value of EXTOSC bit */
	190	ret = mcp795_stop_oscillator(dev, &extosc);
	191	if (ret)
	192	return ret;
1fcbe42c JG	193
1fcbe42c JG	194	/* Read first, so we can leave config bits untouched */
43d0b10f	195	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
1fcbe42c JG	196
	197	if (ret)
	198	return ret;
	199
bcf18d88 EB	200	data[0] = (data[0] & 0x80) \| bin2bcd(tim->tm_sec);
	201	data[1] = (data[1] & 0x80) \| bin2bcd(tim->tm_min);
	202	data[2] = bin2bcd(tim->tm_hour);
72877b51	203	data[3] = (data[3] & 0xF8) \| bin2bcd(tim->tm_wday + 1);
bcf18d88	204	data[4] = bin2bcd(tim->tm_mday);
26eeefd5	205	data[5] = (data[5] & MCP795_LP_BIT) \| bin2bcd(tim->tm_mon + 1);
1fcbe42c JG	206
	207	if (tim->tm_year > 100)
	208	tim->tm_year -= 100;
	209
bcf18d88	210	data[6] = bin2bcd(tim->tm_year);
1fcbe42c	211
43d0b10f EB	212	/* Always write the date and month using a separate Write command.
	213	* This is a workaround for a know silicon issue that some combinations
	214	* of date and month values may result in the date being reset to 1.
	215	*/
	216	ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
	217	if (ret)
	218	return ret;
	219
	220	ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
	221	if (ret)
	222	return ret;
1fcbe42c	223
43d0b10f EB	224	/* Start back RTC and restore previous value of EXTOSC bit.
	225	* There is no need to clear EXTOSC bit when the previous value was 0
	226	* because it was already cleared when stopping the RTC oscillator.
	227	*/
	228	ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
1fcbe42c JG	229	if (ret)
	230	return ret;
	231
14813760	232	dev_dbg(dev, "Set mcp795: %ptR\n", tim);
1fcbe42c JG	233
	234	return 0;
	235	}
	236
	237	static int mcp795_read_time(struct device dev, struct rtc_time tim)
	238	{
	239	int ret;
	240	u8 data[7];
	241
43d0b10f	242	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
1fcbe42c JG	243
	244	if (ret)
	245	return ret;
	246
bcf18d88 EB	247	tim->tm_sec = bcd2bin(data[0] & 0x7F);
	248	tim->tm_min = bcd2bin(data[1] & 0x7F);
	249	tim->tm_hour = bcd2bin(data[2] & 0x3F);
72877b51	250	tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
bcf18d88	251	tim->tm_mday = bcd2bin(data[4] & 0x3F);
26eeefd5	252	tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
bcf18d88	253	tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
1fcbe42c	254
14813760	255	dev_dbg(dev, "Read from mcp795: %ptR\n", tim);
1fcbe42c	256
22652ba7	257	return 0;
1fcbe42c JG	258	}
1fcbe42c JG	259
644d4c36 EB	260	static int mcp795_set_alarm(struct device dev, struct rtc_wkalrm alm)
	261	{
	262	struct rtc_time now_tm;
	263	time64_t now;
	264	time64_t later;
	265	u8 tmp[6];
	266	int ret;
	267
	268	/* Read current time from RTC hardware */
	269	ret = mcp795_read_time(dev, &now_tm);
	270	if (ret)
	271	return ret;
	272	/* Get the number of seconds since 1970 */
	273	now = rtc_tm_to_time64(&now_tm);
	274	later = rtc_tm_to_time64(&alm->time);
	275	if (later <= now)
	276	return -EINVAL;
	277	/* make sure alarm fires within the next one year */
	278	if ((later - now) >=
	279	(SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
	280	return -EDOM;
	281	/* disable alarm */
	282	ret = mcp795_update_alarm(dev, false);
	283	if (ret)
	284	return ret;
	285	/* Read registers, so we can leave configuration bits untouched */
	286	ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	287	if (ret)
	288	return ret;
	289
	290	alm->time.tm_year = -1;
	291	alm->time.tm_isdst = -1;
	292	alm->time.tm_yday = -1;
	293
	294	tmp[0] = (tmp[0] & 0x80) \| bin2bcd(alm->time.tm_sec);
	295	tmp[1] = (tmp[1] & 0x80) \| bin2bcd(alm->time.tm_min);
	296	tmp[2] = (tmp[2] & 0xE0) \| bin2bcd(alm->time.tm_hour);
	297	tmp[3] = (tmp[3] & 0x80) \| bin2bcd(alm->time.tm_wday + 1);
	298	/* set alarm match: seconds, minutes, hour, day, date and month */
	299	tmp[3] \|= (MCP795_ALM0C2_BIT \| MCP795_ALM0C1_BIT \| MCP795_ALM0C0_BIT);
	300	tmp[4] = (tmp[4] & 0xC0) \| bin2bcd(alm->time.tm_mday);
	301	tmp[5] = (tmp[5] & 0xE0) \| bin2bcd(alm->time.tm_mon + 1);
	302
	303	ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
	304	if (ret)
	305	return ret;
	306
	307	/* enable alarm if requested */
	308	if (alm->enabled) {
	309	ret = mcp795_update_alarm(dev, true);
	310	if (ret)
	311	return ret;
	312	dev_dbg(dev, "Alarm IRQ armed\n");
	313	}
14813760 AS	314	dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
14813760 AS	315	&alm->time, alm->time.tm_wday, &alm->time);
644d4c36 EB	316	return 0;
	317	}
	318
	319	static int mcp795_read_alarm(struct device dev, struct rtc_wkalrm alm)
	320	{
	321	u8 data[6];
	322	int ret;
	323
	324	ret = mcp795_rtcc_read(
	325	dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
	326	if (ret)
	327	return ret;
	328
	329	alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
	330	alm->time.tm_min = bcd2bin(data[1] & 0x7F);
	331	alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
	332	alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
	333	alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
	334	alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
	335	alm->time.tm_year = -1;
	336	alm->time.tm_isdst = -1;
	337	alm->time.tm_yday = -1;
	338
14813760 AS	339	dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
14813760 AS	340	&alm->time, alm->time.tm_wday, &alm->time);
644d4c36 EB	341	return 0;
	342	}
	343
	344	static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
	345	{
	346	return mcp795_update_alarm(dev, !!enabled);
	347	}
	348
	349	static irqreturn_t mcp795_irq(int irq, void *data)
	350	{
	351	struct spi_device *spi = data;
	352	struct rtc_device *rtc = spi_get_drvdata(spi);
	353	struct mutex *lock = &rtc->ops_lock;
	354	int ret;
	355
	356	mutex_lock(lock);
	357
	358	/* Disable alarm.
	359	* There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
	360	* because it is done every time when alarm is enabled.
	361	*/
	362	ret = mcp795_update_alarm(&spi->dev, false);
	363	if (ret)
	364	dev_err(&spi->dev,
	365	"Failed to disable alarm in IRQ (ret=%d)\n", ret);
	366	rtc_update_irq(rtc, 1, RTC_AF \| RTC_IRQF);
	367
	368	mutex_unlock(lock);
	369
	370	return IRQ_HANDLED;
	371	}
	372
34c7b3ac	373	static const struct rtc_class_ops mcp795_rtc_ops = {
1fcbe42c	374	.read_time = mcp795_read_time,
644d4c36 EB	375	.set_time = mcp795_set_time,
	376	.read_alarm = mcp795_read_alarm,
	377	.set_alarm = mcp795_set_alarm,
	378	.alarm_irq_enable = mcp795_alarm_irq_enable
1fcbe42c JG	379	};
	380
	381	static int mcp795_probe(struct spi_device *spi)
	382	{
	383	struct rtc_device *rtc;
	384	int ret;
	385
	386	spi->mode = SPI_MODE_0;
	387	spi->bits_per_word = 8;
	388	ret = spi_setup(spi);
	389	if (ret) {
	390	dev_err(&spi->dev, "Unable to setup SPI\n");
	391	return ret;
	392	}
	393
43d0b10f EB	394	/* Start the oscillator but don't set the value of EXTOSC bit */
43d0b10f EB	395	mcp795_start_oscillator(&spi->dev, NULL);
1fcbe42c JG	396	/* Clear the 12 hour mode flag*/
	397	mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
	398
	399	rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
d3e59259	400	&mcp795_rtc_ops, THIS_MODULE);
1fcbe42c JG	401	if (IS_ERR(rtc))
	402	return PTR_ERR(rtc);
	403
	404	spi_set_drvdata(spi, rtc);
	405
644d4c36 EB	406	if (spi->irq > 0) {
	407	dev_dbg(&spi->dev, "Alarm support enabled\n");
	408
	409	/* Clear any pending alarm (ALM0IF bit) before requesting
	410	* the interrupt.
	411	*/
	412	mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
	413	MCP795_ALM0IF_BIT, 0);
	414	ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
	415	mcp795_irq, IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	416	dev_name(&rtc->dev), spi);
	417	if (ret)
	418	dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
	419	spi->irq, ret);
	420	else
	421	device_init_wakeup(&spi->dev, true);
	422	}
1fcbe42c JG	423	return 0;
	424	}
	425
7f8a5892 EB	426	#ifdef CONFIG_OF
	427	static const struct of_device_id mcp795_of_match[] = {
	428	{ .compatible = "maxim,mcp795" },
	429	{ }
	430	};
	431	MODULE_DEVICE_TABLE(of, mcp795_of_match);
	432	#endif
	433
1fcbe42c JG	434	static struct spi_driver mcp795_driver = {
	435	.driver = {
	436	.name = "rtc-mcp795",
7f8a5892	437	.of_match_table = of_match_ptr(mcp795_of_match),
1fcbe42c JG	438	},
	439	.probe = mcp795_probe,
	440	};
	441
	442	module_spi_driver(mcp795_driver);
	443
	444	MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
	445	MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
	446	MODULE_LICENSE("GPL");
	447	MODULE_ALIAS("spi:mcp795");