Commit | Line | Data |
---|---|---|
fca1dd03 | 1 | /* |
f903129b | 2 | * RTC driver for Maxim MAX77686 and MAX77802 |
fca1dd03 JL |
3 | * |
4 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | |
5 | * | |
6 | * based on rtc-max8997.c | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
f3937549 | 15 | #include <linux/i2c.h> |
fca1dd03 JL |
16 | #include <linux/slab.h> |
17 | #include <linux/rtc.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/mutex.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/mfd/max77686-private.h> | |
23 | #include <linux/irqdomain.h> | |
24 | #include <linux/regmap.h> | |
25 | ||
f3937549 | 26 | #define MAX77686_I2C_ADDR_RTC (0x0C >> 1) |
726fe738 | 27 | #define MAX77620_I2C_ADDR_RTC 0x68 |
f3937549 LD |
28 | #define MAX77686_INVALID_I2C_ADDR (-1) |
29 | ||
726fe738 LD |
30 | /* Define non existing register */ |
31 | #define MAX77686_INVALID_REG (-1) | |
32 | ||
fca1dd03 JL |
33 | /* RTC Control Register */ |
34 | #define BCD_EN_SHIFT 0 | |
0b4f8b08 | 35 | #define BCD_EN_MASK BIT(BCD_EN_SHIFT) |
fca1dd03 | 36 | #define MODEL24_SHIFT 1 |
0b4f8b08 | 37 | #define MODEL24_MASK BIT(MODEL24_SHIFT) |
fca1dd03 JL |
38 | /* RTC Update Register1 */ |
39 | #define RTC_UDR_SHIFT 0 | |
0b4f8b08 | 40 | #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT) |
fca1dd03 | 41 | #define RTC_RBUDR_SHIFT 4 |
0b4f8b08 | 42 | #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT) |
fca1dd03 JL |
43 | /* RTC Hour register */ |
44 | #define HOUR_PM_SHIFT 6 | |
0b4f8b08 | 45 | #define HOUR_PM_MASK BIT(HOUR_PM_SHIFT) |
fca1dd03 JL |
46 | /* RTC Alarm Enable */ |
47 | #define ALARM_ENABLE_SHIFT 7 | |
0b4f8b08 | 48 | #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT) |
fca1dd03 | 49 | |
f903129b JMC |
50 | #define REG_RTC_NONE 0xdeadbeef |
51 | ||
52 | /* | |
53 | * MAX77802 has separate register (RTCAE1) for alarm enable instead | |
54 | * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE} | |
55 | * as in done in MAX77686. | |
56 | */ | |
57 | #define MAX77802_ALARM_ENABLE_VALUE 0x77 | |
58 | ||
fca1dd03 JL |
59 | enum { |
60 | RTC_SEC = 0, | |
61 | RTC_MIN, | |
62 | RTC_HOUR, | |
63 | RTC_WEEKDAY, | |
64 | RTC_MONTH, | |
65 | RTC_YEAR, | |
66 | RTC_DATE, | |
67 | RTC_NR_TIME | |
68 | }; | |
69 | ||
01ea01b3 JMC |
70 | struct max77686_rtc_driver_data { |
71 | /* Minimum usecs needed for a RTC update */ | |
72 | unsigned long delay; | |
73 | /* Mask used to read RTC registers value */ | |
74 | u8 mask; | |
90a5698a JMC |
75 | /* Registers offset to I2C addresses map */ |
76 | const unsigned int *map; | |
f903129b JMC |
77 | /* Has a separate alarm enable register? */ |
78 | bool alarm_enable_reg; | |
f3937549 LD |
79 | /* I2C address for RTC block */ |
80 | int rtc_i2c_addr; | |
726fe738 LD |
81 | /* RTC interrupt via platform resource */ |
82 | bool rtc_irq_from_platform; | |
83 | /* Pending alarm status register */ | |
84 | int alarm_pending_status_reg; | |
f3937549 LD |
85 | /* RTC IRQ CHIP for regmap */ |
86 | const struct regmap_irq_chip *rtc_irq_chip; | |
01ea01b3 JMC |
87 | }; |
88 | ||
fca1dd03 JL |
89 | struct max77686_rtc_info { |
90 | struct device *dev; | |
fca1dd03 JL |
91 | struct i2c_client *rtc; |
92 | struct rtc_device *rtc_dev; | |
93 | struct mutex lock; | |
94 | ||
95 | struct regmap *regmap; | |
f604c488 | 96 | struct regmap *rtc_regmap; |
fca1dd03 | 97 | |
01ea01b3 | 98 | const struct max77686_rtc_driver_data *drv_data; |
f3937549 | 99 | struct regmap_irq_chip_data *rtc_irq_data; |
01ea01b3 | 100 | |
f3937549 | 101 | int rtc_irq; |
fca1dd03 JL |
102 | int virq; |
103 | int rtc_24hr_mode; | |
104 | }; | |
105 | ||
106 | enum MAX77686_RTC_OP { | |
107 | MAX77686_RTC_WRITE, | |
108 | MAX77686_RTC_READ, | |
109 | }; | |
110 | ||
90a5698a JMC |
111 | /* These are not registers but just offsets that are mapped to addresses */ |
112 | enum max77686_rtc_reg_offset { | |
113 | REG_RTC_CONTROLM = 0, | |
114 | REG_RTC_CONTROL, | |
115 | REG_RTC_UPDATE0, | |
116 | REG_WTSR_SMPL_CNTL, | |
117 | REG_RTC_SEC, | |
118 | REG_RTC_MIN, | |
119 | REG_RTC_HOUR, | |
120 | REG_RTC_WEEKDAY, | |
121 | REG_RTC_MONTH, | |
122 | REG_RTC_YEAR, | |
123 | REG_RTC_DATE, | |
124 | REG_ALARM1_SEC, | |
125 | REG_ALARM1_MIN, | |
126 | REG_ALARM1_HOUR, | |
127 | REG_ALARM1_WEEKDAY, | |
128 | REG_ALARM1_MONTH, | |
129 | REG_ALARM1_YEAR, | |
130 | REG_ALARM1_DATE, | |
131 | REG_ALARM2_SEC, | |
132 | REG_ALARM2_MIN, | |
133 | REG_ALARM2_HOUR, | |
134 | REG_ALARM2_WEEKDAY, | |
135 | REG_ALARM2_MONTH, | |
136 | REG_ALARM2_YEAR, | |
137 | REG_ALARM2_DATE, | |
f903129b | 138 | REG_RTC_AE1, |
90a5698a JMC |
139 | REG_RTC_END, |
140 | }; | |
141 | ||
142 | /* Maps RTC registers offset to the MAX77686 register addresses */ | |
143 | static const unsigned int max77686_map[REG_RTC_END] = { | |
144 | [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM, | |
145 | [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL, | |
146 | [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0, | |
147 | [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL, | |
148 | [REG_RTC_SEC] = MAX77686_RTC_SEC, | |
149 | [REG_RTC_MIN] = MAX77686_RTC_MIN, | |
150 | [REG_RTC_HOUR] = MAX77686_RTC_HOUR, | |
151 | [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY, | |
152 | [REG_RTC_MONTH] = MAX77686_RTC_MONTH, | |
153 | [REG_RTC_YEAR] = MAX77686_RTC_YEAR, | |
154 | [REG_RTC_DATE] = MAX77686_RTC_DATE, | |
155 | [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC, | |
156 | [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN, | |
157 | [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR, | |
158 | [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY, | |
159 | [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH, | |
160 | [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR, | |
161 | [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE, | |
162 | [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC, | |
163 | [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN, | |
164 | [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR, | |
165 | [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY, | |
166 | [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH, | |
167 | [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR, | |
168 | [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE, | |
f903129b | 169 | [REG_RTC_AE1] = REG_RTC_NONE, |
90a5698a JMC |
170 | }; |
171 | ||
f3937549 LD |
172 | static const struct regmap_irq max77686_rtc_irqs[] = { |
173 | /* RTC interrupts */ | |
7e84536c LD |
174 | REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK), |
175 | REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK), | |
176 | REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK), | |
177 | REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK), | |
178 | REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK), | |
179 | REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK), | |
f3937549 LD |
180 | }; |
181 | ||
182 | static const struct regmap_irq_chip max77686_rtc_irq_chip = { | |
183 | .name = "max77686-rtc", | |
184 | .status_base = MAX77686_RTC_INT, | |
185 | .mask_base = MAX77686_RTC_INTM, | |
186 | .num_regs = 1, | |
187 | .irqs = max77686_rtc_irqs, | |
188 | .num_irqs = ARRAY_SIZE(max77686_rtc_irqs), | |
189 | }; | |
190 | ||
01ea01b3 JMC |
191 | static const struct max77686_rtc_driver_data max77686_drv_data = { |
192 | .delay = 16000, | |
193 | .mask = 0x7f, | |
90a5698a | 194 | .map = max77686_map, |
f903129b | 195 | .alarm_enable_reg = false, |
726fe738 LD |
196 | .rtc_irq_from_platform = false, |
197 | .alarm_pending_status_reg = MAX77686_REG_STATUS2, | |
f3937549 LD |
198 | .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC, |
199 | .rtc_irq_chip = &max77686_rtc_irq_chip, | |
f903129b JMC |
200 | }; |
201 | ||
726fe738 LD |
202 | static const struct max77686_rtc_driver_data max77620_drv_data = { |
203 | .delay = 16000, | |
204 | .mask = 0x7f, | |
205 | .map = max77686_map, | |
206 | .alarm_enable_reg = false, | |
207 | .rtc_irq_from_platform = true, | |
208 | .alarm_pending_status_reg = MAX77686_INVALID_REG, | |
209 | .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC, | |
210 | .rtc_irq_chip = &max77686_rtc_irq_chip, | |
211 | }; | |
212 | ||
f903129b JMC |
213 | static const unsigned int max77802_map[REG_RTC_END] = { |
214 | [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM, | |
215 | [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL, | |
216 | [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0, | |
217 | [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL, | |
218 | [REG_RTC_SEC] = MAX77802_RTC_SEC, | |
219 | [REG_RTC_MIN] = MAX77802_RTC_MIN, | |
220 | [REG_RTC_HOUR] = MAX77802_RTC_HOUR, | |
221 | [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY, | |
222 | [REG_RTC_MONTH] = MAX77802_RTC_MONTH, | |
223 | [REG_RTC_YEAR] = MAX77802_RTC_YEAR, | |
224 | [REG_RTC_DATE] = MAX77802_RTC_DATE, | |
225 | [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC, | |
226 | [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN, | |
227 | [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR, | |
228 | [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY, | |
229 | [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH, | |
230 | [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR, | |
231 | [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE, | |
232 | [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC, | |
233 | [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN, | |
234 | [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR, | |
235 | [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY, | |
236 | [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH, | |
237 | [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR, | |
238 | [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE, | |
239 | [REG_RTC_AE1] = MAX77802_RTC_AE1, | |
240 | }; | |
241 | ||
f3937549 LD |
242 | static const struct regmap_irq_chip max77802_rtc_irq_chip = { |
243 | .name = "max77802-rtc", | |
244 | .status_base = MAX77802_RTC_INT, | |
245 | .mask_base = MAX77802_RTC_INTM, | |
246 | .num_regs = 1, | |
247 | .irqs = max77686_rtc_irqs, /* same masks as 77686 */ | |
248 | .num_irqs = ARRAY_SIZE(max77686_rtc_irqs), | |
249 | }; | |
250 | ||
f903129b JMC |
251 | static const struct max77686_rtc_driver_data max77802_drv_data = { |
252 | .delay = 200, | |
253 | .mask = 0xff, | |
254 | .map = max77802_map, | |
255 | .alarm_enable_reg = true, | |
726fe738 LD |
256 | .rtc_irq_from_platform = false, |
257 | .alarm_pending_status_reg = MAX77686_REG_STATUS2, | |
f3937549 LD |
258 | .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR, |
259 | .rtc_irq_chip = &max77802_rtc_irq_chip, | |
01ea01b3 JMC |
260 | }; |
261 | ||
fca1dd03 | 262 | static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm, |
01ea01b3 | 263 | struct max77686_rtc_info *info) |
fca1dd03 | 264 | { |
01ea01b3 JMC |
265 | u8 mask = info->drv_data->mask; |
266 | ||
267 | tm->tm_sec = data[RTC_SEC] & mask; | |
268 | tm->tm_min = data[RTC_MIN] & mask; | |
0b4f8b08 | 269 | if (info->rtc_24hr_mode) { |
fca1dd03 | 270 | tm->tm_hour = data[RTC_HOUR] & 0x1f; |
0b4f8b08 | 271 | } else { |
fca1dd03 JL |
272 | tm->tm_hour = data[RTC_HOUR] & 0x0f; |
273 | if (data[RTC_HOUR] & HOUR_PM_MASK) | |
274 | tm->tm_hour += 12; | |
275 | } | |
276 | ||
a20cd88e | 277 | /* Only a single bit is set in data[], so fls() would be equivalent */ |
01ea01b3 | 278 | tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1; |
fca1dd03 JL |
279 | tm->tm_mday = data[RTC_DATE] & 0x1f; |
280 | tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; | |
f903129b | 281 | tm->tm_year = data[RTC_YEAR] & mask; |
fca1dd03 JL |
282 | tm->tm_yday = 0; |
283 | tm->tm_isdst = 0; | |
f903129b JMC |
284 | |
285 | /* | |
286 | * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the | |
287 | * year values are just 0..99 so add 100 to support up to 2099. | |
288 | */ | |
289 | if (!info->drv_data->alarm_enable_reg) | |
290 | tm->tm_year += 100; | |
fca1dd03 JL |
291 | } |
292 | ||
f903129b JMC |
293 | static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data, |
294 | struct max77686_rtc_info *info) | |
fca1dd03 JL |
295 | { |
296 | data[RTC_SEC] = tm->tm_sec; | |
297 | data[RTC_MIN] = tm->tm_min; | |
298 | data[RTC_HOUR] = tm->tm_hour; | |
299 | data[RTC_WEEKDAY] = 1 << tm->tm_wday; | |
300 | data[RTC_DATE] = tm->tm_mday; | |
301 | data[RTC_MONTH] = tm->tm_mon + 1; | |
f903129b JMC |
302 | |
303 | if (info->drv_data->alarm_enable_reg) { | |
304 | data[RTC_YEAR] = tm->tm_year; | |
305 | return 0; | |
306 | } | |
307 | ||
cdf5f4ac | 308 | data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0; |
fca1dd03 JL |
309 | |
310 | if (tm->tm_year < 100) { | |
1e5813bd | 311 | dev_err(info->dev, "RTC cannot handle the year %d.\n", |
a737e835 | 312 | 1900 + tm->tm_year); |
fca1dd03 JL |
313 | return -EINVAL; |
314 | } | |
f903129b | 315 | |
fca1dd03 JL |
316 | return 0; |
317 | } | |
318 | ||
319 | static int max77686_rtc_update(struct max77686_rtc_info *info, | |
0b4f8b08 | 320 | enum MAX77686_RTC_OP op) |
fca1dd03 JL |
321 | { |
322 | int ret; | |
323 | unsigned int data; | |
01ea01b3 | 324 | unsigned long delay = info->drv_data->delay; |
fca1dd03 JL |
325 | |
326 | if (op == MAX77686_RTC_WRITE) | |
327 | data = 1 << RTC_UDR_SHIFT; | |
328 | else | |
329 | data = 1 << RTC_RBUDR_SHIFT; | |
330 | ||
f604c488 | 331 | ret = regmap_update_bits(info->rtc_regmap, |
90a5698a JMC |
332 | info->drv_data->map[REG_RTC_UPDATE0], |
333 | data, data); | |
fca1dd03 | 334 | if (ret < 0) |
bf035f42 KK |
335 | dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n", |
336 | ret, data); | |
fca1dd03 | 337 | else { |
01ea01b3 JMC |
338 | /* Minimum delay required before RTC update. */ |
339 | usleep_range(delay, delay * 2); | |
fca1dd03 JL |
340 | } |
341 | ||
342 | return ret; | |
343 | } | |
344 | ||
345 | static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
346 | { | |
347 | struct max77686_rtc_info *info = dev_get_drvdata(dev); | |
348 | u8 data[RTC_NR_TIME]; | |
349 | int ret; | |
350 | ||
351 | mutex_lock(&info->lock); | |
352 | ||
353 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); | |
354 | if (ret < 0) | |
355 | goto out; | |
356 | ||
f604c488 | 357 | ret = regmap_bulk_read(info->rtc_regmap, |
90a5698a JMC |
358 | info->drv_data->map[REG_RTC_SEC], |
359 | data, ARRAY_SIZE(data)); | |
fca1dd03 | 360 | if (ret < 0) { |
bf035f42 | 361 | dev_err(info->dev, "Fail to read time reg(%d)\n", ret); |
fca1dd03 JL |
362 | goto out; |
363 | } | |
364 | ||
01ea01b3 | 365 | max77686_rtc_data_to_tm(data, tm, info); |
fca1dd03 | 366 | |
fca1dd03 JL |
367 | out: |
368 | mutex_unlock(&info->lock); | |
e115a2bf | 369 | return 0; |
fca1dd03 JL |
370 | } |
371 | ||
372 | static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
373 | { | |
374 | struct max77686_rtc_info *info = dev_get_drvdata(dev); | |
375 | u8 data[RTC_NR_TIME]; | |
376 | int ret; | |
377 | ||
f903129b | 378 | ret = max77686_rtc_tm_to_data(tm, data, info); |
fca1dd03 JL |
379 | if (ret < 0) |
380 | return ret; | |
381 | ||
382 | mutex_lock(&info->lock); | |
383 | ||
f604c488 | 384 | ret = regmap_bulk_write(info->rtc_regmap, |
90a5698a JMC |
385 | info->drv_data->map[REG_RTC_SEC], |
386 | data, ARRAY_SIZE(data)); | |
fca1dd03 | 387 | if (ret < 0) { |
bf035f42 | 388 | dev_err(info->dev, "Fail to write time reg(%d)\n", ret); |
fca1dd03 JL |
389 | goto out; |
390 | } | |
391 | ||
392 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); | |
393 | ||
394 | out: | |
395 | mutex_unlock(&info->lock); | |
396 | return ret; | |
397 | } | |
398 | ||
399 | static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
400 | { | |
401 | struct max77686_rtc_info *info = dev_get_drvdata(dev); | |
402 | u8 data[RTC_NR_TIME]; | |
403 | unsigned int val; | |
90a5698a | 404 | const unsigned int *map = info->drv_data->map; |
fca1dd03 JL |
405 | int i, ret; |
406 | ||
407 | mutex_lock(&info->lock); | |
408 | ||
409 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); | |
410 | if (ret < 0) | |
411 | goto out; | |
412 | ||
f604c488 LD |
413 | ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC], |
414 | data, ARRAY_SIZE(data)); | |
fca1dd03 | 415 | if (ret < 0) { |
bf035f42 | 416 | dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret); |
fca1dd03 JL |
417 | goto out; |
418 | } | |
419 | ||
01ea01b3 | 420 | max77686_rtc_data_to_tm(data, &alrm->time, info); |
fca1dd03 JL |
421 | |
422 | alrm->enabled = 0; | |
f903129b JMC |
423 | |
424 | if (info->drv_data->alarm_enable_reg) { | |
425 | if (map[REG_RTC_AE1] == REG_RTC_NONE) { | |
426 | ret = -EINVAL; | |
427 | dev_err(info->dev, | |
428 | "alarm enable register not set(%d)\n", ret); | |
429 | goto out; | |
430 | } | |
431 | ||
f604c488 | 432 | ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val); |
f903129b JMC |
433 | if (ret < 0) { |
434 | dev_err(info->dev, | |
435 | "fail to read alarm enable(%d)\n", ret); | |
436 | goto out; | |
437 | } | |
438 | ||
439 | if (val) | |
fca1dd03 | 440 | alrm->enabled = 1; |
f903129b JMC |
441 | } else { |
442 | for (i = 0; i < ARRAY_SIZE(data); i++) { | |
443 | if (data[i] & ALARM_ENABLE_MASK) { | |
444 | alrm->enabled = 1; | |
445 | break; | |
446 | } | |
fca1dd03 JL |
447 | } |
448 | } | |
449 | ||
450 | alrm->pending = 0; | |
726fe738 LD |
451 | |
452 | if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG) | |
453 | goto out; | |
454 | ||
455 | ret = regmap_read(info->regmap, | |
456 | info->drv_data->alarm_pending_status_reg, &val); | |
fca1dd03 | 457 | if (ret < 0) { |
726fe738 LD |
458 | dev_err(info->dev, |
459 | "Fail to read alarm pending status reg(%d)\n", ret); | |
fca1dd03 JL |
460 | goto out; |
461 | } | |
462 | ||
463 | if (val & (1 << 4)) /* RTCA1 */ | |
464 | alrm->pending = 1; | |
465 | ||
466 | out: | |
467 | mutex_unlock(&info->lock); | |
7cdffeb5 | 468 | return ret; |
fca1dd03 JL |
469 | } |
470 | ||
471 | static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info) | |
472 | { | |
473 | u8 data[RTC_NR_TIME]; | |
474 | int ret, i; | |
475 | struct rtc_time tm; | |
90a5698a | 476 | const unsigned int *map = info->drv_data->map; |
fca1dd03 JL |
477 | |
478 | if (!mutex_is_locked(&info->lock)) | |
479 | dev_warn(info->dev, "%s: should have mutex locked\n", __func__); | |
480 | ||
481 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); | |
482 | if (ret < 0) | |
483 | goto out; | |
484 | ||
f903129b JMC |
485 | if (info->drv_data->alarm_enable_reg) { |
486 | if (map[REG_RTC_AE1] == REG_RTC_NONE) { | |
487 | ret = -EINVAL; | |
488 | dev_err(info->dev, | |
489 | "alarm enable register not set(%d)\n", ret); | |
490 | goto out; | |
491 | } | |
492 | ||
f604c488 | 493 | ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0); |
f903129b | 494 | } else { |
f604c488 LD |
495 | ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC], |
496 | data, ARRAY_SIZE(data)); | |
f903129b | 497 | if (ret < 0) { |
bf035f42 | 498 | dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret); |
f903129b JMC |
499 | goto out; |
500 | } | |
fca1dd03 | 501 | |
f903129b | 502 | max77686_rtc_data_to_tm(data, &tm, info); |
fca1dd03 | 503 | |
f903129b JMC |
504 | for (i = 0; i < ARRAY_SIZE(data); i++) |
505 | data[i] &= ~ALARM_ENABLE_MASK; | |
506 | ||
f604c488 LD |
507 | ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC], |
508 | data, ARRAY_SIZE(data)); | |
f903129b | 509 | } |
fca1dd03 | 510 | |
fca1dd03 | 511 | if (ret < 0) { |
bf035f42 | 512 | dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret); |
fca1dd03 JL |
513 | goto out; |
514 | } | |
515 | ||
516 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); | |
517 | out: | |
518 | return ret; | |
519 | } | |
520 | ||
521 | static int max77686_rtc_start_alarm(struct max77686_rtc_info *info) | |
522 | { | |
523 | u8 data[RTC_NR_TIME]; | |
524 | int ret; | |
525 | struct rtc_time tm; | |
90a5698a | 526 | const unsigned int *map = info->drv_data->map; |
fca1dd03 JL |
527 | |
528 | if (!mutex_is_locked(&info->lock)) | |
529 | dev_warn(info->dev, "%s: should have mutex locked\n", __func__); | |
530 | ||
531 | ret = max77686_rtc_update(info, MAX77686_RTC_READ); | |
532 | if (ret < 0) | |
533 | goto out; | |
534 | ||
f903129b | 535 | if (info->drv_data->alarm_enable_reg) { |
f604c488 | 536 | ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], |
f903129b JMC |
537 | MAX77802_ALARM_ENABLE_VALUE); |
538 | } else { | |
f604c488 LD |
539 | ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC], |
540 | data, ARRAY_SIZE(data)); | |
f903129b | 541 | if (ret < 0) { |
bf035f42 | 542 | dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret); |
f903129b JMC |
543 | goto out; |
544 | } | |
fca1dd03 | 545 | |
f903129b JMC |
546 | max77686_rtc_data_to_tm(data, &tm, info); |
547 | ||
548 | data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT); | |
549 | data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT); | |
550 | data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT); | |
551 | data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK; | |
552 | if (data[RTC_MONTH] & 0xf) | |
553 | data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT); | |
554 | if (data[RTC_YEAR] & info->drv_data->mask) | |
555 | data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT); | |
556 | if (data[RTC_DATE] & 0x1f) | |
557 | data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT); | |
558 | ||
f604c488 LD |
559 | ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC], |
560 | data, ARRAY_SIZE(data)); | |
f903129b | 561 | } |
fca1dd03 | 562 | |
fca1dd03 | 563 | if (ret < 0) { |
bf035f42 | 564 | dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret); |
fca1dd03 JL |
565 | goto out; |
566 | } | |
567 | ||
568 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); | |
569 | out: | |
570 | return ret; | |
571 | } | |
572 | ||
573 | static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
574 | { | |
575 | struct max77686_rtc_info *info = dev_get_drvdata(dev); | |
576 | u8 data[RTC_NR_TIME]; | |
577 | int ret; | |
578 | ||
f903129b | 579 | ret = max77686_rtc_tm_to_data(&alrm->time, data, info); |
fca1dd03 JL |
580 | if (ret < 0) |
581 | return ret; | |
582 | ||
583 | mutex_lock(&info->lock); | |
584 | ||
585 | ret = max77686_rtc_stop_alarm(info); | |
586 | if (ret < 0) | |
587 | goto out; | |
588 | ||
f604c488 | 589 | ret = regmap_bulk_write(info->rtc_regmap, |
90a5698a JMC |
590 | info->drv_data->map[REG_ALARM1_SEC], |
591 | data, ARRAY_SIZE(data)); | |
fca1dd03 JL |
592 | |
593 | if (ret < 0) { | |
bf035f42 | 594 | dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret); |
fca1dd03 JL |
595 | goto out; |
596 | } | |
597 | ||
598 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); | |
599 | if (ret < 0) | |
600 | goto out; | |
601 | ||
602 | if (alrm->enabled) | |
603 | ret = max77686_rtc_start_alarm(info); | |
604 | out: | |
605 | mutex_unlock(&info->lock); | |
606 | return ret; | |
607 | } | |
608 | ||
609 | static int max77686_rtc_alarm_irq_enable(struct device *dev, | |
0b4f8b08 | 610 | unsigned int enabled) |
fca1dd03 JL |
611 | { |
612 | struct max77686_rtc_info *info = dev_get_drvdata(dev); | |
613 | int ret; | |
614 | ||
615 | mutex_lock(&info->lock); | |
616 | if (enabled) | |
617 | ret = max77686_rtc_start_alarm(info); | |
618 | else | |
619 | ret = max77686_rtc_stop_alarm(info); | |
620 | mutex_unlock(&info->lock); | |
621 | ||
622 | return ret; | |
623 | } | |
624 | ||
625 | static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data) | |
626 | { | |
627 | struct max77686_rtc_info *info = data; | |
628 | ||
bf035f42 | 629 | dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq); |
fca1dd03 JL |
630 | |
631 | rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); | |
632 | ||
633 | return IRQ_HANDLED; | |
634 | } | |
635 | ||
636 | static const struct rtc_class_ops max77686_rtc_ops = { | |
637 | .read_time = max77686_rtc_read_time, | |
638 | .set_time = max77686_rtc_set_time, | |
639 | .read_alarm = max77686_rtc_read_alarm, | |
640 | .set_alarm = max77686_rtc_set_alarm, | |
641 | .alarm_irq_enable = max77686_rtc_alarm_irq_enable, | |
642 | }; | |
643 | ||
fca1dd03 JL |
644 | static int max77686_rtc_init_reg(struct max77686_rtc_info *info) |
645 | { | |
646 | u8 data[2]; | |
647 | int ret; | |
648 | ||
649 | /* Set RTC control register : Binary mode, 24hour mdoe */ | |
650 | data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
651 | data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
652 | ||
653 | info->rtc_24hr_mode = 1; | |
654 | ||
f604c488 | 655 | ret = regmap_bulk_write(info->rtc_regmap, |
90a5698a JMC |
656 | info->drv_data->map[REG_RTC_CONTROLM], |
657 | data, ARRAY_SIZE(data)); | |
fca1dd03 | 658 | if (ret < 0) { |
bf035f42 | 659 | dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret); |
fca1dd03 JL |
660 | return ret; |
661 | } | |
662 | ||
663 | ret = max77686_rtc_update(info, MAX77686_RTC_WRITE); | |
664 | return ret; | |
665 | } | |
666 | ||
f3937549 LD |
667 | static const struct regmap_config max77686_rtc_regmap_config = { |
668 | .reg_bits = 8, | |
669 | .val_bits = 8, | |
670 | }; | |
671 | ||
672 | static int max77686_init_rtc_regmap(struct max77686_rtc_info *info) | |
673 | { | |
674 | struct device *parent = info->dev->parent; | |
675 | struct i2c_client *parent_i2c = to_i2c_client(parent); | |
676 | int ret; | |
677 | ||
726fe738 LD |
678 | if (info->drv_data->rtc_irq_from_platform) { |
679 | struct platform_device *pdev = to_platform_device(info->dev); | |
680 | ||
681 | info->rtc_irq = platform_get_irq(pdev, 0); | |
682 | if (info->rtc_irq < 0) { | |
683 | dev_err(info->dev, "Failed to get rtc interrupts: %d\n", | |
684 | info->rtc_irq); | |
685 | return info->rtc_irq; | |
686 | } | |
687 | } else { | |
688 | info->rtc_irq = parent_i2c->irq; | |
689 | } | |
f3937549 LD |
690 | |
691 | info->regmap = dev_get_regmap(parent, NULL); | |
692 | if (!info->regmap) { | |
693 | dev_err(info->dev, "Failed to get rtc regmap\n"); | |
694 | return -ENODEV; | |
695 | } | |
696 | ||
697 | if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) { | |
698 | info->rtc_regmap = info->regmap; | |
699 | goto add_rtc_irq; | |
700 | } | |
701 | ||
702 | info->rtc = i2c_new_dummy(parent_i2c->adapter, | |
703 | info->drv_data->rtc_i2c_addr); | |
704 | if (!info->rtc) { | |
705 | dev_err(info->dev, "Failed to allocate I2C device for RTC\n"); | |
706 | return -ENODEV; | |
707 | } | |
708 | ||
709 | info->rtc_regmap = devm_regmap_init_i2c(info->rtc, | |
710 | &max77686_rtc_regmap_config); | |
711 | if (IS_ERR(info->rtc_regmap)) { | |
712 | ret = PTR_ERR(info->rtc_regmap); | |
713 | dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret); | |
714 | goto err_unregister_i2c; | |
715 | } | |
716 | ||
717 | add_rtc_irq: | |
718 | ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq, | |
719 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT | | |
720 | IRQF_SHARED, 0, info->drv_data->rtc_irq_chip, | |
721 | &info->rtc_irq_data); | |
722 | if (ret < 0) { | |
723 | dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret); | |
724 | goto err_unregister_i2c; | |
725 | } | |
726 | ||
727 | return 0; | |
728 | ||
729 | err_unregister_i2c: | |
730 | if (info->rtc) | |
731 | i2c_unregister_device(info->rtc); | |
732 | return ret; | |
733 | } | |
734 | ||
fca1dd03 JL |
735 | static int max77686_rtc_probe(struct platform_device *pdev) |
736 | { | |
fca1dd03 | 737 | struct max77686_rtc_info *info; |
01ea01b3 | 738 | const struct platform_device_id *id = platform_get_device_id(pdev); |
6f1c1e71 | 739 | int ret; |
fca1dd03 | 740 | |
0f64f853 | 741 | info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info), |
0b4f8b08 | 742 | GFP_KERNEL); |
fca1dd03 JL |
743 | if (!info) |
744 | return -ENOMEM; | |
745 | ||
746 | mutex_init(&info->lock); | |
747 | info->dev = &pdev->dev; | |
01ea01b3 JMC |
748 | info->drv_data = (const struct max77686_rtc_driver_data *) |
749 | id->driver_data; | |
6f1c1e71 | 750 | |
f3937549 LD |
751 | ret = max77686_init_rtc_regmap(info); |
752 | if (ret < 0) | |
753 | return ret; | |
f903129b | 754 | |
fca1dd03 JL |
755 | platform_set_drvdata(pdev, info); |
756 | ||
757 | ret = max77686_rtc_init_reg(info); | |
fca1dd03 JL |
758 | if (ret < 0) { |
759 | dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret); | |
760 | goto err_rtc; | |
761 | } | |
762 | ||
fca1dd03 JL |
763 | device_init_wakeup(&pdev->dev, 1); |
764 | ||
f903129b | 765 | info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name, |
f56950ec | 766 | &max77686_rtc_ops, THIS_MODULE); |
fca1dd03 JL |
767 | |
768 | if (IS_ERR(info->rtc_dev)) { | |
fca1dd03 JL |
769 | ret = PTR_ERR(info->rtc_dev); |
770 | dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); | |
771 | if (ret == 0) | |
772 | ret = -EINVAL; | |
773 | goto err_rtc; | |
774 | } | |
6f1c1e71 | 775 | |
f3937549 | 776 | info->virq = regmap_irq_get_virq(info->rtc_irq_data, |
6f1c1e71 | 777 | MAX77686_RTCIRQ_RTCA1); |
fb166ba1 | 778 | if (info->virq <= 0) { |
ad819039 | 779 | ret = -ENXIO; |
fca1dd03 | 780 | goto err_rtc; |
ad819039 | 781 | } |
fca1dd03 | 782 | |
f3937549 LD |
783 | ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0, |
784 | "rtc-alarm1", info); | |
785 | if (ret < 0) { | |
fca1dd03 JL |
786 | dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", |
787 | info->virq, ret); | |
f3937549 LD |
788 | goto err_rtc; |
789 | } | |
790 | ||
791 | return 0; | |
fca1dd03 | 792 | |
fca1dd03 | 793 | err_rtc: |
f3937549 LD |
794 | regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data); |
795 | if (info->rtc) | |
796 | i2c_unregister_device(info->rtc); | |
797 | ||
fca1dd03 JL |
798 | return ret; |
799 | } | |
800 | ||
f3937549 LD |
801 | static int max77686_rtc_remove(struct platform_device *pdev) |
802 | { | |
803 | struct max77686_rtc_info *info = platform_get_drvdata(pdev); | |
804 | ||
805 | free_irq(info->virq, info); | |
806 | regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data); | |
807 | if (info->rtc) | |
808 | i2c_unregister_device(info->rtc); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
e7f7fc73 DA |
813 | #ifdef CONFIG_PM_SLEEP |
814 | static int max77686_rtc_suspend(struct device *dev) | |
815 | { | |
816 | if (device_may_wakeup(dev)) { | |
817 | struct max77686_rtc_info *info = dev_get_drvdata(dev); | |
818 | ||
819 | return enable_irq_wake(info->virq); | |
820 | } | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int max77686_rtc_resume(struct device *dev) | |
826 | { | |
827 | if (device_may_wakeup(dev)) { | |
828 | struct max77686_rtc_info *info = dev_get_drvdata(dev); | |
829 | ||
830 | return disable_irq_wake(info->virq); | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | #endif | |
836 | ||
837 | static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops, | |
838 | max77686_rtc_suspend, max77686_rtc_resume); | |
839 | ||
fca1dd03 | 840 | static const struct platform_device_id rtc_id[] = { |
01ea01b3 | 841 | { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, }, |
f903129b | 842 | { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, }, |
726fe738 | 843 | { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, }, |
fca1dd03 JL |
844 | {}, |
845 | }; | |
2d0cca0d | 846 | MODULE_DEVICE_TABLE(platform, rtc_id); |
fca1dd03 JL |
847 | |
848 | static struct platform_driver max77686_rtc_driver = { | |
849 | .driver = { | |
850 | .name = "max77686-rtc", | |
e7f7fc73 | 851 | .pm = &max77686_rtc_pm_ops, |
fca1dd03 JL |
852 | }, |
853 | .probe = max77686_rtc_probe, | |
f3937549 | 854 | .remove = max77686_rtc_remove, |
fca1dd03 JL |
855 | .id_table = rtc_id, |
856 | }; | |
857 | ||
0c58ff58 | 858 | module_platform_driver(max77686_rtc_driver); |
fca1dd03 JL |
859 | |
860 | MODULE_DESCRIPTION("Maxim MAX77686 RTC driver"); | |
f5b1d3c5 | 861 | MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>"); |
fca1dd03 | 862 | MODULE_LICENSE("GPL"); |