[linux-block.git] / drivers / rtc / rtc-m48t86.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * ST M48T86 / Dallas DS12887 RTC driver
 * Copyright (c) 2006 Tower Technologies
 *
 * Author: Alessandro Zummo <a.zummo@towertech.it>
 *
 * This drivers only supports the clock running in BCD and 24H mode.
 * If it will be ever adapted to binary and 12H mode, care must be taken
 * to not introduce bugs.
 */

#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/bcd.h>
#include <linux/io.h>

#define M48T86_SEC		0x00
#define M48T86_SECALRM		0x01
#define M48T86_MIN		0x02
#define M48T86_MINALRM		0x03
#define M48T86_HOUR		0x04
#define M48T86_HOURALRM		0x05
#define M48T86_DOW		0x06 /* 1 = sunday */
#define M48T86_DOM		0x07
#define M48T86_MONTH		0x08 /* 1 - 12 */
#define M48T86_YEAR		0x09 /* 0 - 99 */
#define M48T86_A		0x0a
#define M48T86_B		0x0b
#define M48T86_B_SET		BIT(7)
#define M48T86_B_DM		BIT(2)
#define M48T86_B_H24		BIT(1)
#define M48T86_C		0x0c
#define M48T86_D		0x0d
#define M48T86_D_VRT		BIT(7)
#define M48T86_NVRAM(x)		(0x0e + (x))
#define M48T86_NVRAM_LEN	114

struct m48t86_rtc_info {
	void __iomem *index_reg;
	void __iomem *data_reg;
	struct rtc_device *rtc;
};

static unsigned char m48t86_readb(struct device *dev, unsigned long addr)
{
	struct m48t86_rtc_info *info = dev_get_drvdata(dev);
	unsigned char value;

	writeb(addr, info->index_reg);
	value = readb(info->data_reg);

	return value;
}

static void m48t86_writeb(struct device *dev,
			  unsigned char value, unsigned long addr)
{
	struct m48t86_rtc_info *info = dev_get_drvdata(dev);

	writeb(addr, info->index_reg);
	writeb(value, info->data_reg);
}

static int m48t86_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char reg;

	reg = m48t86_readb(dev, M48T86_B);

	if (reg & M48T86_B_DM) {
		/* data (binary) mode */
		tm->tm_sec	= m48t86_readb(dev, M48T86_SEC);
		tm->tm_min	= m48t86_readb(dev, M48T86_MIN);
		tm->tm_hour	= m48t86_readb(dev, M48T86_HOUR) & 0x3f;
		tm->tm_mday	= m48t86_readb(dev, M48T86_DOM);
		/* tm_mon is 0-11 */
		tm->tm_mon	= m48t86_readb(dev, M48T86_MONTH) - 1;
		tm->tm_year	= m48t86_readb(dev, M48T86_YEAR) + 100;
		tm->tm_wday	= m48t86_readb(dev, M48T86_DOW);
	} else {
		/* bcd mode */
		tm->tm_sec	= bcd2bin(m48t86_readb(dev, M48T86_SEC));
		tm->tm_min	= bcd2bin(m48t86_readb(dev, M48T86_MIN));
		tm->tm_hour	= bcd2bin(m48t86_readb(dev, M48T86_HOUR) &
					  0x3f);
		tm->tm_mday	= bcd2bin(m48t86_readb(dev, M48T86_DOM));
		/* tm_mon is 0-11 */
		tm->tm_mon	= bcd2bin(m48t86_readb(dev, M48T86_MONTH)) - 1;
		tm->tm_year	= bcd2bin(m48t86_readb(dev, M48T86_YEAR)) + 100;
		tm->tm_wday	= bcd2bin(m48t86_readb(dev, M48T86_DOW));
	}

	/* correct the hour if the clock is in 12h mode */
	if (!(reg & M48T86_B_H24))
		if (m48t86_readb(dev, M48T86_HOUR) & 0x80)
			tm->tm_hour += 12;

	return 0;
}

static int m48t86_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char reg;

	reg = m48t86_readb(dev, M48T86_B);

	/* update flag and 24h mode */
	reg |= M48T86_B_SET | M48T86_B_H24;
	m48t86_writeb(dev, reg, M48T86_B);

	if (reg & M48T86_B_DM) {
		/* data (binary) mode */
		m48t86_writeb(dev, tm->tm_sec, M48T86_SEC);
		m48t86_writeb(dev, tm->tm_min, M48T86_MIN);
		m48t86_writeb(dev, tm->tm_hour, M48T86_HOUR);
		m48t86_writeb(dev, tm->tm_mday, M48T86_DOM);
		m48t86_writeb(dev, tm->tm_mon + 1, M48T86_MONTH);
		m48t86_writeb(dev, tm->tm_year % 100, M48T86_YEAR);
		m48t86_writeb(dev, tm->tm_wday, M48T86_DOW);
	} else {
		/* bcd mode */
		m48t86_writeb(dev, bin2bcd(tm->tm_sec), M48T86_SEC);
		m48t86_writeb(dev, bin2bcd(tm->tm_min), M48T86_MIN);
		m48t86_writeb(dev, bin2bcd(tm->tm_hour), M48T86_HOUR);
		m48t86_writeb(dev, bin2bcd(tm->tm_mday), M48T86_DOM);
		m48t86_writeb(dev, bin2bcd(tm->tm_mon + 1), M48T86_MONTH);
		m48t86_writeb(dev, bin2bcd(tm->tm_year % 100), M48T86_YEAR);
		m48t86_writeb(dev, bin2bcd(tm->tm_wday), M48T86_DOW);
	}

	/* update ended */
	reg &= ~M48T86_B_SET;
	m48t86_writeb(dev, reg, M48T86_B);

	return 0;
}

static int m48t86_rtc_proc(struct device *dev, struct seq_file *seq)
{
	unsigned char reg;

	reg = m48t86_readb(dev, M48T86_B);

	seq_printf(seq, "mode\t\t: %s\n",
		   (reg & M48T86_B_DM) ? "binary" : "bcd");

	reg = m48t86_readb(dev, M48T86_D);

	seq_printf(seq, "battery\t\t: %s\n",
		   (reg & M48T86_D_VRT) ? "ok" : "exhausted");

	return 0;
}

static const struct rtc_class_ops m48t86_rtc_ops = {
	.read_time	= m48t86_rtc_read_time,
	.set_time	= m48t86_rtc_set_time,
	.proc		= m48t86_rtc_proc,
};

static int m48t86_nvram_read(void *priv, unsigned int off, void *buf,
			     size_t count)
{
	struct device *dev = priv;
	unsigned int i;

	for (i = 0; i < count; i++)
		((u8 *)buf)[i] = m48t86_readb(dev, M48T86_NVRAM(off + i));

	return 0;
}

static int m48t86_nvram_write(void *priv, unsigned int off, void *buf,
			      size_t count)
{
	struct device *dev = priv;
	unsigned int i;

	for (i = 0; i < count; i++)
		m48t86_writeb(dev, ((u8 *)buf)[i], M48T86_NVRAM(off + i));

	return 0;
}

/*
 * The RTC is an optional feature at purchase time on some Technologic Systems
 * boards. Verify that it actually exists by checking if the last two bytes
 * of the NVRAM can be changed.
 *
 * This is based on the method used in their rtc7800.c example.
 */
static bool m48t86_verify_chip(struct platform_device *pdev)
{
	unsigned int offset0 = M48T86_NVRAM(M48T86_NVRAM_LEN - 2);
	unsigned int offset1 = M48T86_NVRAM(M48T86_NVRAM_LEN - 1);
	unsigned char tmp0, tmp1;

	tmp0 = m48t86_readb(&pdev->dev, offset0);
	tmp1 = m48t86_readb(&pdev->dev, offset1);

	m48t86_writeb(&pdev->dev, 0x00, offset0);
	m48t86_writeb(&pdev->dev, 0x55, offset1);
	if (m48t86_readb(&pdev->dev, offset1) == 0x55) {
		m48t86_writeb(&pdev->dev, 0xaa, offset1);
		if (m48t86_readb(&pdev->dev, offset1) == 0xaa &&
		    m48t86_readb(&pdev->dev, offset0) == 0x00) {
			m48t86_writeb(&pdev->dev, tmp0, offset0);
			m48t86_writeb(&pdev->dev, tmp1, offset1);

			return true;
		}
	}
	return false;
}

static int m48t86_rtc_probe(struct platform_device *pdev)
{
	struct m48t86_rtc_info *info;
	unsigned char reg;
	int err;
	struct nvmem_config m48t86_nvmem_cfg = {
		.name = "m48t86_nvram",
		.word_size = 1,
		.stride = 1,
		.size = M48T86_NVRAM_LEN,
		.reg_read = m48t86_nvram_read,
		.reg_write = m48t86_nvram_write,
		.priv = &pdev->dev,
	};

	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

	info->index_reg = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(info->index_reg))
		return PTR_ERR(info->index_reg);

	info->data_reg = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(info->data_reg))
		return PTR_ERR(info->data_reg);

	dev_set_drvdata(&pdev->dev, info);

	if (!m48t86_verify_chip(pdev)) {
		dev_info(&pdev->dev, "RTC not present\n");
		return -ENODEV;
	}

	info->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(info->rtc))
		return PTR_ERR(info->rtc);

	info->rtc->ops = &m48t86_rtc_ops;

	err = devm_rtc_register_device(info->rtc);
	if (err)
		return err;

	devm_rtc_nvmem_register(info->rtc, &m48t86_nvmem_cfg);

	/* read battery status */
	reg = m48t86_readb(&pdev->dev, M48T86_D);
	dev_info(&pdev->dev, "battery %s\n",
		 (reg & M48T86_D_VRT) ? "ok" : "exhausted");

	return 0;
}

static struct platform_driver m48t86_rtc_platform_driver = {
	.driver		= {
		.name	= "rtc-m48t86",
	},
	.probe		= m48t86_rtc_probe,
};

module_platform_driver(m48t86_rtc_platform_driver);

MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
MODULE_DESCRIPTION("M48T86 RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-m48t86");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1d98af87 AZ	2	/*
	3	* ST M48T86 / Dallas DS12887 RTC driver
	4	* Copyright (c) 2006 Tower Technologies
	5	*
	6	* Author: Alessandro Zummo <a.zummo@towertech.it>
	7	*
1d98af87 AZ	8	* This drivers only supports the clock running in BCD and 24H mode.
	9	* If it will be ever adapted to binary and 12H mode, care must be taken
	10	* to not introduce bugs.
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/rtc.h>
	15	#include <linux/platform_device.h>
1d98af87	16	#include <linux/bcd.h>
8057c86d	17	#include <linux/io.h>
1d98af87	18
68b54f47 HS	19	#define M48T86_SEC 0x00
	20	#define M48T86_SECALRM 0x01
	21	#define M48T86_MIN 0x02
	22	#define M48T86_MINALRM 0x03
	23	#define M48T86_HOUR 0x04
	24	#define M48T86_HOURALRM 0x05
	25	#define M48T86_DOW 0x06 /* 1 = sunday */
	26	#define M48T86_DOM 0x07
	27	#define M48T86_MONTH 0x08 /* 1 - 12 */
	28	#define M48T86_YEAR 0x09 /* 0 - 99 */
	29	#define M48T86_A 0x0a
	30	#define M48T86_B 0x0b
	31	#define M48T86_B_SET BIT(7)
	32	#define M48T86_B_DM BIT(2)
	33	#define M48T86_B_H24 BIT(1)
	34	#define M48T86_C 0x0c
	35	#define M48T86_D 0x0d
	36	#define M48T86_D_VRT BIT(7)
b180cf8b HS	37	#define M48T86_NVRAM(x) (0x0e + (x))
b180cf8b HS	38	#define M48T86_NVRAM_LEN 114
1d98af87	39
8057c86d HS	40	struct m48t86_rtc_info {
	41	void __iomem *index_reg;
	42	void __iomem *data_reg;
	43	struct rtc_device *rtc;
8057c86d HS	44	};
	45
	46	static unsigned char m48t86_readb(struct device *dev, unsigned long addr)
	47	{
	48	struct m48t86_rtc_info *info = dev_get_drvdata(dev);
	49	unsigned char value;
	50
0500ce58 HS	51	writeb(addr, info->index_reg);
	52	value = readb(info->data_reg);
	53
8057c86d HS	54	return value;
	55	}
	56
	57	static void m48t86_writeb(struct device *dev,
	58	unsigned char value, unsigned long addr)
	59	{
	60	struct m48t86_rtc_info *info = dev_get_drvdata(dev);
	61
0500ce58 HS	62	writeb(addr, info->index_reg);
0500ce58 HS	63	writeb(value, info->data_reg);
8057c86d HS	64	}
8057c86d HS	65
1d98af87 AZ	66	static int m48t86_rtc_read_time(struct device dev, struct rtc_time tm)
	67	{
	68	unsigned char reg;
1d98af87	69
8057c86d	70	reg = m48t86_readb(dev, M48T86_B);
1d98af87	71
68b54f47	72	if (reg & M48T86_B_DM) {
1d98af87	73	/* data (binary) mode */
8057c86d HS	74	tm->tm_sec = m48t86_readb(dev, M48T86_SEC);
	75	tm->tm_min = m48t86_readb(dev, M48T86_MIN);
	76	tm->tm_hour = m48t86_readb(dev, M48T86_HOUR) & 0x3f;
	77	tm->tm_mday = m48t86_readb(dev, M48T86_DOM);
1d98af87	78	/* tm_mon is 0-11 */
8057c86d HS	79	tm->tm_mon = m48t86_readb(dev, M48T86_MONTH) - 1;
	80	tm->tm_year = m48t86_readb(dev, M48T86_YEAR) + 100;
	81	tm->tm_wday = m48t86_readb(dev, M48T86_DOW);
1d98af87 AZ	82	} else {
1d98af87 AZ	83	/* bcd mode */
8057c86d HS	84	tm->tm_sec = bcd2bin(m48t86_readb(dev, M48T86_SEC));
	85	tm->tm_min = bcd2bin(m48t86_readb(dev, M48T86_MIN));
	86	tm->tm_hour = bcd2bin(m48t86_readb(dev, M48T86_HOUR) &
	87	0x3f);
	88	tm->tm_mday = bcd2bin(m48t86_readb(dev, M48T86_DOM));
1d98af87	89	/* tm_mon is 0-11 */
8057c86d HS	90	tm->tm_mon = bcd2bin(m48t86_readb(dev, M48T86_MONTH)) - 1;
	91	tm->tm_year = bcd2bin(m48t86_readb(dev, M48T86_YEAR)) + 100;
	92	tm->tm_wday = bcd2bin(m48t86_readb(dev, M48T86_DOW));
1d98af87 AZ	93	}
	94
	95	/* correct the hour if the clock is in 12h mode */
68b54f47	96	if (!(reg & M48T86_B_H24))
8057c86d	97	if (m48t86_readb(dev, M48T86_HOUR) & 0x80)
1d98af87 AZ	98	tm->tm_hour += 12;
1d98af87 AZ	99
22652ba7	100	return 0;
1d98af87 AZ	101	}
	102
	103	static int m48t86_rtc_set_time(struct device dev, struct rtc_time tm)
	104	{
	105	unsigned char reg;
1d98af87	106
8057c86d	107	reg = m48t86_readb(dev, M48T86_B);
1d98af87 AZ	108
1d98af87 AZ	109	/* update flag and 24h mode */
68b54f47	110	reg \|= M48T86_B_SET \| M48T86_B_H24;
8057c86d	111	m48t86_writeb(dev, reg, M48T86_B);
1d98af87	112
68b54f47	113	if (reg & M48T86_B_DM) {
1d98af87	114	/* data (binary) mode */
8057c86d HS	115	m48t86_writeb(dev, tm->tm_sec, M48T86_SEC);
	116	m48t86_writeb(dev, tm->tm_min, M48T86_MIN);
	117	m48t86_writeb(dev, tm->tm_hour, M48T86_HOUR);
	118	m48t86_writeb(dev, tm->tm_mday, M48T86_DOM);
	119	m48t86_writeb(dev, tm->tm_mon + 1, M48T86_MONTH);
	120	m48t86_writeb(dev, tm->tm_year % 100, M48T86_YEAR);
	121	m48t86_writeb(dev, tm->tm_wday, M48T86_DOW);
1d98af87 AZ	122	} else {
1d98af87 AZ	123	/* bcd mode */
8057c86d HS	124	m48t86_writeb(dev, bin2bcd(tm->tm_sec), M48T86_SEC);
	125	m48t86_writeb(dev, bin2bcd(tm->tm_min), M48T86_MIN);
	126	m48t86_writeb(dev, bin2bcd(tm->tm_hour), M48T86_HOUR);
	127	m48t86_writeb(dev, bin2bcd(tm->tm_mday), M48T86_DOM);
	128	m48t86_writeb(dev, bin2bcd(tm->tm_mon + 1), M48T86_MONTH);
	129	m48t86_writeb(dev, bin2bcd(tm->tm_year % 100), M48T86_YEAR);
	130	m48t86_writeb(dev, bin2bcd(tm->tm_wday), M48T86_DOW);
1d98af87 AZ	131	}
	132
	133	/* update ended */
68b54f47	134	reg &= ~M48T86_B_SET;
8057c86d	135	m48t86_writeb(dev, reg, M48T86_B);
1d98af87 AZ	136
	137	return 0;
	138	}
	139
	140	static int m48t86_rtc_proc(struct device dev, struct seq_file seq)
	141	{
	142	unsigned char reg;
1d98af87	143
8057c86d	144	reg = m48t86_readb(dev, M48T86_B);
1d98af87	145
1d98af87	146	seq_printf(seq, "mode\t\t: %s\n",
68b54f47	147	(reg & M48T86_B_DM) ? "binary" : "bcd");
1d98af87	148
8057c86d	149	reg = m48t86_readb(dev, M48T86_D);
1d98af87 AZ	150
1d98af87 AZ	151	seq_printf(seq, "battery\t\t: %s\n",
68b54f47	152	(reg & M48T86_D_VRT) ? "ok" : "exhausted");
1d98af87 AZ	153
	154	return 0;
	155	}
	156
ff8371ac	157	static const struct rtc_class_ops m48t86_rtc_ops = {
1d98af87 AZ	158	.read_time = m48t86_rtc_read_time,
	159	.set_time = m48t86_rtc_set_time,
	160	.proc = m48t86_rtc_proc,
	161	};
	162
f8033aab AB	163	static int m48t86_nvram_read(void priv, unsigned int off, void buf,
f8033aab AB	164	size_t count)
b180cf8b	165	{
f8033aab	166	struct device *dev = priv;
b180cf8b HS	167	unsigned int i;
	168
	169	for (i = 0; i < count; i++)
f8033aab	170	((u8 *)buf)[i] = m48t86_readb(dev, M48T86_NVRAM(off + i));
b180cf8b	171
f8033aab	172	return 0;
b180cf8b HS	173	}
b180cf8b HS	174
f8033aab AB	175	static int m48t86_nvram_write(void priv, unsigned int off, void buf,
f8033aab AB	176	size_t count)
b180cf8b	177	{
f8033aab	178	struct device *dev = priv;
b180cf8b HS	179	unsigned int i;
	180
	181	for (i = 0; i < count; i++)
f8033aab	182	m48t86_writeb(dev, ((u8 *)buf)[i], M48T86_NVRAM(off + i));
b180cf8b	183
f8033aab	184	return 0;
b180cf8b HS	185	}
b180cf8b HS	186
3ea07127 HS	187	/*
	188	* The RTC is an optional feature at purchase time on some Technologic Systems
	189	* boards. Verify that it actually exists by checking if the last two bytes
	190	* of the NVRAM can be changed.
	191	*
	192	* This is based on the method used in their rtc7800.c example.
	193	*/
	194	static bool m48t86_verify_chip(struct platform_device *pdev)
	195	{
	196	unsigned int offset0 = M48T86_NVRAM(M48T86_NVRAM_LEN - 2);
	197	unsigned int offset1 = M48T86_NVRAM(M48T86_NVRAM_LEN - 1);
	198	unsigned char tmp0, tmp1;
	199
	200	tmp0 = m48t86_readb(&pdev->dev, offset0);
	201	tmp1 = m48t86_readb(&pdev->dev, offset1);
	202
	203	m48t86_writeb(&pdev->dev, 0x00, offset0);
	204	m48t86_writeb(&pdev->dev, 0x55, offset1);
	205	if (m48t86_readb(&pdev->dev, offset1) == 0x55) {
	206	m48t86_writeb(&pdev->dev, 0xaa, offset1);
	207	if (m48t86_readb(&pdev->dev, offset1) == 0xaa &&
	208	m48t86_readb(&pdev->dev, offset0) == 0x00) {
	209	m48t86_writeb(&pdev->dev, tmp0, offset0);
	210	m48t86_writeb(&pdev->dev, tmp1, offset1);
	211
	212	return true;
	213	}
	214	}
	215	return false;
	216	}
	217
8057c86d	218	static int m48t86_rtc_probe(struct platform_device *pdev)
1d98af87	219	{
8057c86d	220	struct m48t86_rtc_info *info;
1d98af87	221	unsigned char reg;
5508c725	222	int err;
e3f51c0d AB	223	struct nvmem_config m48t86_nvmem_cfg = {
	224	.name = "m48t86_nvram",
	225	.word_size = 1,
	226	.stride = 1,
	227	.size = M48T86_NVRAM_LEN,
	228	.reg_read = m48t86_nvram_read,
	229	.reg_write = m48t86_nvram_write,
	230	.priv = &pdev->dev,
	231	};
d5b6bb0a	232
8057c86d HS	233	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
	234	if (!info)
	235	return -ENOMEM;
	236
89576beb	237	info->index_reg = devm_platform_ioremap_resource(pdev, 0);
0500ce58 HS	238	if (IS_ERR(info->index_reg))
	239	return PTR_ERR(info->index_reg);
	240
89576beb	241	info->data_reg = devm_platform_ioremap_resource(pdev, 1);
0500ce58 HS	242	if (IS_ERR(info->data_reg))
0500ce58 HS	243	return PTR_ERR(info->data_reg);
1d98af87	244
8057c86d	245	dev_set_drvdata(&pdev->dev, info);
1d98af87	246
3ea07127 HS	247	if (!m48t86_verify_chip(pdev)) {
	248	dev_info(&pdev->dev, "RTC not present\n");
	249	return -ENODEV;
	250	}
	251
5508c725	252	info->rtc = devm_rtc_allocate_device(&pdev->dev);
8057c86d HS	253	if (IS_ERR(info->rtc))
8057c86d HS	254	return PTR_ERR(info->rtc);
1d98af87	255
5508c725	256	info->rtc->ops = &m48t86_rtc_ops;
f8033aab	257
fdcfd854	258	err = devm_rtc_register_device(info->rtc);
5508c725 AB	259	if (err)
	260	return err;
	261
3a905c2d	262	devm_rtc_nvmem_register(info->rtc, &m48t86_nvmem_cfg);
3c1bb61f	263
1d98af87	264	/* read battery status */
8057c86d HS	265	reg = m48t86_readb(&pdev->dev, M48T86_D);
8057c86d HS	266	dev_info(&pdev->dev, "battery %s\n",
68b54f47	267	(reg & M48T86_D_VRT) ? "ok" : "exhausted");
1d98af87 AZ	268
	269	return 0;
	270	}
	271
1d98af87 AZ	272	static struct platform_driver m48t86_rtc_platform_driver = {
	273	.driver = {
	274	.name = "rtc-m48t86",
1d98af87 AZ	275	},
1d98af87 AZ	276	.probe = m48t86_rtc_probe,
1d98af87 AZ	277	};
1d98af87 AZ	278
0c4eae66	279	module_platform_driver(m48t86_rtc_platform_driver);
1d98af87 AZ	280
	281	MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
	282	MODULE_DESCRIPTION("M48T86 RTC driver");
	283	MODULE_LICENSE("GPL");
ad28a07b	284	MODULE_ALIAS("platform:rtc-m48t86");