[linux-block.git] / drivers / rtc / rtc-m48t59.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * ST M48T59 RTC driver
 *
 * Copyright (c) 2007 Wind River Systems, Inc.
 *
 * Author: Mark Zhan <rongkai.zhan@windriver.com>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/rtc/m48t59.h>
#include <linux/bcd.h>
#include <linux/slab.h>

#ifndef NO_IRQ
#define NO_IRQ	(-1)
#endif

#define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg))
#define M48T59_WRITE(val, reg) \
	(pdata->write_byte(dev, pdata->offset + reg, val))

#define M48T59_SET_BITS(mask, reg)	\
	M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg))
#define M48T59_CLEAR_BITS(mask, reg)	\
	M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg))

struct m48t59_private {
	void __iomem *ioaddr;
	int irq;
	struct rtc_device *rtc;
	spinlock_t lock; /* serialize the NVRAM and RTC access */
};

/*
 * This is the generic access method when the chip is memory-mapped
 */
static void
m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
{
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);

	writeb(val, m48t59->ioaddr+ofs);
}

static u8
m48t59_mem_readb(struct device *dev, u32 ofs)
{
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);

	return readb(m48t59->ioaddr+ofs);
}

/*
 * NOTE: M48T59 only uses BCD mode
 */
static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;
	u8 val;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the READ command */
	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);

	tm->tm_year	= bcd2bin(M48T59_READ(M48T59_YEAR));
	/* tm_mon is 0-11 */
	tm->tm_mon	= bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
	tm->tm_mday	= bcd2bin(M48T59_READ(M48T59_MDAY));

	val = M48T59_READ(M48T59_WDAY);
	if ((pdata->type == M48T59RTC_TYPE_M48T59) &&
	    (val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
		dev_dbg(dev, "Century bit is enabled\n");
		tm->tm_year += 100;	/* one century */
	}
#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	tm->tm_year += 68;
#endif

	tm->tm_wday	= bcd2bin(val & 0x07);
	tm->tm_hour	= bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F);
	tm->tm_min	= bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F);
	tm->tm_sec	= bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F);

	/* Clear the READ bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	dev_dbg(dev, "RTC read time %ptR\n", tm);
	return 0;
}

static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;
	u8 val = 0;
	int year = tm->tm_year;

#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	year -= 68;
#endif

	dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
		year + 1900, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);

	if (year < 0)
		return -EINVAL;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the WRITE command */
	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);

	M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC);
	M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN);
	M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR);
	M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY);
	/* tm_mon is 0-11 */
	M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
	M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR);

	if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100))
		val = (M48T59_WDAY_CEB | M48T59_WDAY_CB);
	val |= (bin2bcd(tm->tm_wday) & 0x07);
	M48T59_WRITE(val, M48T59_WDAY);

	/* Clear the WRITE bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);
	return 0;
}

/*
 * Read alarm time and date in RTC
 */
static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	unsigned long flags;
	u8 val;

	/* If no irq, we don't support ALARM */
	if (m48t59->irq == NO_IRQ)
		return -EIO;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the READ command */
	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);

	tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	tm->tm_year += 68;
#endif
	/* tm_mon is 0-11 */
	tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;

	val = M48T59_READ(M48T59_WDAY);
	if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
		tm->tm_year += 100;	/* one century */

	tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE));
	tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR));
	tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN));
	tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC));

	/* Clear the READ bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	dev_dbg(dev, "RTC read alarm time %ptR\n", tm);
	return rtc_valid_tm(tm);
}

/*
 * Set alarm time and date in RTC
 */
static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	u8 mday, hour, min, sec;
	unsigned long flags;
	int year = tm->tm_year;

#ifdef CONFIG_SPARC
	/* Sun SPARC machines count years since 1968 */
	year -= 68;
#endif

	/* If no irq, we don't support ALARM */
	if (m48t59->irq == NO_IRQ)
		return -EIO;

	if (year < 0)
		return -EINVAL;

	/*
	 * 0xff means "always match"
	 */
	mday = tm->tm_mday;
	mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
	if (mday == 0xff)
		mday = M48T59_READ(M48T59_MDAY);

	hour = tm->tm_hour;
	hour = (hour < 24) ? bin2bcd(hour) : 0x00;

	min = tm->tm_min;
	min = (min < 60) ? bin2bcd(min) : 0x00;

	sec = tm->tm_sec;
	sec = (sec < 60) ? bin2bcd(sec) : 0x00;

	spin_lock_irqsave(&m48t59->lock, flags);
	/* Issue the WRITE command */
	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);

	M48T59_WRITE(mday, M48T59_ALARM_DATE);
	M48T59_WRITE(hour, M48T59_ALARM_HOUR);
	M48T59_WRITE(min, M48T59_ALARM_MIN);
	M48T59_WRITE(sec, M48T59_ALARM_SEC);

	/* Clear the WRITE bit */
	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
		year + 1900, tm->tm_mon, tm->tm_mday,
		tm->tm_hour, tm->tm_min, tm->tm_sec);
	return 0;
}

/*
 * Handle commands from user-space
 */
static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;

	spin_lock_irqsave(&m48t59->lock, flags);
	if (enabled)
		M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
	else
		M48T59_WRITE(0x00, M48T59_INTR);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	return 0;
}

static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	unsigned long flags;
	u8 val;

	spin_lock_irqsave(&m48t59->lock, flags);
	val = M48T59_READ(M48T59_FLAGS);
	spin_unlock_irqrestore(&m48t59->lock, flags);

	seq_printf(seq, "battery\t\t: %s\n",
		 (val & M48T59_FLAGS_BF) ? "low" : "normal");
	return 0;
}

/*
 * IRQ handler for the RTC
 */
static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
{
	struct device *dev = (struct device *)dev_id;
	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
	u8 event;

	spin_lock(&m48t59->lock);
	event = M48T59_READ(M48T59_FLAGS);
	spin_unlock(&m48t59->lock);

	if (event & M48T59_FLAGS_AF) {
		rtc_update_irq(m48t59->rtc, 1, (RTC_AF | RTC_IRQF));
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static const struct rtc_class_ops m48t59_rtc_ops = {
	.read_time	= m48t59_rtc_read_time,
	.set_time	= m48t59_rtc_set_time,
	.read_alarm	= m48t59_rtc_readalarm,
	.set_alarm	= m48t59_rtc_setalarm,
	.proc		= m48t59_rtc_proc,
	.alarm_irq_enable = m48t59_rtc_alarm_irq_enable,
};

static const struct rtc_class_ops m48t02_rtc_ops = {
	.read_time	= m48t59_rtc_read_time,
	.set_time	= m48t59_rtc_set_time,
};

static int m48t59_nvram_read(void *priv, unsigned int offset, void *val,
			     size_t size)
{
	struct platform_device *pdev = priv;
	struct device *dev = &pdev->dev;
	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	ssize_t cnt = 0;
	unsigned long flags;
	u8 *buf = val;

	spin_lock_irqsave(&m48t59->lock, flags);

	for (; cnt < size; cnt++)
		*buf++ = M48T59_READ(cnt);

	spin_unlock_irqrestore(&m48t59->lock, flags);

	return 0;
}

static int m48t59_nvram_write(void *priv, unsigned int offset, void *val,
			      size_t size)
{
	struct platform_device *pdev = priv;
	struct device *dev = &pdev->dev;
	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	ssize_t cnt = 0;
	unsigned long flags;
	u8 *buf = val;

	spin_lock_irqsave(&m48t59->lock, flags);

	for (; cnt < size; cnt++)
		M48T59_WRITE(*buf++, cnt);

	spin_unlock_irqrestore(&m48t59->lock, flags);

	return 0;
}

static int m48t59_rtc_probe(struct platform_device *pdev)
{
	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
	struct m48t59_private *m48t59 = NULL;
	struct resource *res;
	int ret = -ENOMEM;
	const struct rtc_class_ops *ops;
	struct nvmem_config nvmem_cfg = {
		.name = "m48t59-",
		.word_size = 1,
		.stride = 1,
		.reg_read = m48t59_nvram_read,
		.reg_write = m48t59_nvram_write,
		.priv = pdev,
	};

	/* This chip could be memory-mapped or I/O-mapped */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		res = platform_get_resource(pdev, IORESOURCE_IO, 0);
		if (!res)
			return -EINVAL;
	}

	if (res->flags & IORESOURCE_IO) {
		/* If we are I/O-mapped, the platform should provide
		 * the operations accessing chip registers.
		 */
		if (!pdata || !pdata->write_byte || !pdata->read_byte)
			return -EINVAL;
	} else if (res->flags & IORESOURCE_MEM) {
		/* we are memory-mapped */
		if (!pdata) {
			pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata),
						GFP_KERNEL);
			if (!pdata)
				return -ENOMEM;
			/* Ensure we only kmalloc platform data once */
			pdev->dev.platform_data = pdata;
		}
		if (!pdata->type)
			pdata->type = M48T59RTC_TYPE_M48T59;

		/* Try to use the generic memory read/write ops */
		if (!pdata->write_byte)
			pdata->write_byte = m48t59_mem_writeb;
		if (!pdata->read_byte)
			pdata->read_byte = m48t59_mem_readb;
	}

	m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL);
	if (!m48t59)
		return -ENOMEM;

	m48t59->ioaddr = pdata->ioaddr;

	if (!m48t59->ioaddr) {
		/* ioaddr not mapped externally */
		m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start,
						resource_size(res));
		if (!m48t59->ioaddr)
			return ret;
	}

	/* Try to get irq number. We also can work in
	 * the mode without IRQ.
	 */
	m48t59->irq = platform_get_irq(pdev, 0);
	if (m48t59->irq <= 0)
		m48t59->irq = NO_IRQ;

	if (m48t59->irq != NO_IRQ) {
		ret = devm_request_irq(&pdev->dev, m48t59->irq,
				m48t59_rtc_interrupt, IRQF_SHARED,
				"rtc-m48t59", &pdev->dev);
		if (ret)
			return ret;
	}
	switch (pdata->type) {
	case M48T59RTC_TYPE_M48T59:
		ops = &m48t59_rtc_ops;
		pdata->offset = 0x1ff0;
		break;
	case M48T59RTC_TYPE_M48T02:
		ops = &m48t02_rtc_ops;
		pdata->offset = 0x7f0;
		break;
	case M48T59RTC_TYPE_M48T08:
		ops = &m48t02_rtc_ops;
		pdata->offset = 0x1ff0;
		break;
	default:
		dev_err(&pdev->dev, "Unknown RTC type\n");
		return -ENODEV;
	}

	spin_lock_init(&m48t59->lock);
	platform_set_drvdata(pdev, m48t59);

	m48t59->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(m48t59->rtc))
		return PTR_ERR(m48t59->rtc);

	m48t59->rtc->nvram_old_abi = true;
	m48t59->rtc->ops = ops;

	nvmem_cfg.size = pdata->offset;
	ret = rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
	if (ret)
		return ret;

	ret = rtc_register_device(m48t59->rtc);
	if (ret)
		return ret;

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:rtc-m48t59");

static struct platform_driver m48t59_rtc_driver = {
	.driver		= {
		.name	= "rtc-m48t59",
	},
	.probe		= m48t59_rtc_probe,
};

module_platform_driver(m48t59_rtc_driver);

MODULE_AUTHOR("Mark Zhan <rongkai.zhan@windriver.com>");
MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
2e774c7c MZ	2	/*
	3	* ST M48T59 RTC driver
	4	*
	5	* Copyright (c) 2007 Wind River Systems, Inc.
	6	*
	7	* Author: Mark Zhan <rongkai.zhan@windriver.com>
2e774c7c MZ	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/init.h>
	13	#include <linux/io.h>
	14	#include <linux/device.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/rtc.h>
	17	#include <linux/rtc/m48t59.h>
	18	#include <linux/bcd.h>
5a0e3ad6	19	#include <linux/slab.h>
2e774c7c MZ	20
	21	#ifndef NO_IRQ
	22	#define NO_IRQ (-1)
	23	#endif
	24
94fe7424 KH	25	#define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg))
	26	#define M48T59_WRITE(val, reg) \
	27	(pdata->write_byte(dev, pdata->offset + reg, val))
2e774c7c MZ	28
	29	#define M48T59_SET_BITS(mask, reg) \
	30	M48T59_WRITE((M48T59_READ(reg) \| (mask)), (reg))
	31	#define M48T59_CLEAR_BITS(mask, reg) \
	32	M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg))
	33
	34	struct m48t59_private {
	35	void __iomem *ioaddr;
0439208a	36	int irq;
2e774c7c MZ	37	struct rtc_device *rtc;
	38	spinlock_t lock; /* serialize the NVRAM and RTC access */
	39	};
	40
	41	/*
	42	* This is the generic access method when the chip is memory-mapped
	43	*/
	44	static void
	45	m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
	46	{
85368bb9	47	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	48
	49	writeb(val, m48t59->ioaddr+ofs);
	50	}
	51
	52	static u8
	53	m48t59_mem_readb(struct device *dev, u32 ofs)
	54	{
85368bb9	55	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	56
	57	return readb(m48t59->ioaddr+ofs);
	58	}
	59
	60	/*
	61	* NOTE: M48T59 only uses BCD mode
	62	*/
	63	static int m48t59_rtc_read_time(struct device dev, struct rtc_time tm)
	64	{
85368bb9 WS	65	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	66	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	67	unsigned long flags;
	68	u8 val;
	69
	70	spin_lock_irqsave(&m48t59->lock, flags);
	71	/* Issue the READ command */
	72	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	73
fe20ba70	74	tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
2e774c7c	75	/* tm_mon is 0-11 */
fe20ba70 AB	76	tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
fe20ba70 AB	77	tm->tm_mday = bcd2bin(M48T59_READ(M48T59_MDAY));
2e774c7c MZ	78
2e774c7c MZ	79	val = M48T59_READ(M48T59_WDAY);
833be4e1 RR	80	if ((pdata->type == M48T59RTC_TYPE_M48T59) &&
833be4e1 RR	81	(val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
2e774c7c MZ	82	dev_dbg(dev, "Century bit is enabled\n");
	83	tm->tm_year += 100; /* one century */
	84	}
12a9ee3c KH	85	#ifdef CONFIG_SPARC
	86	/* Sun SPARC machines count years since 1968 */
	87	tm->tm_year += 68;
	88	#endif
2e774c7c	89
fe20ba70 AB	90	tm->tm_wday = bcd2bin(val & 0x07);
	91	tm->tm_hour = bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F);
	92	tm->tm_min = bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F);
	93	tm->tm_sec = bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F);
2e774c7c MZ	94
	95	/* Clear the READ bit */
	96	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	97	spin_unlock_irqrestore(&m48t59->lock, flags);
	98
ad78343e	99	dev_dbg(dev, "RTC read time %ptR\n", tm);
22652ba7	100	return 0;
2e774c7c MZ	101	}
	102
	103	static int m48t59_rtc_set_time(struct device dev, struct rtc_time tm)
	104	{
85368bb9 WS	105	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	106	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	107	unsigned long flags;
2e774c7c MZ	108	u8 val = 0;
12a9ee3c KH	109	int year = tm->tm_year;
	110
	111	#ifdef CONFIG_SPARC
	112	/* Sun SPARC machines count years since 1968 */
	113	year -= 68;
	114	#endif
2e774c7c MZ	115
2e774c7c MZ	116	dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
12a9ee3c	117	year + 1900, tm->tm_mon, tm->tm_mday,
2e774c7c MZ	118	tm->tm_hour, tm->tm_min, tm->tm_sec);
2e774c7c MZ	119
12a9ee3c KH	120	if (year < 0)
	121	return -EINVAL;
	122
2e774c7c MZ	123	spin_lock_irqsave(&m48t59->lock, flags);
	124	/* Issue the WRITE command */
	125	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	126
fe20ba70 AB	127	M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC);
	128	M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN);
	129	M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR);
	130	M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY);
2e774c7c	131	/* tm_mon is 0-11 */
fe20ba70	132	M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
12a9ee3c	133	M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR);
2e774c7c	134
12a9ee3c	135	if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100))
2e774c7c	136	val = (M48T59_WDAY_CEB \| M48T59_WDAY_CB);
fe20ba70	137	val \|= (bin2bcd(tm->tm_wday) & 0x07);
2e774c7c MZ	138	M48T59_WRITE(val, M48T59_WDAY);
	139
	140	/* Clear the WRITE bit */
	141	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	142	spin_unlock_irqrestore(&m48t59->lock, flags);
	143	return 0;
	144	}
	145
	146	/*
	147	* Read alarm time and date in RTC
	148	*/
	149	static int m48t59_rtc_readalarm(struct device dev, struct rtc_wkalrm alrm)
	150	{
85368bb9 WS	151	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	152	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	153	struct rtc_time *tm = &alrm->time;
	154	unsigned long flags;
	155	u8 val;
	156
	157	/* If no irq, we don't support ALARM */
	158	if (m48t59->irq == NO_IRQ)
	159	return -EIO;
	160
	161	spin_lock_irqsave(&m48t59->lock, flags);
	162	/* Issue the READ command */
	163	M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	164
fe20ba70	165	tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
12a9ee3c KH	166	#ifdef CONFIG_SPARC
	167	/* Sun SPARC machines count years since 1968 */
	168	tm->tm_year += 68;
	169	#endif
2e774c7c	170	/* tm_mon is 0-11 */
fe20ba70	171	tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
2e774c7c MZ	172
	173	val = M48T59_READ(M48T59_WDAY);
	174	if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
	175	tm->tm_year += 100; /* one century */
	176
fe20ba70 AB	177	tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE));
	178	tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR));
	179	tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN));
	180	tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC));
2e774c7c MZ	181
	182	/* Clear the READ bit */
	183	M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
	184	spin_unlock_irqrestore(&m48t59->lock, flags);
	185
ad78343e	186	dev_dbg(dev, "RTC read alarm time %ptR\n", tm);
caf1e106	187	return rtc_valid_tm(tm);
2e774c7c MZ	188	}
	189
	190	/*
	191	* Set alarm time and date in RTC
	192	*/
	193	static int m48t59_rtc_setalarm(struct device dev, struct rtc_wkalrm alrm)
	194	{
85368bb9 WS	195	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	196	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	197	struct rtc_time *tm = &alrm->time;
	198	u8 mday, hour, min, sec;
	199	unsigned long flags;
12a9ee3c KH	200	int year = tm->tm_year;
	201
	202	#ifdef CONFIG_SPARC
	203	/* Sun SPARC machines count years since 1968 */
	204	year -= 68;
	205	#endif
2e774c7c MZ	206
	207	/* If no irq, we don't support ALARM */
	208	if (m48t59->irq == NO_IRQ)
	209	return -EIO;
	210
12a9ee3c KH	211	if (year < 0)
	212	return -EINVAL;
	213
2e774c7c MZ	214	/*
	215	* 0xff means "always match"
	216	*/
	217	mday = tm->tm_mday;
fe20ba70	218	mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
2e774c7c MZ	219	if (mday == 0xff)
	220	mday = M48T59_READ(M48T59_MDAY);
	221
	222	hour = tm->tm_hour;
fe20ba70	223	hour = (hour < 24) ? bin2bcd(hour) : 0x00;
2e774c7c MZ	224
2e774c7c MZ	225	min = tm->tm_min;
fe20ba70	226	min = (min < 60) ? bin2bcd(min) : 0x00;
2e774c7c MZ	227
2e774c7c MZ	228	sec = tm->tm_sec;
fe20ba70	229	sec = (sec < 60) ? bin2bcd(sec) : 0x00;
2e774c7c MZ	230
	231	spin_lock_irqsave(&m48t59->lock, flags);
	232	/* Issue the WRITE command */
	233	M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	234
	235	M48T59_WRITE(mday, M48T59_ALARM_DATE);
	236	M48T59_WRITE(hour, M48T59_ALARM_HOUR);
	237	M48T59_WRITE(min, M48T59_ALARM_MIN);
	238	M48T59_WRITE(sec, M48T59_ALARM_SEC);
	239
	240	/* Clear the WRITE bit */
	241	M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
	242	spin_unlock_irqrestore(&m48t59->lock, flags);
	243
	244	dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
12a9ee3c	245	year + 1900, tm->tm_mon, tm->tm_mday,
2e774c7c MZ	246	tm->tm_hour, tm->tm_min, tm->tm_sec);
	247	return 0;
	248	}
	249
	250	/*
	251	* Handle commands from user-space
	252	*/
16380c15	253	static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
2e774c7c	254	{
85368bb9 WS	255	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	256	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c	257	unsigned long flags;
2e774c7c MZ	258
2e774c7c MZ	259	spin_lock_irqsave(&m48t59->lock, flags);
16380c15	260	if (enabled)
2e774c7c	261	M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
16380c15 JS	262	else
16380c15 JS	263	M48T59_WRITE(0x00, M48T59_INTR);
2e774c7c MZ	264	spin_unlock_irqrestore(&m48t59->lock, flags);
2e774c7c MZ	265
16380c15	266	return 0;
2e774c7c MZ	267	}
	268
	269	static int m48t59_rtc_proc(struct device dev, struct seq_file seq)
	270	{
85368bb9 WS	271	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	272	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	273	unsigned long flags;
	274	u8 val;
	275
	276	spin_lock_irqsave(&m48t59->lock, flags);
	277	val = M48T59_READ(M48T59_FLAGS);
	278	spin_unlock_irqrestore(&m48t59->lock, flags);
	279
	280	seq_printf(seq, "battery\t\t: %s\n",
	281	(val & M48T59_FLAGS_BF) ? "low" : "normal");
	282	return 0;
	283	}
	284
	285	/*
	286	* IRQ handler for the RTC
	287	*/
	288	static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
	289	{
	290	struct device dev = (struct device )dev_id;
85368bb9 WS	291	struct m48t59_plat_data *pdata = dev_get_platdata(dev);
85368bb9 WS	292	struct m48t59_private *m48t59 = dev_get_drvdata(dev);
2e774c7c MZ	293	u8 event;
	294
	295	spin_lock(&m48t59->lock);
	296	event = M48T59_READ(M48T59_FLAGS);
	297	spin_unlock(&m48t59->lock);
	298
	299	if (event & M48T59_FLAGS_AF) {
	300	rtc_update_irq(m48t59->rtc, 1, (RTC_AF \| RTC_IRQF));
	301	return IRQ_HANDLED;
	302	}
	303
	304	return IRQ_NONE;
	305	}
	306
	307	static const struct rtc_class_ops m48t59_rtc_ops = {
2e774c7c MZ	308	.read_time = m48t59_rtc_read_time,
	309	.set_time = m48t59_rtc_set_time,
	310	.read_alarm = m48t59_rtc_readalarm,
	311	.set_alarm = m48t59_rtc_setalarm,
	312	.proc = m48t59_rtc_proc,
16380c15	313	.alarm_irq_enable = m48t59_rtc_alarm_irq_enable,
2e774c7c MZ	314	};
2e774c7c MZ	315
94fe7424 KH	316	static const struct rtc_class_ops m48t02_rtc_ops = {
	317	.read_time = m48t59_rtc_read_time,
	318	.set_time = m48t59_rtc_set_time,
	319	};
	320
0ff3565d AB	321	static int m48t59_nvram_read(void priv, unsigned int offset, void val,
0ff3565d AB	322	size_t size)
2e774c7c	323	{
0ff3565d AB	324	struct platform_device *pdev = priv;
0ff3565d AB	325	struct device *dev = &pdev->dev;
8136032b	326	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
2e774c7c MZ	327	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	328	ssize_t cnt = 0;
	329	unsigned long flags;
0ff3565d	330	u8 *buf = val;
2e774c7c	331
99be3e37 VZ	332	spin_lock_irqsave(&m48t59->lock, flags);
	333
	334	for (; cnt < size; cnt++)
2e774c7c	335	*buf++ = M48T59_READ(cnt);
99be3e37 VZ	336
99be3e37 VZ	337	spin_unlock_irqrestore(&m48t59->lock, flags);
2e774c7c	338
0ff3565d	339	return 0;
2e774c7c MZ	340	}
2e774c7c MZ	341
0ff3565d AB	342	static int m48t59_nvram_write(void priv, unsigned int offset, void val,
0ff3565d AB	343	size_t size)
2e774c7c	344	{
0ff3565d AB	345	struct platform_device *pdev = priv;
0ff3565d AB	346	struct device *dev = &pdev->dev;
8136032b	347	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
2e774c7c MZ	348	struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
	349	ssize_t cnt = 0;
	350	unsigned long flags;
0ff3565d	351	u8 *buf = val;
2e774c7c	352
99be3e37 VZ	353	spin_lock_irqsave(&m48t59->lock, flags);
	354
	355	for (; cnt < size; cnt++)
2e774c7c	356	M48T59_WRITE(*buf++, cnt);
99be3e37 VZ	357
99be3e37 VZ	358	spin_unlock_irqrestore(&m48t59->lock, flags);
2e774c7c	359
0ff3565d	360	return 0;
2e774c7c MZ	361	}
2e774c7c MZ	362
5a167f45	363	static int m48t59_rtc_probe(struct platform_device *pdev)
2e774c7c	364	{
8136032b	365	struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
2e774c7c MZ	366	struct m48t59_private *m48t59 = NULL;
	367	struct resource *res;
	368	int ret = -ENOMEM;
94fe7424	369	const struct rtc_class_ops *ops;
0ff3565d AB	370	struct nvmem_config nvmem_cfg = {
	371	.name = "m48t59-",
	372	.word_size = 1,
	373	.stride = 1,
	374	.reg_read = m48t59_nvram_read,
	375	.reg_write = m48t59_nvram_write,
	376	.priv = pdev,
	377	};
2e774c7c MZ	378
	379	/* This chip could be memory-mapped or I/O-mapped */
	380	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	381	if (!res) {
	382	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	383	if (!res)
	384	return -EINVAL;
	385	}
	386
	387	if (res->flags & IORESOURCE_IO) {
	388	/* If we are I/O-mapped, the platform should provide
	389	* the operations accessing chip registers.
	390	*/
	391	if (!pdata \|\| !pdata->write_byte \|\| !pdata->read_byte)
	392	return -EINVAL;
	393	} else if (res->flags & IORESOURCE_MEM) {
	394	/* we are memory-mapped */
	395	if (!pdata) {
19b8d887 JH	396	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata),
19b8d887 JH	397	GFP_KERNEL);
2e774c7c MZ	398	if (!pdata)
	399	return -ENOMEM;
	400	/* Ensure we only kmalloc platform data once */
	401	pdev->dev.platform_data = pdata;
	402	}
94fe7424 KH	403	if (!pdata->type)
94fe7424 KH	404	pdata->type = M48T59RTC_TYPE_M48T59;
2e774c7c MZ	405
	406	/* Try to use the generic memory read/write ops */
	407	if (!pdata->write_byte)
	408	pdata->write_byte = m48t59_mem_writeb;
	409	if (!pdata->read_byte)
	410	pdata->read_byte = m48t59_mem_readb;
	411	}
	412
19b8d887	413	m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL);
2e774c7c MZ	414	if (!m48t59)
	415	return -ENOMEM;
	416
64151ad5 KH	417	m48t59->ioaddr = pdata->ioaddr;
	418
	419	if (!m48t59->ioaddr) {
	420	/* ioaddr not mapped externally */
19b8d887 JH	421	m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start,
19b8d887 JH	422	resource_size(res));
64151ad5	423	if (!m48t59->ioaddr)
19b8d887	424	return ret;
64151ad5	425	}
2e774c7c MZ	426
	427	/* Try to get irq number. We also can work in
	428	* the mode without IRQ.
	429	*/
	430	m48t59->irq = platform_get_irq(pdev, 0);
2fac6674	431	if (m48t59->irq <= 0)
2e774c7c MZ	432	m48t59->irq = NO_IRQ;
	433
	434	if (m48t59->irq != NO_IRQ) {
19b8d887 JH	435	ret = devm_request_irq(&pdev->dev, m48t59->irq,
	436	m48t59_rtc_interrupt, IRQF_SHARED,
	437	"rtc-m48t59", &pdev->dev);
2e774c7c	438	if (ret)
19b8d887	439	return ret;
2e774c7c	440	}
94fe7424 KH	441	switch (pdata->type) {
94fe7424 KH	442	case M48T59RTC_TYPE_M48T59:
94fe7424 KH	443	ops = &m48t59_rtc_ops;
	444	pdata->offset = 0x1ff0;
	445	break;
	446	case M48T59RTC_TYPE_M48T02:
94fe7424 KH	447	ops = &m48t02_rtc_ops;
	448	pdata->offset = 0x7f0;
	449	break;
	450	case M48T59RTC_TYPE_M48T08:
94fe7424 KH	451	ops = &m48t02_rtc_ops;
	452	pdata->offset = 0x1ff0;
	453	break;
	454	default:
	455	dev_err(&pdev->dev, "Unknown RTC type\n");
19b8d887	456	return -ENODEV;
94fe7424	457	}
2e774c7c	458
b74d2caa AZ	459	spin_lock_init(&m48t59->lock);
	460	platform_set_drvdata(pdev, m48t59);
	461
affb842b	462	m48t59->rtc = devm_rtc_allocate_device(&pdev->dev);
19b8d887 JH	463	if (IS_ERR(m48t59->rtc))
19b8d887 JH	464	return PTR_ERR(m48t59->rtc);
2e774c7c	465
0ff3565d	466	m48t59->rtc->nvram_old_abi = true;
affb842b AB	467	m48t59->rtc->ops = ops;
affb842b AB	468
0ff3565d AB	469	nvmem_cfg.size = pdata->offset;
0ff3565d AB	470	ret = rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
affb842b AB	471	if (ret)
	472	return ret;
	473
0ff3565d	474	ret = rtc_register_device(m48t59->rtc);
19b8d887 JH	475	if (ret)
19b8d887 JH	476	return ret;
2e774c7c	477
2e774c7c	478	return 0;
2e774c7c MZ	479	}
2e774c7c MZ	480
ad28a07b KS	481	/* work with hotplug and coldplug */
	482	MODULE_ALIAS("platform:rtc-m48t59");
	483
12730926	484	static struct platform_driver m48t59_rtc_driver = {
2e774c7c MZ	485	.driver = {
2e774c7c MZ	486	.name = "rtc-m48t59",
2e774c7c MZ	487	},
2e774c7c MZ	488	.probe = m48t59_rtc_probe,
2e774c7c MZ	489	};
2e774c7c MZ	490
0c4eae66	491	module_platform_driver(m48t59_rtc_driver);
2e774c7c MZ	492
2e774c7c MZ	493	MODULE_AUTHOR("Mark Zhan <rongkai.zhan@windriver.com>");
94fe7424	494	MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver");
2e774c7c	495	MODULE_LICENSE("GPL");